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| author | Daniel Hellstrom <daniel@gaisler.com> | 2016-03-22 11:42:10 +0100 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2017-03-06 07:54:55 +0100 |
| commit | c442647f9d0755f1dfeaef903cc5e054dac29d82 (patch) | |
| tree | e81b34d9ec2ec5a7a09e8b33a428b5a9ee67bcd3 | |
| parent | leon, gptimer: start/reset must take RS and IP into account (diff) | |
| download | rtems-c442647f9d0755f1dfeaef903cc5e054dac29d82.tar.bz2 | |
leon, grspw_pkt: code style clean-ups
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c b/c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c index 6d2cefb2b6..e23410acbc 100644 --- a/c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c +++ b/c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c @@ -545,6 +545,7 @@ void *grspw_open(int dev_no) * channels. Max-size descriptor area is allocated (or user assigned): * - 128 RX descriptors per DMA Channel * - 64 TX descriptors per DMA Channel + * Specified address must be in CPU RAM. */ bdtabsize = 2 * BDTAB_SIZE * priv->hwsup.ndma_chans; value = drvmgr_dev_key_get(priv->dev, "bdDmaArea", DRVMGR_KT_INT); @@ -827,14 +828,14 @@ void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data) */ void grspw_tc_time(void *d, int *time) { - struct grspw_priv *priv = d; - struct grspw_regs *regs = priv->regs; + struct grspw_priv *priv = d; + struct grspw_regs *regs = priv->regs; - if (time == NULL) - return; - if (*time != -1) - REG_WRITE(®s->time, *time & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL)); - *time = REG_READ(®s->time) & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL); + if (time == NULL) + return; + if (*time != -1) + REG_WRITE(®s->time, *time & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL)); + *time = REG_READ(®s->time) & (GRSPW_TIME_TCNT | GRSPW_TIME_CTRL); } /* Generate Tick-In for the given Interrupt-code and check for generation @@ -1832,7 +1833,7 @@ int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count) } /* 3. Schedule as many packets as possible (SEND->SCHED) */ - if ((started > 0 ) && ((opts & 2) == 0)) + if ((started > 0) && ((opts & 2) == 0)) grspw_tx_schedule_send(dma); /* Unlock DMA channel */ |