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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 15:15:46 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 15:17:07 +0100 |
commit | bfdfc979fd272111b783986dbe1fc2f8ba14a466 (patch) | |
tree | 4448273079a66b578fac01c10711f6995a764884 | |
parent | arm: Fix Armv7-M TLS support (diff) | |
download | rtems-bfdfc979fd272111b783986dbe1fc2f8ba14a466.tar.bz2 |
bsps/riscv: Fix PLIC enable register count
Each PLIC enable register has 32 bits, so we have to divide by 32.
-rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index 6fcaee172e..74d833eac8 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -245,10 +245,10 @@ static void riscv_plic_init(const void *fdt) uint32_t cpu_index; /* - * Interrupt enable registers with 32-bit alignment based on + * Interrupt enable registers with 32-bit alignment based on * number of interrupts. */ - enable_register_count = RTEMS_ALIGN_UP(ndev, 32); + enable_register_count = RTEMS_ALIGN_UP(ndev, 32) / 32; hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); |