summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSebastian Huber <sebastian.huber@embedded-brains.de>2014-11-13 10:12:32 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2014-11-20 10:30:20 +0100
commitbdf8fa76c24f563c1d1287e24bfa65c0d2186588 (patch)
tree18322a9213db50993d286997d9468772eff4cd18
parentbsp/xilinx-zynq: Rename BSP_ARM_A9MPCORE_UARTCLK (diff)
downloadrtems-bdf8fa76c24f563c1d1287e24bfa65c0d2186588.tar.bz2
bsp/xilinx-zynq: Add zync_clock_cpu_1x()
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/configure.ac5
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h4
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c7
3 files changed, 14 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
index a6f16cc502..580049a621 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
@@ -34,6 +34,11 @@ RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL])
RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL])
RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz])
+RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U])
+RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U])
+RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U])
+RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz])
+
USE_FAST_IDLE=0
AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1])
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
index d2c0bbb416..9a0bfd27a7 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -67,6 +67,8 @@ extern "C" {
*/
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
+uint32_t zynq_clock_cpu_1x(void);
+
/** @} */
#ifdef __cplusplus
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c
index 0be515c057..ad66640861 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -17,6 +17,11 @@
#include <bsp/arm-a9mpcore-clock.h>
#include <bsp/irq-generic.h>
+__attribute__ ((weak)) uint32_t zynq_clock_cpu_1x(void)
+{
+ return ZYNQ_CLOCK_CPU_1X;
+}
+
void bsp_start(void)
{
a9mpcore_clock_initialize_early();