diff options
| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-04-17 09:43:30 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-17 13:25:11 +0200 |
| commit | 9ee2ec56b5758b5921fe0b5be1ad14a3f23bbc1d (patch) | |
| tree | 75cef8578297b5905e628b9900958b57cbeb9d5e | |
| parent | bsp/arm: RTEMS_SMP to arm erratum 764369 detection (diff) | |
| download | rtems-9ee2ec56b5758b5921fe0b5be1ad14a3f23bbc1d.tar.bz2 | |
bsp/arm: Consistenly same handling for flushing
It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 72d3ee31cf..77069bd1df 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -252,8 +252,8 @@ static inline void arm_cache_l1_flush_data_range( ARM_CACHE_L1_ERRATA_764369_HANDLER(); for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { - /* Store the Data cache line */ - arm_cp15_data_cache_clean_line( (void*)adx ); + /* Store and invalidate the Data cache line */ + arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx ); } /* Wait for L1 store to complete */ _ARM_Data_synchronization_barrier(); |