smp: Use ISR lock in per-CPU control

Rename _Per_CPU_Lock_acquire() to _Per_CPU_ISR_disable_and_acquire().
Rename _Per_CPU_Lock_release() to _Per_CPU_Release_and_ISR_enable().

Add _Per_CPU_Acquire() and _Per_CPU_Release().

2 files changed, 25 insertions, 17 deletions

diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h
index e6713bf502..6e3a18e6db 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -23,9 +23,8 @@
   #include <rtems/asm.h>
 #else
   #include <rtems/score/assert.h>
-  #include <rtems/score/isrlevel.h>
+  #include <rtems/score/isrlock.h>
   #include <rtems/score/timestamp.h>
-  #include <rtems/score/smplock.h>
   #include <rtems/score/smp.h>
 #endif
 
@@ -179,10 +178,13 @@ typedef struct {
   /** This is the time of the last context switch on this CPU. */
   Timestamp_Control time_of_last_context_switch;
 
-  #if defined( RTEMS_SMP )
-    /** This element is used to lock this structure */
-    SMP_lock_Control lock;
+  /**
+   * @brief This lock protects the dispatch_necessary, executing, heir and
+   * message fields.
+   */
+  ISR_lock_Control lock;
 
+  #if defined( RTEMS_SMP )
     /**
      *  This is the request for the interrupt.
      *
@@ -220,6 +222,18 @@ typedef struct {
  */
 extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
 
+#define _Per_CPU_ISR_disable_and_acquire( per_cpu, isr_cookie ) \
+  _ISR_lock_ISR_disable_and_acquire( &( per_cpu )->lock, isr_cookie )
+
+#define _Per_CPU_Release_and_ISR_enable( per_cpu, isr_cookie ) \
+  _ISR_lock_Release_and_ISR_enable( &( per_cpu )->lock, isr_cookie )
+
+#define _Per_CPU_Acquire( per_cpu ) \
+  _ISR_lock_Acquire( &( per_cpu )->lock )
+
+#define _Per_CPU_Release( per_cpu ) \
+  _ISR_lock_Release( &( per_cpu )->lock )
+
 #if defined( RTEMS_SMP )
 static inline Per_CPU_Control *_Per_CPU_Get( void )
 {
@@ -275,12 +289,6 @@ void _Per_CPU_Wait_for_state(
   Per_CPU_State desired_state
 );
 
-#define _Per_CPU_Lock_acquire( per_cpu, isr_cookie ) \
-  _SMP_lock_ISR_disable_and_acquire( &( per_cpu )->lock, isr_cookie )
-
-#define _Per_CPU_Lock_release( per_cpu, isr_cookie ) \
-  _SMP_lock_Release_and_ISR_enable( &( per_cpu )->lock, isr_cookie )
-
 #endif /* defined( RTEMS_SMP ) */
 
 /*
diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c
index 4f7229092c..c254631048 100644
--- a/cpukit/score/src/smp.c
+++ b/cpukit/score/src/smp.c
@@ -53,10 +53,10 @@ void rtems_smp_process_interrupt( void )
     uint32_t  message;
     ISR_Level level;
 
-    _Per_CPU_Lock_acquire( self_cpu, level );
+    _Per_CPU_ISR_disable_and_acquire( self_cpu, level );
     message = self_cpu->message;
     self_cpu->message = 0;
-    _Per_CPU_Lock_release( self_cpu, level );
+    _Per_CPU_Release_and_ISR_enable( self_cpu, level );
 
     #if defined(RTEMS_DEBUG)
       {
@@ -100,9 +100,9 @@ void _SMP_Send_message( uint32_t cpu, uint32_t message )
       printk( "Send 0x%x to %d\n", message, cpu );
   #endif
 
-  _Per_CPU_Lock_acquire( per_cpu, level );
+  _Per_CPU_ISR_disable_and_acquire( per_cpu, level );
   per_cpu->message |= message;
-  _Per_CPU_Lock_release( per_cpu, level );
+  _Per_CPU_Release_and_ISR_enable( per_cpu, level );
 
   _CPU_SMP_Send_interrupt( cpu );
 }
@@ -118,9 +118,9 @@ void _SMP_Broadcast_message( uint32_t message )
       Per_CPU_Control *per_cpu = _Per_CPU_Get_by_index( cpu );
       ISR_Level level;
 
-      _Per_CPU_Lock_acquire( per_cpu, level );
+      _Per_CPU_ISR_disable_and_acquire( per_cpu, level );
       per_cpu->message |= message;
-      _Per_CPU_Lock_release( per_cpu, level );
+      _Per_CPU_Release_and_ISR_enable( per_cpu, level );
     }
   }