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| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-05-28 14:47:02 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-05-28 14:59:01 +0200 |
| commit | 5fd4e35f9b606321243a833ba5af7175fad6d33d (patch) | |
| tree | 0db90426d34603e85899892f7588a6a64345feea | |
| parent | score: Multiprocessor Resource Sharing Protocol (diff) | |
| download | rtems-5fd4e35f9b606321243a833ba5af7175fad6d33d.tar.bz2 | |
bsp/arm: Broadcast cache maintenances
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h index 578c842b0b..97977ba8ab 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h @@ -108,7 +108,7 @@ BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) /* Enable cache coherency support for this processor */ { uint32_t actlr = arm_cp15_get_auxiliary_control(); - actlr |= ARM_CORTEX_A9_ACTL_SMP; + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; arm_cp15_set_auxiliary_control(actlr); } #endif |