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| author | Thomas Dörfler <thomas.doerfler@embedded-brains.de> | 2019-01-10 07:29:54 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-01-10 08:12:16 +0100 |
| commit | 0abe47f142691910cae4e8a8b0544e63c14a5516 (patch) | |
| tree | 3ca0a6311c540d7b21c4ccea473fb994b68503ff | |
| parent | riscv: Enable robust thread dispatch (diff) | |
| download | rtems-0abe47f142691910cae4e8a8b0544e63c14a5516.tar.bz2 | |
bsps/arm: Fix typo in disable cache for ARMv7-AR
Update #3667.
| -rw-r--r-- | bsps/arm/shared/cache/cache-v7ar-disable-data.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S index b275c1d484..4b20fb268f 100644 --- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S +++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S @@ -73,7 +73,7 @@ FUNCTION_ENTRY(rtems_cache_disable_data) /* Read CCSIDR */ lsl r4, r3, #1 - mcr p15, 2, r5, c0, c0, 0 + mcr p15, 2, r4, c0, c0, 0 isb mrc p15, 1, r5, c0, c0, 0 |