lwip: Add bbb and tms570 drivers

+ Add networking01 and telnetd01 tests

68 files changed, 24194 insertions, 93 deletions

diff --git a/COPYING.cpsw b/COPYING.cpsw
new file mode 100644
index 0000000..decb195
--- /dev/null
+++ b/COPYING.cpsw
@@ -0,0 +1,33 @@
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
diff --git a/COPYING.rtemslwip b/COPYING.rtemslwip
new file mode 100644
index 0000000..d971823
--- /dev/null
+++ b/COPYING.rtemslwip
@@ -0,0 +1,23 @@
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
diff --git a/ORIGIN.cpsw b/ORIGIN.cpsw
new file mode 100644
index 0000000..033a9c9
--- /dev/null
+++ b/ORIGIN.cpsw
@@ -0,0 +1,2 @@
+The files under the cpsw/ directory are sourced from:
+https://github.com/ragunath3252/cpsw-lwip.git
diff --git a/ORIGIN.rtemslwip b/ORIGIN.rtemslwip
new file mode 100644
index 0000000..d3735b5
--- /dev/null
+++ b/ORIGIN.rtemslwip
@@ -0,0 +1 @@
+The files under the rtemslwip/ directory are either written specifically for this project or pulled with modifications from the RTEMS project.
diff --git a/cpsw/src/delay.c b/cpsw/src/delay.c
new file mode 100644
index 0000000..8aa0684
--- /dev/null
+++ b/cpsw/src/delay.c
@@ -0,0 +1,8 @@
+void delay(unsigned int ms)
+{
+	ms*=80000u;
+	while (--ms)
+	{
+		__asm__("");
+	}
+}
\ No newline at end of file
diff --git a/cpsw/src/include/FILES b/cpsw/src/include/FILES
new file mode 100755
index 0000000..4e3a47d
--- /dev/null
+++ b/cpsw/src/include/FILES
@@ -0,0 +1,4 @@
+arch/       - Include files for architecture.
+netif/      - Include files for CPSW network interfaces.
+
+See also the FILES file in each subdirectory.
diff --git a/cpsw/src/include/beaglebone.h b/cpsw/src/include/beaglebone.h
new file mode 100755
index 0000000..fdb5043
--- /dev/null
+++ b/cpsw/src/include/beaglebone.h
@@ -0,0 +1,134 @@
+/**
+ * \file   beaglebone.h
+ *
+ * \brief  This file contains prototype declarations of functions which 
+ *         performs EVM configurations.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _BEALGEBONE_H_
+#define _BEAGLEBONE_H_
+
+#include <libcpu/am335x.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+**                    INTERNAL MACRO DEFINITIONS
+*****************************************************************************/
+#define CTRL_NUM_IOPAD_REGS                 (211)
+
+#define BBB_BOARD_NAME                      ("A335BON")
+#define BBB_A1_VERSION                      ("00A1")
+#define BBB_A2_VERSION                      ("00A2")
+#define BBB_A3_VERSION                      ("00A3")
+#define BBB_A5_VERSION                      ("00A5")
+#define BBB_A6_VERSION                      ("00A6")
+#define BOARD_ID_BBB_A1                     (0x1)
+#define BOARD_ID_BBB_A2                     (0x2)
+#define BOARD_ID_BBB_A3                     (0x3)
+#define BOARD_ID_BBB_A5                     (0x4)
+#define BOARD_ID_BBB_A6                     (0x5)
+
+/*
+** Structure to map selection of IO Pad for power down configuration
+*/
+typedef struct ioPadMap {
+    unsigned int ioPad;
+    unsigned int sel;
+}tIOPadMap;
+
+/*
+** Structure to store the control register context. More registers
+** can be added to this if need to be saved.
+*/
+typedef struct ctrlRegContext {
+    unsigned int pwmssctrl;
+    unsigned int gmiisel;
+    tIOPadMap ioPadMap[CTRL_NUM_IOPAD_REGS];
+}CTRLREGCONTEXT;
+
+/*****************************************************************************
+**                    FUNCTION PROTOTYPES
+*****************************************************************************/
+
+extern unsigned int BoardInfoCheck(unsigned char *boardId,
+                                   unsigned char *boardVer);
+extern void ControlRegContextSave(CTRLREGCONTEXT *contextPtr);
+extern void ControlRegContextRestore(CTRLREGCONTEXT *contextPtr);
+extern void GPIO1ModuleClkConfig(void);
+extern void GPIO1Pin23PinMuxSetup(void);
+extern void GPIO0ModuleClkConfig(void);
+extern void UART0ModuleClkConfig(void);
+extern void UARTPinMuxSetup(unsigned int instanceNum);
+extern void CPSWPinMuxSetup(void);
+extern void CPSWClkEnable(void);
+extern unsigned int RTCRevisionInfoGet(void);
+extern void EDMAModuleClkConfig(void);
+extern void EVMMACAddrGet(unsigned int addrIdx, unsigned char *macAddr);
+extern void WatchdogTimer1ModuleClkConfig(void);
+extern void DMTimer2ModuleClkConfig(void);
+extern void DMTimer3ModuleClkConfig(void);
+extern void DMTimer4ModuleClkConfig(void);
+extern void DMTimer6ModuleClkConfig(void);
+extern void DMTimer7ModuleClkConfig(void);
+extern void DMTimer1msModuleClkConfig(unsigned int clkselect);
+extern void EVMPortMIIModeSelect(void);
+extern void RTCModuleClkConfig(void);
+extern void HSMMCSDModuleClkConfig(void);
+extern void HSMMCSDPinMuxSetup(void);
+extern void I2C0ModuleClkConfig(void);
+extern void I2C1ModuleClkConfig(void);
+extern void I2CPinMuxSetup(unsigned int instance);
+extern void GpioPinMuxSetup(unsigned int offsetAddr,
+                            unsigned int padConfValue);
+extern void IOPadContextSave(CTRLREGCONTEXT *contextPtr, unsigned int ioPadOff);
+extern void IOPadContextRestore(CTRLREGCONTEXT *contextPtr,
+                                unsigned int ioPadOff);
+void IOPadConfigure(unsigned int ioPadOff, unsigned int ioPadValue);
+void IOPadSelConfigure(CTRLREGCONTEXT *contextPtr, unsigned int ioPadValue);
+void IOPadSel(CTRLREGCONTEXT *contextPtr, unsigned int ioPadOff,
+              unsigned int ioPadSel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/******************************** End of file *******************************/
diff --git a/cpsw/src/include/cache.h b/cpsw/src/include/cache.h
new file mode 100755
index 0000000..97a596a
--- /dev/null
+++ b/cpsw/src/include/cache.h
@@ -0,0 +1,85 @@
+/*
+ *  \file   cache.h
+ *
+ *  \brief  Cache related function prototypes
+ *
+ *  This file contains the API prototypes for configuring ARMv7a Cache.
+*/
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/*
+** Macros which can be passed to CacheDisable/Enable APIs
+*/
+#define CACHE_ICACHE                 (0x01) /* Instruction cache */
+#define CACHE_DCACHE                 (0x02) /* Data and Unified cache*/
+#define CACHE_ALL                    (0x03) /* Instruction, Data and Unified
+                                               Cache at all levels*/
+
+/*****************************************************************************/
+/*
+** API prototypes
+*/
+extern void CacheEnable(unsigned int enFlag);
+extern void CacheDisable(unsigned int disFlag);
+extern void CacheInstInvalidateAll(void);
+extern void CacheInstInvalidateBuff(unsigned int startAddr,
+                                    unsigned int numBytes);
+extern void CacheDataCleanInvalidateAll(void);
+extern void CacheDataCleanAll(void);
+extern void CacheDataInvalidateAll(void);
+extern void CacheDataCleanBuff(unsigned int startAddr,
+                               unsigned int numBytes);
+
+extern void CacheDataInvalidateBuff(unsigned int startAddr,
+                                    unsigned int numBytes);
+
+extern void CacheDataCleanInvalidateBuff(unsigned int startAddr,
+                                         unsigned int numBytes);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CACHE_H__ */
+
diff --git a/cpsw/src/include/cp15.h b/cpsw/src/include/cp15.h
new file mode 100755
index 0000000..e618d9c
--- /dev/null
+++ b/cpsw/src/include/cp15.h
@@ -0,0 +1,97 @@
+/**
+ *  \file   cp15.h
+ *
+ *  \brief  CP15 related function prototypes
+ *
+ *  This file contains the API prototypes for configuring CP15
+*/
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef __CP15_H
+#define __CP15_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/*
+** Macros which can be passed to CP15ControlFeatureDisable/Enable APIs 
+** as 'features'. Any, or an OR combination of the below macros can be
+** passed to disable/enable the corresponding feature.
+*/
+#define CP15_CONTROL_TEXREMAP                  (0x10000000) 
+#define CP15_CONTROL_ACCESSFLAG                (0x20000000)
+#define CP15_CONTROL_ALIGN_CHCK                (0x00000002)
+#define CP15_CONTROL_MMU                       (0x00000001)
+
+/*****************************************************************************/
+/*
+** API prototypes
+*/
+extern void CP15AuxControlFeatureEnable(unsigned int enFlag);
+extern void CP15AuxControlFeatureDisable(unsigned int disFlag);
+extern void CP15DCacheCleanBuff(unsigned int bufPtr, unsigned int size);
+extern void CP15DCacheCleanFlushBuff(unsigned int bufPtr, unsigned int size);
+extern void CP15DCacheFlushBuff(unsigned int bufPtr, unsigned int size);
+extern void CP15ICacheFlushBuff(unsigned int bufPtr, unsigned int size);
+extern void CP15ICacheDisable(void);
+extern void CP15DCacheDisable(void);
+extern void CP15ICacheEnable(void);
+extern void CP15DCacheEnable(void);
+extern void CP15DCacheCleanFlush(void);
+extern void CP15DCacheClean(void);
+extern void CP15DCacheFlush(void);
+extern void CP15ICacheFlush(void);
+extern void CP15Ttb0Set(unsigned int ttb);
+extern void CP15TlbInvalidate(void);
+extern void CP15MMUDisable(void);
+extern void CP15MMUEnable(void);
+extern void CP15VectorBaseAddrSet(unsigned int addr);
+extern void CP15BranchPredictorInvalidate(void);
+extern void CP15BranchPredictionEnable(void);
+extern void CP15BranchPredictionDisable(void);
+extern void CP15DomainAccessClientSet(void);
+extern void CP15ControlFeatureDisable(unsigned int features);
+extern void CP15ControlFeatureEnable(unsigned int features);
+extern void CP15TtbCtlTtb0Config(void);
+extern unsigned int CP15MainIdPrimPartNumGet(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __CP15_H__ */
diff --git a/cpsw/src/include/cpsw.h b/cpsw/src/include/cpsw.h
new file mode 100755
index 0000000..c059f9c
--- /dev/null
+++ b/cpsw/src/include/cpsw.h
@@ -0,0 +1,380 @@
+/**
+ *  \file   cpsw.h
+ *
+ *  \brief  CPSW APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __CPSW_H__
+#define __CPSW_H__
+
+#include "hw_cpsw_ale.h"
+#include "hw_cpsw_cpdma.h"
+#include "hw_cpsw_port.h"
+#include "hw_cpsw_sl.h"
+#include "hw_cpsw_ss.h"
+#include "hw_cpsw_wr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/*
+** Macros which can be used as 'mode' to pass to the API CPSWSlTransferModeSet
+*/
+#define CPSW_SLIVER_NON_GIG_FULL_DUPLEX        CPSW_SL_MACCONTROL_FULLDUPLEX
+#define CPSW_SLIVER_NON_GIG_HALF_DUPLEX        (0x00u)
+#define CPSW_SLIVER_GIG_FULL_DUPLEX            CPSW_SL_MACCONTROL_GIG
+#define CPSW_SLIVER_INBAND                     CPSW_SL_MACCONTROL_EXT_EN
+
+/*
+** Macros which can be used as 'statFlag' to the API CPSWSlMACStatusGet
+*/
+#define CPSW_SLIVER_STATE                      CPSW_SL_MACSTATUS_IDLE
+#define CPSW_SLIVER_EXT_GIG_INPUT_BIT          CPSW_SL_MACSTATUS_EXT_GIG
+#define CPSW_SLIVER_EXT_FULL_DUPLEX_BIT        CPSW_SL_MACSTATUS_EXT_FULLDUPLEX
+#define CPSW_SLIVER_RX_FLOWCTRL                CPSW_SL_MACSTATUS_RX_FLOW_ACT
+#define CPSW_SLIVER_TX_FLOWCTRL                CPSW_SL_MACSTATUS_TX_FLOW_ACT
+
+/*
+** Macros returned by API CPSWSlMACStatusGet
+*/
+#define CPSW_SLIVER_STATE_IDLE                 CPSW_SL_MACSTATUS_IDLE
+#define CPSW_SLIVER_EXT_GIG_INPUT_HIGH         CPSW_SL_MACSTATUS_EXT_GIG
+#define CPSW_SLIVER_EXT_FULL_DUPLEX_HIGH       CPSW_SL_MACSTATUS_EXT_FULLDUPLEX
+#define CPSW_SLIVER_RX_FLOWCTRL_ACTIVE         CPSW_SL_MACSTATUS_RX_FLOW_ACT
+#define CPSW_SLIVER_TX_FLOWCTRL_ACTIVE         CPSW_SL_MACSTATUS_TX_FLOW_ACT
+
+/*
+** Macros which can be passed asi 'intFlag' to the API CPSWWrCoreIntEnable
+** , CPSWWrCoreIntDisable and CPSWWrCoreIntStatusGet
+*/
+#define CPSW_CORE_INT_RX_THRESH                (0x00u)
+#define CPSW_CORE_INT_RX_PULSE                 (0x04u)
+#define CPSW_CORE_INT_TX_PULSE                 (0x08u)
+#define CPSW_CORE_INT_MISC                     (0x0Cu)
+
+/*
+** Macros which can be passed as 'statFlag' to the API CPSWWrRGMIIStatusGet
+*/
+#define CPSW_RGMII2_DUPLEX                     CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX
+#define CPSW_RGMII2_SPEED                      CPSW_WR_RGMII_CTL_RGMII2_SPEED
+#define CPSW_RGMII2_LINK_STAT                  CPSW_WR_RGMII_CTL_RGMII2_LINK
+#define CPSW_RGMII1_DUPLEX                     CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX
+#define CPSW_RGMII1_SPEED                      CPSW_WR_RGMII_CTL_RGMII1_SPEED
+#define CPSW_RGMII1_LINK_STAT                  CPSW_WR_RGMII_CTL_RGMII1_LINK
+
+/* The values, one of which will be returned by CPSWWrRGMIIStatusGet */
+#define CPSW_RGMII2_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX
+#define CPSW_RGMII2_DUPLEX_HALF                (0x00u)
+#define CPSW_RGMII2_SPEED_10M                  (0x00u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
+#define CPSW_RGMII2_SPEED_100M                 (0x01u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
+#define CPSW_RGMII2_SPEED_1000M                (0x02u << CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT)
+#define CPSW_RGMII2_LINK_UP                    CPSW_WR_RGMII_CTL_RGMII2_LINK
+#define CPSW_RGMII2_LINK_DOWN                  (0x00u)
+#define CPSW_RGMII1_DUPLEX_FULL                CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX
+#define CPSW_RGMII1_DUPLEX_HALF                (0x00u)
+#define CPSW_RGMII1_SPEED_10M                  (0x00u << CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT)
+#define CPSW_RGMII1_SPEED_100M                 (0x01u << CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT)
+#define CPSW_RGMII1_SPEED_1000M                (0x02u << CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT)
+#define CPSW_RGMII1_LINK_UP                    CPSW_WR_RGMII_CTL_RGMII1_LINK
+#define CPSW_RGMII1_LINK_DOWN                  (0x00u)
+
+/*
+** Macros which can be passed as 'pacFlag' to the API CPSWWrIntPacingEnable
+** CPSWWrIntPacingDisable
+*/
+#define CPSW_INT_PACING_C0_RX_PULSE            (0x01 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+#define CPSW_INT_PACING_C0_TX_PULSE            (0x02 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+#define CPSW_INT_PACING_C1_RX_PULSE            (0x04 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+#define CPSW_INT_PACING_C1_TX_PULSE            (0x08 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+#define CPSW_INT_PACING_C2_RX_PULSE            (0x10 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+#define CPSW_INT_PACING_C2_TX_PULSE            (0x20 << CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT)
+
+/*
+** Macros which can be passed as 'portState' to CPSWALEPortStateSet
+*/
+#define CPSW_ALE_PORT_STATE_FWD                (0x03u)
+#define CPSW_ALE_PORT_STATE_LEARN              (0x02u)
+#define CPSW_ALE_PORT_STATE_BLOCKED            (0x01u)
+#define CPSW_ALE_PORT_STATE_DISABLED           (0x00u)
+
+/*
+** Macros which can be passed as 'eoiFlag' to CPSWCPDMAEndOfIntVectorWrite
+*/
+#define CPSW_EOI_TX_PULSE                      (0x02u)
+#define CPSW_EOI_RX_PULSE                      (0x01u)
+#define CPSW_EOI_RX_THRESH_PULSE               (0x00u)
+#define CPSW_EOI_MISC_PULSE                    (0x03u)
+
+/*
+** Macro which can be passed as 'statFlag' to CPSWCPDMAStatusGet
+** The same value can be used to compare against the idle status
+*/
+#define CPDMA_STAT_IDLE                        (CPSW_CPDMA_DMASTATUS_IDLE)
+
+/*
+** Macro which can be passed as 'statFlag' to CPSWCPDMAStatusGet
+*/
+#define CPDMA_STAT_TX_HOST_ERR_CODE            (CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE)
+
+/* The return values for the above 'statFlag' */
+#define CPDMA_STAT_TX_NO_ERR                   (0x00u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_SOP_ERR                  (0x01u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_OWN_ERR                  (0x02u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_ZERO_DESC                (0x03u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_ZERO_BUF_PTR             (0x04u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_ZERO_BUF_LEN             (0x05u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_TX_PKT_LEN_ERR              (0x06u << CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT)
+
+/*
+** Macro which can be passed as 'statFlag' to CPSWCPDMAStatusGet
+*/
+#define CPDMA_STAT_RX_HOST_ERR_CODE            (CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE)
+
+/* The return values for the above 'statFlag' */
+#define CPDMA_STAT_RX_NO_ERR                   (0x00u << CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_RX_OWN_NOT_SET              (0x02u << CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_RX_ZERO_BUF_PTR             (0x04u << CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_RX_ZERO_BUF_LEN             (0x05u << CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT)
+#define CPDMA_STAT_RX_SOP_BUF_LEN_ERR          (0x06u << CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT)
+
+/*
+** Macros which can be passed as 'statFlag' to CPSWCPDMAStatusGet
+*/
+#define CPDMA_STAT_TX_HOST_ERR_CHAN            (CPSW_CPDMA_DMASTATUS_TX_ERR_CH | 0x10u)
+#define CPDMA_STAT_RX_HOST_ERR_CHAN            (CPSW_CPDMA_DMASTATUS_RX_ERR_CH | 0x08u)
+
+/*
+** Macro which can be passed as 'cfg' to the API CPSWCPDMAConfig
+** The values for individual fields are also listed below.
+*/
+#define CPDMA_CFG(tx_rlim, rx_cef, cmd_idle, rx_offlen_blk, rx_own, tx_ptype) \
+             (tx_rlim | rx_cef | cmd_idle | rx_offlen_blk | rx_own | tx_ptype)
+/* Values for 'tx_rlim' */
+#define CPDMA_CFG_TX_RATE_LIM_CH_7             (0x80u << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_6        (0xC0u << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_5        (0xE0u << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_4        (0xF0u << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_3        (0xF8u << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_2        (0xFCu << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_1        (0xFEu << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+#define CPDMA_CFG_TX_RATE_LIM_CH_7_TO_0        (0xFFu << CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT)
+
+/* Values for 'rx_cef' */
+#define CPDMA_CFG_COPY_ERR_FRAMES              (CPSW_CPDMA_DMACONTROL_RX_CEF)
+#define CPDMA_CFG_NO_COPY_ERR_FRAMES           (0x00u)
+
+/* Values for 'cmd_idle' */
+#define CPDMA_CFG_IDLE_COMMAND                 (CPSW_CPDMA_DMACONTROL_CMD_IDLE)
+#define CPDMA_CFG_IDLE_COMMAND_NONE            (0x00u)
+
+/* Values for 'rx_offlen_blk' */
+#define CPDMA_CFG_BLOCK_RX_OFF_LEN_WRITE       (CPSW_CPDMA_DMACONTROL_RX_OFFLEN_BLOCK)
+#define CPDMA_CFG_NOT_BLOCK_RX_OFF_LEN_WRITE   (0x00u)
+
+/* Values for 'rx_own' */
+#define CPDMA_CFG_RX_OWN_1                     (CPSW_CPDMA_DMACONTROL_RX_OWNERSHIP)
+#define CPDMA_CFG_RX_OWN_0                     (0x00u)
+
+/* Values for 'tx_ptype' */
+#define CPDMA_CFG_TX_PRI_ROUND_ROBIN           (CPSW_CPDMA_DMACONTROL_TX_PTYPE)
+#define CPDMA_CFG_TX_PRI_FIXED                 (0x00u)
+
+/*
+** Macros which can be passed as 'intType' to CPSWCPDMARxIntStatRawGet
+** and CPSWCPDMARxIntStatMaskedGet
+*/
+#define CPDMA_RX_INT_THRESH_PEND               (0x08u)
+#define CPDMA_RX_INT_PULSE_PEND                (0x00u)
+
+#define CPSW_MAX_NUM_ALE_ENTRY                 (1024)
+#define CPSW_SIZE_CPPI_RAM                     (8192)
+
+/*
+** Structure to save CPSW context
+*/
+typedef struct cpswContext {
+    unsigned int aleBase;
+    unsigned int ssBase;
+    unsigned int port1Base;
+    unsigned int port2Base;
+    unsigned int cpdmaBase;
+    unsigned int cppiRamBase;
+    unsigned int wrBase;
+    unsigned int sl1Base;
+    unsigned int sl2Base;
+    unsigned int aleCtrl;
+    unsigned int alePortCtl[3];
+    unsigned int aleEntry[CPSW_MAX_NUM_ALE_ENTRY * 3];
+    unsigned int ssStatPortEn;
+    unsigned int port1SaHi;
+    unsigned int port1SaLo;
+    unsigned int port2SaHi;
+    unsigned int port2SaLo;
+    unsigned int port1TxInCtl;
+    unsigned int port1Vlan;
+    unsigned int port2TxInCtl;
+    unsigned int port2Vlan;
+    unsigned int cpdmaRxFB;
+    unsigned int cpdmaTxCtl;
+    unsigned int cpdmaRxCtl;
+    unsigned int cpdmaRxHdp;
+    unsigned int txIntMaskSet;
+    unsigned int rxIntMaskSet;
+    unsigned int wrCoreIntTxPulse;
+    unsigned int wrCoreIntRxPulse;
+    unsigned int sl1MacCtl;
+    unsigned int sl2MacCtl;
+    unsigned int cppiRam[CPSW_SIZE_CPPI_RAM];
+} CPSWCONTEXT;
+
+/*****************************************************************************/
+/*
+** Prototypes for the APIs
+*/
+extern void CPSWSSReset(unsigned int baseAddr);
+extern void CPSWSlControlExtEnable(unsigned int baseAddr);
+extern void CPSWSlGigModeForceEnable(unsigned int baseAddr);
+extern void CPSWSlGigModeForceDisable(unsigned int baseAddr);
+extern void CPSWSlTransferModeSet(unsigned int baseAddr, unsigned int mode);
+extern unsigned int CPSWSlMACStatusGet(unsigned int baseAddr, unsigned int statFlag);
+extern void CPSWSlReset(unsigned int baseAddr);
+extern void CPSWSlRxMaxLenSet(unsigned int baseAddr, unsigned int rxMaxLen);
+extern void CPSWSlGMIIEnable(unsigned int baseAddr);
+extern void CPSWSlRGMIIEnable(unsigned int baseAddr);
+extern void CPSWWrReset(unsigned int baseAddr);
+extern void CPSWWrControlRegReset(unsigned int baseAddr);
+extern void CPSWWrCoreIntEnable(unsigned int baseAddr, unsigned int core,
+                         unsigned int channel, unsigned int intFlag);
+extern void CPSWWrCoreIntDisable(unsigned int baseAddr, unsigned int core,
+                          unsigned int channel, unsigned int intFlag);
+extern unsigned int CPSWWrCoreIntStatusGet(unsigned int baseAddr, unsigned int core,
+                                    unsigned int channel, unsigned int intFlag);
+extern unsigned int CPSWWrRGMIIStatusGet(unsigned int baseAddr, unsigned int statFlag);
+extern void CPSWALEInit(unsigned int baseAddr);
+extern void CPSWALEPortStateSet(unsigned int baseAddr, unsigned int portNum,
+                         unsigned int portState);
+extern void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx,
+                          unsigned int *aleEntryPtr);
+extern void CPSWALETableEntryGet(unsigned int baseAddr, unsigned int aleTblIdx,
+                          unsigned int *aleEntryPtr);
+extern unsigned int CPSWALEPrescaleGet(unsigned int baseAddr);
+extern void CPSWALEPrescaleSet(unsigned int baseAddr, unsigned int psVal);
+extern void CPSWALEBypassEnable(unsigned int baseAddr);
+extern void CPSWALEBypassDisable(unsigned int baseAddr);
+extern void CPSWRxFlowControlEnable(unsigned int baseAddr, unsigned int portNum);
+extern void CPSWRxFlowControlDisable(unsigned int baseAddr, unsigned int portNum);
+extern void CPSWSoftwareIdleEnable(unsigned int baseAddr);
+extern void CPSWSoftwareIdleDisable(unsigned int baseAddr, unsigned int portNum);
+extern void CPSWStatisticsEnable(unsigned int baseAddr);
+extern void CPSWVLANAwareEnable(unsigned int baseAddr);
+extern void CPSWVLANAwareDisable(unsigned int baseAddr);
+extern void CPSWPortSrcAddrSet(unsigned int baseAddr, unsigned char *ethAddr);
+extern unsigned int CPSWStatisticsGet(unsigned int baseAddr, unsigned int statReg);
+extern void CPSWCPDMAReset(unsigned int baseAddr);
+extern void CPSWCPDMACmdIdleEnable(unsigned int baseAddr);
+extern void CPSWCPDMACmdIdleDisable(unsigned int baseAddr);
+extern void CPSWCPDMATxIntEnable(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMARxIntEnable(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMATxIntDisable(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMARxIntDisable(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMATxEnable(unsigned int baseAddr);
+extern void CPSWCPDMARxEnable(unsigned int baseAddr);
+extern void CPSWCPDMATxHdrDescPtrWrite(unsigned int baseAddr, unsigned int descHdr,
+                                unsigned int channel);
+extern void CPSWCPDMARxHdrDescPtrWrite(unsigned int baseAddr, unsigned int descHdr,
+                                unsigned int channel);
+extern void CPSWCPDMAEndOfIntVectorWrite(unsigned int baseAddr, unsigned int eoiFlag);
+extern unsigned int CPSWCPDMATxCPRead(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMATxCPWrite(unsigned int baseAddr, unsigned int channel,
+                        unsigned int comPtr);
+extern unsigned int CPSWCPDMARxCPRead(unsigned int baseAddr, unsigned int channel);
+extern void CPSWCPDMARxCPWrite(unsigned int baseAddr, unsigned int channel,
+                        unsigned int comPtr);
+extern void CPSWCPDMANumFreeBufSet(unsigned int baseAddr, unsigned int channel,
+                            unsigned int nBuf);
+extern unsigned int CPSWCPDMAStatusGet(unsigned int baseAddr, unsigned int statFlag);
+extern void CPSWCPDMAConfig(unsigned int baseAddr, unsigned int cfg);
+extern void CPSWCPDMARxBufOffsetSet(unsigned int baseAddr, unsigned int bufOff);
+extern unsigned int CPSWCPDMATxIntStatRawGet(unsigned int baseAddr,
+                                      unsigned int chanMask);
+extern unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr,
+                                         unsigned int chanMask);
+extern unsigned int CPSWCPDMARxIntStatRawGet(unsigned int baseAddr,
+                                      unsigned int chanMask,
+                                      unsigned int intType);
+extern unsigned int CPSWCPDMARxIntStatMaskedGet(unsigned int baseAddr,
+                                         unsigned int channel,
+                                         unsigned int intFlag);
+extern void CPSWContextSave(CPSWCONTEXT *contextPtr);
+extern void CPSWContextRestore(CPSWCONTEXT *contextPtr);
+extern void CPSWHostPortDualMacModeSet(unsigned int baseAddr);
+extern void CPSWALEVLANAwareSet(unsigned int baseAddr);
+extern void CPSWALEVLANAwareClear(unsigned int baseAddr);
+extern void CPSWPortVLANConfig(unsigned int baseAddr, unsigned int vlanId,
+                               unsigned int cfiBit, unsigned int vlanPri);
+extern void CPSWALERateLimitTXMode(unsigned int baseAddr);
+extern void CPSWALERateLimitRXMode(unsigned int baseAddr);
+extern void CPSWALERateLimitEnable(unsigned int baseAddr);
+extern void CPSWALERateLimitDisable(unsigned int baseAddr);
+extern void CPSWALEAUTHModeSet(unsigned int baseAddr);
+extern void CPSWALEAUTHModeClear(unsigned int baseAddr);
+extern void CPSWALEUnknownUntaggedEgressSet(unsigned int baseAddr,
+                                            unsigned int ueVal);
+extern void CPSWALEUnknownRegFloodMaskSet(unsigned int baseAddr,
+                                          unsigned int rfmVal);
+extern void CPSWALEUnknownUnRegFloodMaskSet(unsigned int baseAddr,
+                                            unsigned int ufmVal);
+extern void CPSWALEUnknownMemberListSet(unsigned int baseAddr,
+                                        unsigned int mlVal);
+extern void CPSWALEBroadcastRateLimitSet(unsigned int baseAddr,
+                                         unsigned int portNum,
+                                         unsigned int bplVal);
+extern void CPSWALEMulticastRateLimitSet(unsigned int baseAddr,
+                                         unsigned int portNum,
+                                         unsigned int mplVal);
+extern void CPSWALEVIDIngressCheckSet(unsigned int baseAddr,
+                                      unsigned int portNum);
+extern void CPSWALEAgeOut(unsigned int baseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CPSW_H__ */
diff --git a/cpsw/src/include/delay.h b/cpsw/src/include/delay.h
new file mode 100644
index 0000000..507d177
--- /dev/null
+++ b/cpsw/src/include/delay.h
@@ -0,0 +1,4 @@
+#ifndef DELAY_H
+#define DELAY_H
+void delay(unsigned int ms);
+#endif
\ No newline at end of file
diff --git a/cpsw/src/include/hw_cm_per.h b/cpsw/src/include/hw_cm_per.h
new file mode 100755
index 0000000..9a39797
--- /dev/null
+++ b/cpsw/src/include/hw_cm_per.h
@@ -0,0 +1,1407 @@
+
+
+/**
+ *  @Component:   CM
+ *
+ *  @Filename:    ../../CredDataBase/prcmCRED/cm_per_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CM_PER_H_
+#define _HW_CM_PER_H_
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CM_PER_L4LS_CLKSTCTRL   (0x0)
+#define CM_PER_L3S_CLKSTCTRL   (0x4)
+#define CM_PER_L4FW_CLKSTCTRL   (0x8)
+#define CM_PER_L3_CLKSTCTRL   (0xc)
+#define CM_PER_CPGMAC0_CLKCTRL   (0x14)
+#define CM_PER_LCDC_CLKCTRL   (0x18)
+#define CM_PER_USB0_CLKCTRL   (0x1c)
+#define CM_PER_MLB_CLKCTRL   (0x20)
+#define CM_PER_TPTC0_CLKCTRL   (0x24)
+#define CM_PER_EMIF_CLKCTRL   (0x28)
+#define CM_PER_OCMCRAM_CLKCTRL   (0x2c)
+#define CM_PER_GPMC_CLKCTRL   (0x30)
+#define CM_PER_MCASP0_CLKCTRL   (0x34)
+#define CM_PER_UART5_CLKCTRL   (0x38)
+#define CM_PER_MMC0_CLKCTRL   (0x3c)
+#define CM_PER_ELM_CLKCTRL   (0x40)
+#define CM_PER_I2C2_CLKCTRL   (0x44)
+#define CM_PER_I2C1_CLKCTRL   (0x48)
+#define CM_PER_SPI0_CLKCTRL   (0x4c)
+#define CM_PER_SPI1_CLKCTRL   (0x50)
+#define CM_PER_L4LS_CLKCTRL   (0x60)
+#define CM_PER_L4FW_CLKCTRL   (0x64)
+#define CM_PER_MCASP1_CLKCTRL   (0x68)
+#define CM_PER_UART1_CLKCTRL   (0x6c)
+#define CM_PER_UART2_CLKCTRL   (0x70)
+#define CM_PER_UART3_CLKCTRL   (0x74)
+#define CM_PER_UART4_CLKCTRL   (0x78)
+#define CM_PER_TIMER7_CLKCTRL   (0x7c)
+#define CM_PER_TIMER2_CLKCTRL   (0x80)
+#define CM_PER_TIMER3_CLKCTRL   (0x84)
+#define CM_PER_TIMER4_CLKCTRL   (0x88)
+#define CM_PER_RNG_CLKCTRL   (0x90)
+#define CM_PER_AES0_CLKCTRL   (0x94)
+#define CM_PER_SHA0_CLKCTRL   (0xa0)
+#define CM_PER_PKA_CLKCTRL   (0xa4)
+#define CM_PER_GPIO6_CLKCTRL   (0xa8)
+#define CM_PER_GPIO1_CLKCTRL   (0xac)
+#define CM_PER_GPIO2_CLKCTRL   (0xb0)
+#define CM_PER_GPIO3_CLKCTRL   (0xb4)
+#define CM_PER_TPCC_CLKCTRL   (0xbc)
+#define CM_PER_DCAN0_CLKCTRL   (0xc0)
+#define CM_PER_DCAN1_CLKCTRL   (0xc4)
+#define CM_PER_EPWMSS1_CLKCTRL   (0xcc)
+#define CM_PER_EMIF_FW_CLKCTRL   (0xd0)
+#define CM_PER_EPWMSS0_CLKCTRL   (0xd4)
+#define CM_PER_EPWMSS2_CLKCTRL   (0xd8)
+#define CM_PER_L3_INSTR_CLKCTRL   (0xdc)
+#define CM_PER_L3_CLKCTRL   (0xe0)
+#define CM_PER_IEEE5000_CLKCTRL   (0xe4)
+#define CM_PER_ICSS_CLKCTRL   (0xe8)
+#define CM_PER_TIMER5_CLKCTRL   (0xec)
+#define CM_PER_TIMER6_CLKCTRL   (0xf0)
+#define CM_PER_MMC1_CLKCTRL   (0xf4)
+#define CM_PER_MMC2_CLKCTRL   (0xf8)
+#define CM_PER_TPTC1_CLKCTRL   (0xfc)
+#define CM_PER_TPTC2_CLKCTRL   (0x100)
+#define CM_PER_SPINLOCK_CLKCTRL   (0x10c)
+#define CM_PER_MAILBOX0_CLKCTRL   (0x110)
+#define CM_PER_L4HS_CLKSTCTRL   (0x11c)
+#define CM_PER_L4HS_CLKCTRL   (0x120)
+#define CM_PER_MSTR_EXPS_CLKCTRL   (0x124)
+#define CM_PER_SLV_EXPS_CLKCTRL   (0x128)
+#define CM_PER_OCPWP_L3_CLKSTCTRL   (0x12c)
+#define CM_PER_OCPWP_CLKCTRL   (0x130)
+#define CM_PER_ICSS_CLKSTCTRL   (0x140)
+#define CM_PER_CPSW_CLKSTCTRL   (0x144)
+#define CM_PER_LCDC_CLKSTCTRL   (0x148)
+#define CM_PER_CLKDIV32K_CLKCTRL   (0x14c)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL   (0x150)
+
+/**************************************************************************\ 
+ * Field Definition Macros
+\**************************************************************************/
+
+/* L4LS_CLKSTCTRL */
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK   (0x00000800u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_SHIFT   (0x0000000Bu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK   (0x00080000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT   (0x00000013u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK   (0x00100000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT   (0x00000014u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK   (0x00200000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT   (0x00000015u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK   (0x01000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_SHIFT   (0x00000018u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK   (0x00000100u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_SHIFT   (0x00000008u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK   (0x00020000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_SHIFT   (0x00000011u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK   (0x02000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_SHIFT   (0x00000019u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK   (0x00004000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_SHIFT   (0x0000000Eu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK   (0x00008000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_SHIFT   (0x0000000Fu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK   (0x00010000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_SHIFT   (0x00000010u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK   (0x08000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_SHIFT   (0x0000001Bu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK   (0x10000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_SHIFT   (0x0000001Cu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK   (0x00002000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_SHIFT   (0x0000000Du)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK   (0x00000400u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_SHIFT   (0x0000000Au)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_ACT   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_INACT   (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* L3S_CLKSTCTRL */
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK   (0x00000008u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_SHIFT   (0x00000003u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_ACT   (0x1u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_INACT   (0x0u)
+
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* L4FW_CLKSTCTRL */
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK   (0x00000100u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_SHIFT   (0x00000008u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_ACT   (0x1u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* L3_CLKSTCTRL */
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK   (0x00000040u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT   (0x00000006u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_ACT   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_INACT   (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK   (0x00000004u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_SHIFT   (0x00000002u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_ACT   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_INACT   (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK   (0x00000010u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_ACT   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_INACT   (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK   (0x00000080u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_SHIFT   (0x00000007u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_ACT   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_INACT   (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK   (0x00000008u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_SHIFT   (0x00000003u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_ACT   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_INACT   (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* CPGMAC0_CLKCTRL */
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* LCDC_CLKCTRL */
+#define CM_PER_LCDC_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_LCDC_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* USB0_CLKCTRL */
+#define CM_PER_USB0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_USB0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_USB0_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_USB0_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_USB0_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_USB0_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* MLB_CLKCTRL */
+#define CM_PER_MLB_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MLB_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_MLB_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_MLB_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_MLB_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_MLB_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* TPTC0_CLKCTRL */
+#define CM_PER_TPTC0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_TPTC0_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* EMIF_CLKCTRL */
+#define CM_PER_EMIF_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* OCMCRAM_CLKCTRL */
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* GPMC_CLKCTRL */
+#define CM_PER_GPMC_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MCASP0_CLKCTRL */
+#define CM_PER_MCASP0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* UART5_CLKCTRL */
+#define CM_PER_UART5_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_UART5_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MMC0_CLKCTRL */
+#define CM_PER_MMC0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* ELM_CLKCTRL */
+#define CM_PER_ELM_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_ELM_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* I2C2_CLKCTRL */
+#define CM_PER_I2C2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* I2C1_CLKCTRL */
+#define CM_PER_I2C1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* SPI0_CLKCTRL */
+#define CM_PER_SPI0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* SPI1_CLKCTRL */
+#define CM_PER_SPI1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* L4LS_CLKCTRL */
+#define CM_PER_L4LS_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* L4FW_CLKCTRL */
+#define CM_PER_L4FW_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MCASP1_CLKCTRL */
+#define CM_PER_MCASP1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* UART1_CLKCTRL */
+#define CM_PER_UART1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_UART1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* UART2_CLKCTRL */
+#define CM_PER_UART2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_UART2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* UART3_CLKCTRL */
+#define CM_PER_UART3_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_UART3_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* UART4_CLKCTRL */
+#define CM_PER_UART4_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_UART4_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TIMER7_CLKCTRL */
+#define CM_PER_TIMER7_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TIMER2_CLKCTRL */
+#define CM_PER_TIMER2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_DISABLDED   (0x3u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TIMER3_CLKCTRL */
+#define CM_PER_TIMER3_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TIMER4_CLKCTRL */
+#define CM_PER_TIMER4_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* RNG_CLKCTRL */
+#define CM_PER_RNG_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_RNG_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* AES0_CLKCTRL */
+#define CM_PER_AES0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_AES0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* SHA0_CLKCTRL */
+#define CM_PER_SHA0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* PKA_CLKCTRL */
+#define CM_PER_PKA_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_PKA_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* GPIO1_CLKCTRL */
+#define CM_PER_GPIO1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK   (0x00040000u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT   (0x00000012u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_DIS   (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_EN   (0x1u)
+
+
+/* GPIO2_CLKCTRL */
+#define CM_PER_GPIO2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK   (0x00040000u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT   (0x00000012u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_DIS   (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_EN   (0x1u)
+
+
+/* GPIO3_CLKCTRL */
+#define CM_PER_GPIO3_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK   (0x00040000u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT   (0x00000012u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_DIS   (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_EN   (0x1u)
+
+
+/* TPCC_CLKCTRL */
+#define CM_PER_TPCC_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* DCAN0_CLKCTRL */
+#define CM_PER_DCAN0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* DCAN1_CLKCTRL */
+#define CM_PER_DCAN1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* EPWMSS1_CLKCTRL */
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* EMIF_FW_CLKCTRL */
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* EPWMSS0_CLKCTRL */
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* EPWMSS2_CLKCTRL */
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* L3_INSTR_CLKCTRL */
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* L3_CLKCTRL */
+#define CM_PER_L3_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_L3_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_L3_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_L3_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_L3_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_L3_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_L3_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* IEEE5000_CLKCTRL */
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_IEEE5000_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* ICSS_CLKCTRL */
+#define CM_PER_ICSS_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_ICSS_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* TIMER5_CLKCTRL */
+#define CM_PER_TIMER5_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TIMER6_CLKCTRL */
+#define CM_PER_TIMER6_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MMC1_CLKCTRL */
+#define CM_PER_MMC1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MMC2_CLKCTRL */
+#define CM_PER_MMC2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* TPTC1_CLKCTRL */
+#define CM_PER_TPTC1_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_TPTC1_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* TPTC2_CLKCTRL */
+#define CM_PER_TPTC2_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_DISABLED   (0x3u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_DISABLE   (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_TPTC2_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* SPINLOCK_CLKCTRL */
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MAILBOX0_CLKCTRL */
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* L4HS_CLKSTCTRL */
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK   (0x00000010u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_ACT   (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK   (0x00000020u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT   (0x00000005u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_ACT   (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK   (0x00000040u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT   (0x00000006u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_ACT   (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK   (0x00000008u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_SHIFT   (0x00000003u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_ACT   (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_INACT   (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* L4HS_CLKCTRL */
+#define CM_PER_L4HS_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* MSTR_EXPS_CLKCTRL */
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* SLV_EXPS_CLKCTRL */
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* OCPWP_L3_CLKSTCTRL */
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK   (0x00000010u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_ACT   (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_INACT   (0x0u)
+
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK   (0x00000020u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT   (0x00000005u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_ACT   (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_INACT   (0x0u)
+
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* OCPWP_CLKCTRL */
+#define CM_PER_OCPWP_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+#define CM_PER_OCPWP_CLKCTRL_STBYST   (0x00040000u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_SHIFT   (0x00000012u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_FUNC   (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_STANDBY   (0x1u)
+
+
+/* ICSS_CLKSTCTRL */
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK   (0x00000020u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_SHIFT   (0x00000005u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_ACT   (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_INACT   (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK   (0x00000010u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_ACT   (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_INACT   (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK   (0x00000040u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_SHIFT   (0x00000006u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_ACT   (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_INACT   (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* CPSW_CLKSTCTRL */
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK   (0x00000010u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_ACT   (0x1u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_INACT   (0x0u)
+
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* LCDC_CLKSTCTRL */
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK   (0x00000010u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_ACT   (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_INACT   (0x0u)
+
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK   (0x00000020u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT   (0x00000005u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_ACT   (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_INACT   (0x0u)
+
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+/* CLKDIV32K_CLKCTRL */
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST   (0x00030000u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_DISABLE   (0x3u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_FUNC   (0x0u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_IDLE   (0x2u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_TRANS   (0x1u)
+
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE   (0x00000003u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_SHIFT   (0x00000000u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_DISABLED   (0x0u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED   (0x3u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED_1   (0x1u)
+
+
+/* CLK_24MHZ_CLKSTCTRL */
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK   (0x00000010u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT   (0x00000004u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_ACT   (0x1u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_INACT   (0x0u)
+
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL   (0x00000003u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SHIFT   (0x00000000u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_HW_AUTO   (0x3u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_NO_SLEEP   (0x0u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_SLEEP   (0x1u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_WKUP   (0x2u)
+
+
+
+#endif
diff --git a/cpsw/src/include/hw_control_AM335x.h b/cpsw/src/include/hw_control_AM335x.h
new file mode 100755
index 0000000..c3312f9
--- /dev/null
+++ b/cpsw/src/include/hw_control_AM335x.h
@@ -0,0 +1,7794 @@
+

+

+/**

+ *  @Component:   CONTROL

+ *

+ *  @Filename:    ../../CredDataBase/CONTROL_cred.h

+ *

+ ============================================================================ */

+/*

+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/

+*/

+/*

+*  Redistribution and use in source and binary forms, with or without

+*  modification, are permitted provided that the following conditions

+*  are met:

+*

+*    Redistributions of source code must retain the above copyright

+*    notice, this list of conditions and the following disclaimer.

+*

+*    Redistributions in binary form must reproduce the above copyright

+*    notice, this list of conditions and the following disclaimer in the

+*    documentation and/or other materials provided with the

+*    distribution.

+*

+*    Neither the name of Texas Instruments Incorporated nor the names of

+*    its contributors may be used to endorse or promote products derived

+*    from this software without specific prior written permission.

+*

+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+*

+*/

+

+

+

+#ifndef _HW_CONTROL_H_

+#define _HW_CONTROL_H_

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/***********************************************************************\

+ * Register arrays Definition

+\***********************************************************************/

+

+

+/***********************************************************************\

+ * Bundle arrays Definition

+\***********************************************************************/

+

+

+/***********************************************************************\

+ * Bundles Definition

+\***********************************************************************/

+

+

+

+/*************************************************************************\

+ * Registers Definition

+\*************************************************************************/

+

+#define CONTROL_REVISION   (0x0)

+#define CONTROL_HWINFO   (0x4)

+#define CONTROL_SYSCONFIG   (0x10)

+#define CONTROL_STATUS   (0x40)

+#define CONTROL_BOOTSTAT   (0x44)

+#define CONTROL_SEC_CTRL   (0x100)

+#define CONTROL_SEC_SW   (0x104)

+#define CONTROL_SEC_EMU   (0x108)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG   (0x110)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2   (0x114)

+#define CONTROL_SW_CFG   (0x118)

+#define CONTROL_SW_CCFG   (0x11c)

+#define CONTROL_MPK(n)   (0x120 + (n * 4))

+#define CONTROL_SWRV(n)   (0x140 + (n * 4))

+#define CONTROL_SEC_TAP   (0x180)

+#define CONTROL_SEC_TAP_CMDIN   (0x184)

+#define CONTROL_SEC_TAP_CMDOUT   (0x188)

+#define CONTROL_SEC_TAP_DATIN   (0x18c)

+#define CONTROL_SEC_TAP_DATOUT   (0x190)

+#define CONTROL_MREQDOMAIN_EXP1   (0x198)

+#define CONTROL_MREQDOMAIN_EXP2   (0x19c)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0   (0x1a0)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1   (0x1a4)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF   (0x1a8)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL   (0x1ac)

+#define CONTROL_SEC_CTRL_RO   (0x1b4)

+#define CONTROL_EMIF_OBFUSCATION_KEY   (0x1b8)

+#define CONTROL_SEC_CLK_CTRL   (0x1bc)

+#define CONTROL_MREQDOMAIN_EXP3   (0x1d4)

+#define CONTROL_CEK(n)   (0x200 + (n * 4))

+#define CONTROL_CEK_BCH(n)   (0x210 + (n * 4))

+#define CONTROL_MSV_0   (0x224)

+#define CONTROL_MSV_BCH(n)   (0x228 + (n * 4))

+#define CONTROL_SEC_STATUS   (0x240)

+#define CONTROL_SECMEM_STATUS   (0x244)

+#define CONTROL_SEC_ERR_STAT_FUNC(n)   (0x248 + (n * 4))

+#define CONTROL_SEC_ERR_STAT_DBUG(n)   (0x250 + (n * 4))

+#define CONTROL_KEK_SW(n)   (0x260 + (n * 4))

+#define CONTROL_CMPK_BCH(n)   (0x280 + (n * 4))

+#define CONTROL_CMPK(n)   (0x2b0 + (n * 4))

+#define CONTROL_SSM_END_FAST_SECRAM   (0x300)

+#define CONTROL_SSM_FIREWALL_CONTROLLER   (0x304)

+#define CONTROL_SSM_START_SECURE_STACKED_RAM   (0x308)

+#define CONTROL_SSM_END_SECURE_STACKED_RAM   (0x30c)

+#define CONTROL_SSM_START_SPM_STACK   (0x310)

+#define CONTROL_SSM_END_SPM_STACK   (0x314)

+#define CONTROL_SSM_START_MONITOR_RAMCODE   (0x318)

+#define CONTROL_SSM_END_MONITOR_RAMCODE   (0x31c)

+#define CONTROL_SSM_END_MONITOR_RAMDATA   (0x320)

+#define CONTROL_SSM_START_MONITOR_CODE   (0x324)

+#define CONTROL_SSM_END_MONITOR_CODE   (0x328)

+#define CONTROL_SSM_START_MONITOR_PERIPH   (0x32c)

+#define CONTROL_SSM_END_MONITOR_PERIPH   (0x330)

+#define CONTROL_SSM_START_MONITOR_STACK   (0x334)

+#define CONTROL_SSM_END_MONITOR_STACK   (0x338)

+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM   (0x33c)

+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM   (0x340)

+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM   (0x344)

+#define CONTROL_SSM_START_MONITOR_CODE_ETM   (0x348)

+#define CONTROL_SSM_END_MONITOR_CODE_ETM   (0x34c)

+#define CONTROL_SSM_START_MONITOR_STACK_ETM   (0x350)

+#define CONTROL_SSM_END_MONITOR_STACK_ETM   (0x354)

+#define CONTROL_SSM_START_MONITOR_SHARED_ETM   (0x358)

+#define CONTROL_SSM_END_MONITOR_SHARED_ETM   (0x35c)

+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM   (0x360)

+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM   (0x364)

+#define CONTROL_SSM_CPSR_MODE_ENFC   (0x368)

+#define CONTROL_SSM_END_L3_SECRAM   (0x36c)

+#define CONTROL_CORTEX_VBBLDO_CTRL   (0x41c)

+#define CONTROL_CORE_SLDO_CTRL   (0x428)

+#define CONTROL_MPU_SLDO_CTRL   (0x42c)

+#define CONTROL_REFCLK_LJCBLDO_CTRL   (0x440)

+#define CONTROL_CLK32KDIVRATIO_CTRL   (0x444)

+#define CONTROL_BANDGAP_CTRL   (0x448)

+#define CONTROL_BANDGAP_TRIM   (0x44c)

+#define CONTROL_PLL_CLKINPULOW_CTRL   (0x458)

+#define CONTROL_MOSC_CTRL   (0x468)

+#define CONTROL_RCOSC_CTRL   (0x46c)

+#define CONTROL_DEEPSLEEP_CTRL   (0x470)

+#define CONTROL_PE_SCRATCHPAD(n)   (0x500 + (n * 4))

+#define CONTROL_DEVICE_ID   (0x600)

+#define CONTROL_DEV_FEATURE   (0x604)

+#define CONTROL_INIT_PRIORITY(n)   (0x608 + (n * 4))

+#define CONTROL_MMU_CFG   (0x610)

+#define CONTROL_TPTC_CFG   (0x614)

+#define CONTROL_OCMC_CFG   (0x618)

+#define CONTROL_USB_CTRL(n)   (0x620 + (n * 8))

+#define CONTROL_USB_STS(n)   (0x624 + (n * 8))

+#define CONTROL_MAC_ID_LO(n)   (0x630 + (n * 8))

+#define CONTROL_MAC_ID_HI(n)   (0x634 + (n * 8))

+#define CONTROL_DCAN_RAMINIT   (0x644)

+#define CONTROL_USB_WKUP_CTRL   (0x648)

+#define CONTROL_GMII_SEL   (0x650)

+#define CONTROL_PWMSS_CTRL   (0x664)

+#define CONTROL_MREQPRIO(n)   (0x670 + (n * 4))

+#define CONTROL_HW_EVENT_SEL_GRP(n)   (0x690 + (n * 4))

+#define CONTROL_SMRT_CTRL   (0x6a0)

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL   (0x6a4)

+#define CONTROL_SABTOOTH_HW_DBG_INFO   (0x6a8)

+#define CONTROL_MRGN_MODE(n)   (0x6c0 + (n * 4))

+#define CONTROL_VDD_MPU_OPP(n)   (0x770 + (n * 4))

+#define CONTROL_VDD_MPU_OPP_TURBO   (0x77c)

+#define CONTROL_VDD_CORE_OPP(n)   (0x7b8 + (n * 4))

+#define CONTROL_BB_SCALE   (0x7d0)

+#define CONTROL_USB_VID_PID   (0x7f4)

+#define CONTROL_EFUSE_SMA   (0x7fc)

+#define CONTROL_CONF_GPMC_AD(n)   (0x800 + (n * 4))

+#define CONTROL_CONF_GPMC_A(n)   (0x840 + (n * 4))

+#define CONTROL_CONF_GPMC_WAIT0   (0x870)

+#define CONTROL_CONF_GPMC_WPN   (0x874)

+#define CONTROL_CONF_GPMC_BE1N   (0x878)

+#define CONTROL_CONF_GPMC_CSN(n)   (0x87c + (n * 4))

+#define CONTROL_CONF_GPMC_CLK   (0x88c)

+#define CONTROL_CONF_GPMC_ADVN_ALE   (0x890)

+#define CONTROL_CONF_GPMC_OEN_REN   (0x894)

+#define CONTROL_CONF_GPMC_WEN   (0x898)

+#define CONTROL_CONF_GPMC_BE0N_CLE   (0x89c)

+#define CONTROL_CONF_LCD_DATA(n)   (0x8a0 + (n * 4))

+#define CONTROL_CONF_LCD_VSYNC   (0x8e0)

+#define CONTROL_CONF_LCD_HSYNC   (0x8e4)

+#define CONTROL_CONF_LCD_PCLK   (0x8e8)

+#define CONTROL_CONF_LCD_AC_BIAS_EN   (0x8ec)

+#define CONTROL_CONF_MMC0_DAT3   (0x8f0)

+#define CONTROL_CONF_MMC0_DAT2   (0x8f4)

+#define CONTROL_CONF_MMC0_DAT1   (0x8f8)

+#define CONTROL_CONF_MMC0_DAT0   (0x8fc)

+#define CONTROL_CONF_MMC0_CLK   (0x900)

+#define CONTROL_CONF_MMC0_CMD   (0x904)

+#define CONTROL_CONF_MII1_COL   (0x908)

+#define CONTROL_CONF_MII1_CRS   (0x90c)

+#define CONTROL_CONF_MII1_RXERR   (0x910)

+#define CONTROL_CONF_MII1_TXEN   (0x914)

+#define CONTROL_CONF_MII1_RXDV   (0x918)

+#define CONTROL_CONF_MII1_TXD3   (0x91c)

+#define CONTROL_CONF_MII1_TXD2   (0x920)

+#define CONTROL_CONF_MII1_TXD1   (0x924)

+#define CONTROL_CONF_MII1_TXD0   (0x928)

+#define CONTROL_CONF_MII1_TXCLK   (0x92c)

+#define CONTROL_CONF_MII1_RXCLK   (0x930)

+#define CONTROL_CONF_MII1_RXD3   (0x934)

+#define CONTROL_CONF_MII1_RXD2   (0x938)

+#define CONTROL_CONF_MII1_RXD1   (0x93c)

+#define CONTROL_CONF_MII1_RXD0   (0x940)

+#define CONTROL_CONF_RMII1_REFCLK   (0x944)

+#define CONTROL_CONF_MDIO_DATA   (0x948)

+#define CONTROL_CONF_MDIO_CLK   (0x94c)

+#define CONTROL_CONF_SPI0_SCLK   (0x950)

+#define CONTROL_CONF_SPI0_D0   (0x954)

+#define CONTROL_CONF_SPI0_D1   (0x958)

+#define CONTROL_CONF_SPI0_CS0   (0x95c)

+#define CONTROL_CONF_SPI0_CS1   (0x960)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT   (0x964)

+#define CONTROL_CONF_UART_CTSN(n)   (0x968 + ((n) * 0x10))

+#define CONTROL_CONF_UART_RTSN(n)   (0x96c + ((n) * 0x10))

+#define CONTROL_CONF_UART_RXD(n)   (0x970 + ((n) * 0x10))

+#define CONTROL_CONF_UART_TXD(n)   (0x974 + ((n) * 0x10))

+#define CONTROL_CONF_I2C0_SDA   (0x988)

+#define CONTROL_CONF_I2C0_SCL   (0x98c)

+#define CONTROL_CONF_MCASP0_ACLKX   (0x990)

+#define CONTROL_CONF_MCASP0_FSX   (0x994)

+#define CONTROL_CONF_MCASP0_AXR0   (0x998)

+#define CONTROL_CONF_MCASP0_AHCLKR   (0x99c)

+#define CONTROL_CONF_MCASP0_ACLKR   (0x9a0)

+#define CONTROL_CONF_MCASP0_FSR   (0x9a4)

+#define CONTROL_CONF_MCASP0_AXR1   (0x9a8)

+#define CONTROL_CONF_MCASP0_AHCLKX   (0x9ac)

+#define CONTROL_CONF_XDMA_EVENT_INTR(n)   (0x9b0 + (n * 4))

+#define CONTROL_CONF_NRESETIN_OUT   (0x9b8)

+#define CONTROL_CONF_PORZ   (0x9bc)

+#define CONTROL_CONF_NNMI   (0x9c0)

+#define CONTROL_CONF_OSC_IN(n)   (0x9c4 + (n * 0x24))

+#define CONTROL_CONF_OSC_OUT(n)   (0x9c8 + (n * 0x24))

+#define CONTROL_CONF_OSC_VSS(n)   (0x9cc + (n * 0x24))

+#define CONTROL_CONF_TMS   (0x9d0)

+#define CONTROL_CONF_TDI   (0x9d4)

+#define CONTROL_CONF_TDO   (0x9d8)

+#define CONTROL_CONF_TCK   (0x9dc)

+#define CONTROL_CONF_NTRST   (0x9e0)

+#define CONTROL_CONF_EMU(n)   (0x9e4 + (n * 4))

+#define CONTROL_CONF_RTC_PORZ   (0x9f8)

+#define CONTROL_CONF_PMIC_POWER_EN   (0x9fc)

+#define CONTROL_CONF_EXT_WAKEUP   (0xa00)

+#define CONTROL_CONF_ENZ_KALDO_1P8V   (0xa04)

+#define CONTROL_CONF_USB_DM(n)   (0xa08 + ((n) * 0x18))

+#define CONTROL_CONF_USB_DP(n)   (0xa0c + ((n) * 0x18))

+#define CONTROL_CONF_USB_CE(n)   (0xa10 + ((n) * 0x18))

+#define CONTROL_CONF_USB_ID(n)   (0xa14 + ((n) * 0x18))

+#define CONTROL_CONF_USB_VBUS(n)   (0xa18 + ((n) * 0x18))

+#define CONTROL_CONF_USB_DRVVBUS(n)   (0xa1c + ((n) * 0x18))

+#define CONTROL_CONF_DDR_RESETN   (0xa38)

+#define CONTROL_CONF_DDR_CSN0   (0xa3c)

+#define CONTROL_CONF_DDR_CKE   (0xa40)

+#define CONTROL_CONF_DDR_CK    (0xa44)

+#define CONTROL_CONF_DDR_NCK   (0xa48)

+#define CONTROL_CONF_DDR_CASN   (0xa4c)

+#define CONTROL_CONF_DDR_RASN   (0xa50)

+#define CONTROL_CONF_DDR_WEN   (0xa54)

+#define CONTROL_CONF_DDR_BA(n)   (0xa58 + (n * 4))

+#define CONTROL_CONF_DDR_A(n)   (0xa64 + (n * 4))

+#define CONTROL_CONF_DDR_ODT   (0xaa4)

+#define CONTROL_CONF_DDR_D(n)   (0xaa8 + (n * 4))

+#define CONTROL_CONF_DDR_DQM(n)   (0xae8 + (n * 4))

+#define CONTROL_CONF_DDR_DQS(n)   (0xaf0 + (n * 8))

+#define CONTROL_CONF_DDR_DQSN(n)   (0xaf4 + (n * 8))

+#define CONTROL_CONF_DDR_VREF   (0xb00)

+#define CONTROL_CONF_DDR_VTP   (0xb04)

+#define CONTROL_CONF_DDR_STRBEN(n)   (0xb08 + (n * 4))

+#define CONTROL_CONF_AIN0    (0xb2c)

+#define CONTROL_CONF_AIN1    (0xb28)

+#define CONTROL_CONF_AIN2    (0xb24)

+#define CONTROL_CONF_AIN3    (0xb20)

+#define CONTROL_CONF_AIN4    (0xb1c)

+#define CONTROL_CONF_AIN5    (0xb18)

+#define CONTROL_CONF_AIN6    (0xb14)

+#define CONTROL_CONF_AIN7    (0xb10)

+#define CONTROL_CONF_VREFP   (0xb30)

+#define CONTROL_CONF_VREFN   (0xb34)

+#define CONTROL_CONF_AVDD   (0xb38)

+#define CONTROL_CONF_AVSS   (0xb3c)

+#define CONTROL_CONF_IFORCE   (0xb40)

+#define CONTROL_CONF_VSENSE   (0xb44)

+#define CONTROL_CONF_TESTOUT   (0xb48)

+#define CONTROL_CQDETECT_STATUS   (0xe00)

+#define CONTROL_DDR_IO_CTRL   (0xe04)

+#define CONTROL_VTP_CTRL   (0xe0c)

+#define CONTROL_VREF_CTRL   (0xe14)

+#define CONTROL_SERDES_REFCLK_CTL   (0xe24)

+#define CONTROL_TPCC_EVT_MUX_0_3   (0xf90)

+#define CONTROL_TPCC_EVT_MUX_4_7   (0xf94)

+#define CONTROL_TPCC_EVT_MUX_8_11   (0xf98)

+#define CONTROL_TPCC_EVT_MUX_12_15   (0xf9c)

+#define CONTROL_TPCC_EVT_MUX_16_19   (0xfa0)

+#define CONTROL_TPCC_EVT_MUX_20_23   (0xfa4)

+#define CONTROL_TPCC_EVT_MUX_24_27   (0xfa8)

+#define CONTROL_TPCC_EVT_MUX_28_31   (0xfac)

+#define CONTROL_TPCC_EVT_MUX_32_35   (0xfb0)

+#define CONTROL_TPCC_EVT_MUX_36_39   (0xfb4)

+#define CONTROL_TPCC_EVT_MUX_40_43   (0xfb8)

+#define CONTROL_TPCC_EVT_MUX_44_47   (0xfbc)

+#define CONTROL_TPCC_EVT_MUX_48_51   (0xfc0)

+#define CONTROL_TPCC_EVT_MUX_52_55   (0xfc4)

+#define CONTROL_TPCC_EVT_MUX_56_59   (0xfc8)

+#define CONTROL_TPCC_EVT_MUX_60_63   (0xfcc)

+#define CONTROL_TIMER_EVT_CAPT   (0xfd0)

+#define CONTROL_ECAP_EVT_CAPT   (0xfd4)

+#define CONTROL_ADC_EVT_CAPT   (0xfd8)

+#define CONTROL_RESET_ISO   (0x1000)

+#define CONTROL_SMA(n)   (0x1318 + (n * 8))

+#define CONTROL_DDR_CKE_CTRL   (0x131c)

+#define CONTROL_M3_TXEV_EOI   (0x1324)

+#define CONTROL_IPC_MSG_REG(n)   (0x1328 + (n * 4))

+#define CONTROL_DDR_CMD_IOCTRL(n)   (0x1404 + (n * 4))

+#define CONTROL_DDR_DATA_IOCTRL(n)   (0x1440 + (n * 4))

+

+

+#define CONTROL_CONF_PULLUDDISABLE     0x00000008 

+#define CONTROL_CONF_PULLUPSEL         0x00000010

+#define CONTROL_CONF_RXACTIVE          0x00000020 

+#define CONTROL_CONF_SLOWSLEW          0x00000040

+#define CONTROL_CONF_MUXMODE(n)        (n)

+

+

+/**************************************************************************\ 

+ * Field Definition Macros

+\**************************************************************************/

+

+/* CONTROL_REVISION */

+#define CONTROL_REVISION_IP_REV_CUSTOM   (0x000000C0u)

+#define CONTROL_REVISION_IP_REV_CUSTOM_SHIFT   (0x00000006u)

+

+#define CONTROL_REVISION_IP_REV_FUNC   (0x0FFF0000u)

+#define CONTROL_REVISION_IP_REV_FUNC_SHIFT   (0x00000010u)

+

+#define CONTROL_REVISION_IP_REV_MAJOR   (0x00000700u)

+#define CONTROL_REVISION_IP_REV_MAJOR_SHIFT   (0x00000008u)

+

+#define CONTROL_REVISION_IP_REV_MINOR   (0x0000003Fu)

+#define CONTROL_REVISION_IP_REV_MINOR_SHIFT   (0x00000000u)

+

+#define CONTROL_REVISION_IP_REV_RTL   (0x0000F800u)

+#define CONTROL_REVISION_IP_REV_RTL_SHIFT   (0x0000000Bu)

+

+#define CONTROL_REVISION_IP_REV_SCHEME   (0xC0000000u)

+#define CONTROL_REVISION_IP_REV_SCHEME_SHIFT   (0x0000001Eu)

+

+

+/* CONTROL_HWINFO */

+#define CONTROL_HWINFO_IP_HWINFO   (0xFFFFFFFFu)

+#define CONTROL_HWINFO_IP_HWINFO_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SYSCONFIG */

+#define CONTROL_SYSCONFIG_FREEEMU   (0x00000002u)

+#define CONTROL_SYSCONFIG_FREEEMU_SHIFT   (0x00000001u)

+

+#define CONTROL_SYSCONFIG_IDLEMODE   (0x0000000Cu)

+#define CONTROL_SYSCONFIG_IDLEMODE_SHIFT   (0x00000002u)

+

+#define CONTROL_SYSCONFIG_RSVD2   (0xFFFFFFC0u)

+#define CONTROL_SYSCONFIG_RSVD2_SHIFT   (0x00000006u)

+

+#define CONTROL_SYSCONFIG_STANDBY   (0x00000030u)

+#define CONTROL_SYSCONFIG_STANDBY_SHIFT   (0x00000004u)

+

+

+/* CONTROL_STATUS */

+#define CONTROL_STATUS_ADMUX   (0x000C0000u)

+#define CONTROL_STATUS_ADMUX_SHIFT   (0x00000012u)

+

+#define CONTROL_STATUS_BW   (0x00010000u)

+#define CONTROL_STATUS_BW_SHIFT   (0x00000010u)

+

+#define CONTROL_STATUS_DEVTYPE   (0x00000700u)

+#define CONTROL_STATUS_DEVTYPE_SHIFT   (0x00000008u)

+

+#define CONTROL_STATUS_RSVD2   (0xFF000000u)

+#define CONTROL_STATUS_RSVD2_SHIFT   (0x00000018u)

+

+#define CONTROL_STATUS_SYSBOOT0   (0x000000FFu)

+#define CONTROL_STATUS_SYSBOOT0_SHIFT   (0x00000000u)

+

+#define CONTROL_STATUS_SYSBOOT1   (0x00C00000u)

+#define CONTROL_STATUS_SYSBOOT1_SHIFT   (0x00000016u)

+

+#define CONTROL_STATUS_TESTMD   (0x00300000u)

+#define CONTROL_STATUS_TESTMD_SHIFT   (0x00000014u)

+

+#define CONTROL_STATUS_WAITEN   (0x00020000u)

+#define CONTROL_STATUS_WAITEN_SHIFT   (0x00000011u)

+

+

+/* BOOTSTAT */

+#define CONTROL_BOOTSTAT_BC   (0x00000001u)

+#define CONTROL_BOOTSTAT_BC_SHIFT   (0x00000000u)

+

+#define CONTROL_BOOTSTAT_BOOTERR   (0x000F0000u)

+#define CONTROL_BOOTSTAT_BOOTERR_SHIFT   (0x00000010u)

+

+#define CONTROL_BOOTSTAT_RSVD2   (0xFFF00000u)

+#define CONTROL_BOOTSTAT_RSVD2_SHIFT   (0x00000014u)

+

+

+/* CONTROL_SEC_CTRL */

+#define CONTROL_SEC_CTRL_BSCENABLE   (0x00000200u)

+#define CONTROL_SEC_CTRL_BSCENABLE_SHIFT   (0x00000009u)

+

+#define CONTROL_SEC_CTRL_CATSCANEN   (0x00000100u)

+#define CONTROL_SEC_CTRL_CATSCANEN_SHIFT   (0x00000008u)

+

+#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC   (0x00002000u)

+#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC_SHIFT   (0x0000000Du)

+

+#define CONTROL_SEC_CTRL_CPEFUSELDDONE   (0x00000400u)

+#define CONTROL_SEC_CTRL_CPEFUSELDDONE_SHIFT   (0x0000000Au)

+

+#define CONTROL_SEC_CTRL_CPEFUSENOTDEC   (0x00001000u)

+#define CONTROL_SEC_CTRL_CPEFUSENOTDEC_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SEC_CTRL_CPEFUSEWRDIS   (0x00000800u)

+#define CONTROL_SEC_CTRL_CPEFUSEWRDIS_SHIFT   (0x0000000Bu)

+

+#define CONTROL_SEC_CTRL_DMLEDCOREEN   (0x00000080u)

+#define CONTROL_SEC_CTRL_DMLEDCOREEN_SHIFT   (0x00000007u)

+

+#define CONTROL_SEC_CTRL_FASTOCMSECSAVE   (0x30000000u)

+#define CONTROL_SEC_CTRL_FASTOCMSECSAVE_SHIFT   (0x0000001Cu)

+

+#define CONTROL_SEC_CTRL_KEKSWENABLE0   (0x00000004u)

+#define CONTROL_SEC_CTRL_KEKSWENABLE0_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_CTRL_KEKSWENABLE1   (0x00000010u)

+#define CONTROL_SEC_CTRL_KEKSWENABLE1_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_CTRL_L3OCMSECSAVE   (0x0C000000u)

+#define CONTROL_SEC_CTRL_L3OCMSECSAVE_SHIFT   (0x0000001Au)

+

+#define CONTROL_SEC_CTRL_RSVD2   (0x00000060u)

+#define CONTROL_SEC_CTRL_RSVD2_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE   (0x80000000u)

+#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE_SHIFT   (0x0000001Fu)

+

+#define CONTROL_SEC_CTRL_SECUREMODEINITDONE   (0x40000000u)

+#define CONTROL_SEC_CTRL_SECUREMODEINITDONE_SHIFT   (0x0000001Eu)

+

+#define CONTROL_SEC_CTRL_WDOPDISABLE   (0x00000001u)

+#define CONTROL_SEC_CTRL_WDOPDISABLE_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_CTRL_WDREGENABLE   (0x00000002u)

+#define CONTROL_SEC_CTRL_WDREGENABLE_SHIFT   (0x00000001u)

+

+

+/* CONTROL_SEC_SW */

+#define CONTROL_SEC_SW_SW_HW_PARAMETERS   (0xFFFFFFFFu)

+#define CONTROL_SEC_SW_SW_HW_PARAMETERS_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SEC_EMU */

+#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN   (0x00001000u)

+#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SEC_EMU_GENDBGEN   (0x00000FFFu)

+#define CONTROL_SEC_EMU_GENDBGEN_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_EMU_GENDBGEN_M3   (0x0000C000u)

+#define CONTROL_SEC_EMU_GENDBGEN_M3_SHIFT   (0x0000000Eu)

+

+#define CONTROL_SEC_EMU_ICESECPRIVDBGEN   (0x00002000u)

+#define CONTROL_SEC_EMU_ICESECPRIVDBGEN_SHIFT   (0x0000000Du)

+

+#define CONTROL_SEC_EMU_SECEMUWRDIS   (0x80000000u)

+#define CONTROL_SEC_EMU_SECEMUWRDIS_SHIFT   (0x0000001Fu)

+

+

+/* SECURE_EMIF_SDRAM_CONFIG */

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL   (0x00003C00u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL_SHIFT   (0x0000000Au)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL   (0x00030000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL_SHIFT   (0x00000010u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM   (0x07000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM_SHIFT   (0x00000018u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT   (0x00600000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT_SHIFT   (0x00000015u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK   (0x00000008u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK_SHIFT   (0x00000003u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK   (0x00000070u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_SHIFT   (0x00000004u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS   (0x18000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE   (0x0000C000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE_SHIFT   (0x0000000Eu)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE   (0x00000007u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE_SHIFT   (0x00000000u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE   (0x00000380u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE_SHIFT   (0x00000007u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2   (0x00800000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2_SHIFT   (0x00000017u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE   (0x000C0000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE_SHIFT   (0x00000012u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE   (0xE0000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE_SHIFT   (0x0000001Du)

+

+

+/* SECURE_EMIF_SDRAM_CONFIG_2 */

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN   (0x40000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN_SHIFT   (0x0000001Eu)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS   (0x08000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM   (0x00000030u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM_SHIFT   (0x00000004u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE   (0x00000007u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE_SHIFT   (0x00000000u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2   (0x07FFFFC0u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2_SHIFT   (0x00000006u)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3   (0x30000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3_SHIFT   (0x0000001Cu)

+

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4   (0x80000000u)

+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4_SHIFT   (0x0000001Fu)

+

+

+/* CONTROL_SW_CFG */

+#define CONTROL_SW_CFG_SW_CFG   (0xFFFFFFFFu)

+#define CONTROL_SW_CFG_SW_CFG_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SW_CCFG */

+#define CONTROL_SW_CCFG_SW_CCFG   (0x0000FFFFu)

+#define CONTROL_SW_CCFG_SW_CCFG_SHIFT   (0x00000000u)

+

+#define CONTROL_SW_CCFG_SW_CCFG_RED   (0xFFFF0000u)

+#define CONTROL_SW_CCFG_SW_CCFG_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_MPK_0 */

+#define CONTROL_MPK_0_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_0_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_1 */

+#define CONTROL_MPK_1_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_1_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_2 */

+#define CONTROL_MPK_2_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_2_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_3 */

+#define CONTROL_MPK_3_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_3_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_4 */

+#define CONTROL_MPK_4_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_4_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_5 */

+#define CONTROL_MPK_5_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_5_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_6 */

+#define CONTROL_MPK_6_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_6_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MPK_7 */

+#define CONTROL_MPK_7_MPK   (0xFFFFFFFFu)

+#define CONTROL_MPK_7_MPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SWRV_0 */

+#define CONTROL_SWRV_0_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_0_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_0_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_0_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_1 */

+#define CONTROL_SWRV_1_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_1_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_1_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_1_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_2 */

+#define CONTROL_SWRV_2_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_2_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_2_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_2_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_3 */

+#define CONTROL_SWRV_3_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_3_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_3_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_3_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_4 */

+#define CONTROL_SWRV_4_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_4_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_4_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_4_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_5 */

+#define CONTROL_SWRV_5_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_5_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_5_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_5_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SWRV_6 */

+#define CONTROL_SWRV_6_SWRV   (0x0000FFFFu)

+#define CONTROL_SWRV_6_SWRV_SHIFT   (0x00000000u)

+

+#define CONTROL_SWRV_6_SWRV_RED   (0xFFFF0000u)

+#define CONTROL_SWRV_6_SWRV_RED_SHIFT   (0x00000010u)

+

+

+/* CONTROL_SEC_TAP */

+#define CONTROL_SEC_TAP_1500EN   (0x00000008u)

+#define CONTROL_SEC_TAP_1500EN_SHIFT   (0x00000003u)

+

+#define CONTROL_SEC_TAP_DAPTAPEN   (0x00000001u)

+#define CONTROL_SEC_TAP_DAPTAPEN_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_TAP_PART1500DIS   (0x00000010u)

+#define CONTROL_SEC_TAP_PART1500DIS_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_TAP_RSVD2   (0x000001E0u)

+#define CONTROL_SEC_TAP_RSVD2_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_TAP_RSVD3   (0x7FFFFC00u)

+#define CONTROL_SEC_TAP_RSVD3_SHIFT   (0x0000000Au)

+

+#define CONTROL_SEC_TAP_SABERMPUTAPEN   (0x00000200u)

+#define CONTROL_SEC_TAP_SABERMPUTAPEN_SHIFT   (0x00000009u)

+

+#define CONTROL_SEC_TAP_SECTAPWRDISABLE   (0x80000000u)

+#define CONTROL_SEC_TAP_SECTAPWRDISABLE_SHIFT   (0x0000001Fu)

+

+#define CONTROL_SEC_TAP_WAKEUPTAPEN   (0x00000004u)

+#define CONTROL_SEC_TAP_WAKEUPTAPEN_SHIFT   (0x00000002u)

+

+

+/* CONTROL_SEC_TAP_CMDIN */

+#define CONTROL_SEC_TAP_CMDIN_CMDIN   (0x000000FFu)

+#define CONTROL_SEC_TAP_CMDIN_CMDIN_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SEC_TAP_CMDOUT */

+#define CONTROL_SEC_TAP_CMDOUT_CMDOUT   (0x000000FFu)

+#define CONTROL_SEC_TAP_CMDOUT_CMDOUT_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SEC_TAP_DATIN */

+#define CONTROL_SEC_TAP_DATIN_DATAIN   (0x000000FFu)

+#define CONTROL_SEC_TAP_DATIN_DATAIN_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SEC_TAP_DATOUT */

+#define CONTROL_SEC_TAP_DATOUT_DATAOUT   (0x000000FFu)

+#define CONTROL_SEC_TAP_DATOUT_DATAOUT_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MREQDOMAIN_EXP1 */

+#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM   (0x001C0000u)

+#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM_SHIFT   (0x00000012u)

+

+#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM   (0x00000007u)

+#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM_SHIFT   (0x00000000u)

+

+#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM   (0x00038000u)

+#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM_SHIFT   (0x0000000Fu)

+

+#define CONTROL_MREQDOMAIN_EXP1_LCK   (0x80000000u)

+#define CONTROL_MREQDOMAIN_EXP1_LCK_SHIFT   (0x0000001Fu)

+

+#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM   (0x00007000u)

+#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_MREQDOMAIN_EXP1_RSVD2   (0x78000000u)

+#define CONTROL_MREQDOMAIN_EXP1_RSVD2_SHIFT   (0x0000001Bu)

+

+#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM   (0x07000000u)

+#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM_SHIFT   (0x00000018u)

+

+#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM   (0x00E00000u)

+#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM_SHIFT   (0x00000015u)

+

+

+/* CONTROL_MREQDOMAIN_EXP2 */

+#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM   (0x001C0000u)

+#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM_SHIFT   (0x00000012u)

+

+#define CONTROL_MREQDOMAIN_EXP2_LCK   (0x80000000u)

+#define CONTROL_MREQDOMAIN_EXP2_LCK_SHIFT   (0x0000001Fu)

+

+#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM   (0x00038000u)

+#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM_SHIFT   (0x0000000Fu)

+

+#define CONTROL_MREQDOMAIN_EXP2_RSVD2   (0x7FE00000u)

+#define CONTROL_MREQDOMAIN_EXP2_RSVD2_SHIFT   (0x00000015u)

+

+#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM   (0x00000E00u)

+#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM_SHIFT   (0x00000009u)

+

+#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM   (0x00007000u)

+#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM_SHIFT   (0x0000000Cu)

+

+

+/* L3_HW_FW_EXP_VAL_CONF0 */

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN   (0x00040000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN_SHIFT   (0x00000012u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN   (0x00000004u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN_SHIFT   (0x00000002u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN   (0x01000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN_SHIFT   (0x00000018u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN   (0x00000100u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN_SHIFT   (0x00000008u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2   (0x00000020u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2_SHIFT   (0x00000005u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3   (0x00000200u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3_SHIFT   (0x00000009u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4   (0x0003F800u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4_SHIFT   (0x0000000Bu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5   (0x00200000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5_SHIFT   (0x00000015u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6   (0x02000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6_SHIFT   (0x00000019u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7   (0xF8000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7_SHIFT   (0x0000001Bu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN   (0x00800000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN_SHIFT   (0x00000017u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN   (0x00000080u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN_SHIFT   (0x00000007u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN   (0x00100000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN_SHIFT   (0x00000014u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN   (0x00000010u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN_SHIFT   (0x00000004u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN   (0x00080000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN_SHIFT   (0x00000013u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN   (0x00000008u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN_SHIFT   (0x00000003u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN   (0x04000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN_SHIFT   (0x0000001Au)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN   (0x00000400u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN_SHIFT   (0x0000000Au)

+

+

+/* L3_HW_FW_EXP_VAL_CONF1 */

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN   (0x08000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN_SHIFT   (0x0000001Bu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN   (0x00000800u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN_SHIFT   (0x0000000Bu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN   (0x10000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN_SHIFT   (0x0000001Cu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN   (0x00001000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN_SHIFT   (0x0000000Cu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN   (0x02000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN_SHIFT   (0x00000019u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN   (0x00000200u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN_SHIFT   (0x00000009u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN   (0x01000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN_SHIFT   (0x00000018u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN   (0x00000100u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN_SHIFT   (0x00000008u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN   (0x00080000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN_SHIFT   (0x00000013u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN   (0x00000008u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN_SHIFT   (0x00000003u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN   (0x00100000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN_SHIFT   (0x00000014u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN   (0x00000010u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN_SHIFT   (0x00000004u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN   (0x00200000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN_SHIFT   (0x00000015u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN   (0x00000020u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN_SHIFT   (0x00000005u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN   (0x04000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN_SHIFT   (0x0000001Au)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN   (0x00000400u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN_SHIFT   (0x0000000Au)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2   (0x00000080u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2_SHIFT   (0x00000007u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3   (0x00078000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3_SHIFT   (0x0000000Fu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4   (0x00800000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4_SHIFT   (0x00000017u)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5   (0x80000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5_SHIFT   (0x0000001Fu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN   (0x40000000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN_SHIFT   (0x0000001Eu)

+

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN   (0x00004000u)

+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN_SHIFT   (0x0000000Eu)

+

+

+/* L4_HW_FW_EXP_VAL_CONF */

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN   (0x01000000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN_SHIFT   (0x00000018u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN   (0x00000100u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN_SHIFT   (0x00000008u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN   (0x00100000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN_SHIFT   (0x00000014u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN   (0x00000010u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN_SHIFT   (0x00000004u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN   (0x00200000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN_SHIFT   (0x00000015u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN   (0x00000020u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN_SHIFT   (0x00000005u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN   (0x00010000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN_SHIFT   (0x00000010u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN   (0x00000001u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN_SHIFT   (0x00000000u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN   (0x00020000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN_SHIFT   (0x00000011u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN   (0x00000002u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN_SHIFT   (0x00000001u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN   (0x10000000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN_SHIFT   (0x0000001Cu)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN   (0x00001000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN_SHIFT   (0x0000000Cu)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN   (0x20000000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN_SHIFT   (0x0000001Du)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN   (0x00002000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN_SHIFT   (0x0000000Du)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2   (0x000000C0u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2_SHIFT   (0x00000006u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3   (0x00000E00u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3_SHIFT   (0x00000009u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4   (0x0000C000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4_SHIFT   (0x0000000Eu)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5   (0x000C0000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5_SHIFT   (0x00000012u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6   (0x00C00000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6_SHIFT   (0x00000016u)

+

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7   (0x0E000000u)

+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7_SHIFT   (0x00000019u)

+

+

+/* CONTROL_SEC_LOAD_FW_EXP_VAL */

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN   (0x00000010u)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN   (0x00000004u)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN   (0x00000008u)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN_SHIFT   (0x00000003u)

+

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN   (0x00000020u)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2   (0xFFFFFFC0u)

+#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2_SHIFT   (0x00000006u)

+

+

+/* CONTROL_SEC_CTRL_RO */

+#define CONTROL_SEC_CTRL_RO_CUSTMPK   (0x00000010u)

+#define CONTROL_SEC_CTRL_RO_CUSTMPK_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN   (0x00000002u)

+#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN_SHIFT   (0x00000001u)

+

+#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN   (0x00000004u)

+#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_CTRL_RO_RSVD2   (0xFFFFFFE0u)

+#define CONTROL_SEC_CTRL_RO_RSVD2_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_CTRL_RO_SECKEYACCEN   (0x00000008u)

+#define CONTROL_SEC_CTRL_RO_SECKEYACCEN_SHIFT   (0x00000003u)

+

+

+/* EMIF_OBFUSCATION_KEY */

+#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY   (0x0000FFFFu)

+#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY_SHIFT   (0x00000000u)

+

+

+/* SEC_CLK_CTRL */

+#define CONTROL_SEC_CLK_CTRL_RSVD2   (0x7FFFFFC0u)

+#define CONTROL_SEC_CLK_CTRL_RSVD2_SHIFT   (0x00000006u)

+

+#define CONTROL_SEC_CLK_CTRL_SECCLKLCK   (0x80000000u)

+#define CONTROL_SEC_CLK_CTRL_SECCLKLCK_SHIFT   (0x0000001Fu)

+

+#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL   (0x00000030u)

+#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL   (0x00000001u)

+#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MREQDOMAIN_EXP3 */

+#define CONTROL_MREQDOMAIN_EXP3_LCK   (0x80000000u)

+#define CONTROL_MREQDOMAIN_EXP3_LCK_SHIFT   (0x0000001Fu)

+

+#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM   (0x00000007u)

+#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM_SHIFT   (0x00000000u)

+

+#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM   (0x00000038u)

+#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM_SHIFT   (0x00000003u)

+

+#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM   (0x000001C0u)

+#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM_SHIFT   (0x00000006u)

+

+#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM   (0x00000E00u)

+#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM_SHIFT   (0x00000009u)

+

+

+/* CONTROL_CEK_0 */

+#define CONTROL_CEK_0_CEK   (0xFFFFFFFFu)

+#define CONTROL_CEK_0_CEK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_1 */

+#define CONTROL_CEK_1_CEK   (0xFFFFFFFFu)

+#define CONTROL_CEK_1_CEK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_2 */

+#define CONTROL_CEK_2_CEK   (0xFFFFFFFFu)

+#define CONTROL_CEK_2_CEK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_3 */

+#define CONTROL_CEK_3_CEK   (0xFFFFFFFFu)

+#define CONTROL_CEK_3_CEK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_BCH_0 */

+#define CONTROL_CEK_BCH_0_CEK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CEK_BCH_0_CEK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_BCH_1 */

+#define CONTROL_CEK_BCH_1_CEK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CEK_BCH_1_CEK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_BCH_2 */

+#define CONTROL_CEK_BCH_2_CEK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CEK_BCH_2_CEK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_BCH_3 */

+#define CONTROL_CEK_BCH_3_CEK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CEK_BCH_3_CEK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CEK_BCH_4 */

+#define CONTROL_CEK_BCH_4_CEK_BCH   (0x0000FFFFu)

+#define CONTROL_CEK_BCH_4_CEK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MSV_0 */

+#define CONTROL_MSV_0_MSV   (0xFFFFFFFFu)

+#define CONTROL_MSV_0_MSV_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MSV_BCH_0 */

+#define CONTROL_MSV_BCH_0_MSV_BCH   (0xFFFFFFFFu)

+#define CONTROL_MSV_BCH_0_MSV_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_MSV_BCH_1 */

+#define CONTROL_MSV_BCH_1_MSV_BCH   (0xFFFFFFFFu)

+#define CONTROL_MSV_BCH_1_MSV_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_SEC_STATUS */

+#define CONTROL_SEC_STATUS_EMURST   (0x00000020u)

+#define CONTROL_SEC_STATUS_EMURST_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_STATUS_GFXDOMAINRST   (0x00000200u)

+#define CONTROL_SEC_STATUS_GFXDOMAINRST_SHIFT   (0x00000009u)

+

+#define CONTROL_SEC_STATUS_GLOBALCOLDRST   (0x00000001u)

+#define CONTROL_SEC_STATUS_GLOBALCOLDRST_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_STATUS_GLOBALWARMRST   (0x00000002u)

+#define CONTROL_SEC_STATUS_GLOBALWARMRST_SHIFT   (0x00000001u)

+

+#define CONTROL_SEC_STATUS_ICSS0RST   (0x00040000u)

+#define CONTROL_SEC_STATUS_ICSS0RST_SHIFT   (0x00000012u)

+

+#define CONTROL_SEC_STATUS_ICSS1RST   (0x00080000u)

+#define CONTROL_SEC_STATUS_ICSS1RST_SHIFT   (0x00000013u)

+

+#define CONTROL_SEC_STATUS_MPUDOMAINRST   (0x00000040u)

+#define CONTROL_SEC_STATUS_MPUDOMAINRST_SHIFT   (0x00000006u)

+

+#define CONTROL_SEC_STATUS_MPURST   (0x00020000u)

+#define CONTROL_SEC_STATUS_MPURST_SHIFT   (0x00000011u)

+

+#define CONTROL_SEC_STATUS_PERDOMAINRST   (0x00000080u)

+#define CONTROL_SEC_STATUS_PERDOMAINRST_SHIFT   (0x00000007u)

+

+#define CONTROL_SEC_STATUS_PUBWDRST   (0x00000004u)

+#define CONTROL_SEC_STATUS_PUBWDRST_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_STATUS_RSVD2   (0xFFF00000u)

+#define CONTROL_SEC_STATUS_RSVD2_SHIFT   (0x00000014u)

+

+#define CONTROL_SEC_STATUS_SECWDRST   (0x00000008u)

+#define CONTROL_SEC_STATUS_SECWDRST_SHIFT   (0x00000003u)

+

+#define CONTROL_SEC_STATUS_SSMVIOLATIONRST   (0x00000010u)

+#define CONTROL_SEC_STATUS_SSMVIOLATIONRST_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_STATUS_WKUPDOMAINRST   (0x00000100u)

+#define CONTROL_SEC_STATUS_WKUPDOMAINRST_SHIFT   (0x00000008u)

+

+

+/* CONTROL_SECMEM_STATUS */

+#define CONTROL_SECMEM_STATUS_A8L1DEST   (0x00000001u)

+#define CONTROL_SECMEM_STATUS_A8L1DEST_SHIFT   (0x00000000u)

+

+#define CONTROL_SECMEM_STATUS_A8L1NOTACC   (0x00010000u)

+#define CONTROL_SECMEM_STATUS_A8L1NOTACC_SHIFT   (0x00000010u)

+

+#define CONTROL_SECMEM_STATUS_A8L2DEST   (0x00000002u)

+#define CONTROL_SECMEM_STATUS_A8L2DEST_SHIFT   (0x00000001u)

+

+#define CONTROL_SECMEM_STATUS_A8L2NOTACC   (0x00020000u)

+#define CONTROL_SECMEM_STATUS_A8L2NOTACC_SHIFT   (0x00000011u)

+

+#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST   (0x00000004u)

+#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST_SHIFT   (0x00000002u)

+

+#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC   (0x00040000u)

+#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC_SHIFT   (0x00000012u)

+

+#define CONTROL_SECMEM_STATUS_L3SECRAMDEST   (0x00000008u)

+#define CONTROL_SECMEM_STATUS_L3SECRAMDEST_SHIFT   (0x00000003u)

+

+#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC   (0x00080000u)

+#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC_SHIFT   (0x00000013u)

+

+#define CONTROL_SECMEM_STATUS_RSVD2   (0xFFF00000u)

+#define CONTROL_SECMEM_STATUS_RSVD2_SHIFT   (0x00000014u)

+

+

+/* CONTROL_SEC_ERR_STAT_FUNC0 */

+#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR   (0x00000010u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR   (0x00000004u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR   (0x00000001u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2   (0x00000008u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2_SHIFT   (0x00000003u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3   (0x0001FFE0u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4   (0x007C0000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4_SHIFT   (0x00000012u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5   (0xF8000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR   (0x00020000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR_SHIFT   (0x00000011u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR   (0x01000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR_SHIFT   (0x00000018u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR   (0x02000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR_SHIFT   (0x00000019u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR   (0x04000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR_SHIFT   (0x0000001Au)

+

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR   (0x00800000u)

+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR_SHIFT   (0x00000017u)

+

+

+/* CONTROL_SEC_ERR_STAT_FUNC1 */

+#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR   (0x00000200u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR_SHIFT   (0x00000009u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR   (0x00100000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR_SHIFT   (0x00000014u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR   (0x00080000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR_SHIFT   (0x00000013u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR   (0x00020000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR_SHIFT   (0x00000011u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR   (0x00010000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR_SHIFT   (0x00000010u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR   (0x02000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR_SHIFT   (0x00000019u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR   (0x08000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR   (0x01000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR_SHIFT   (0x00000018u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR   (0x04000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR_SHIFT   (0x0000001Au)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR   (0x00000001u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR   (0x00000002u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR_SHIFT   (0x00000001u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR   (0x00008000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR_SHIFT   (0x0000000Fu)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2   (0x00000400u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2_SHIFT   (0x0000000Au)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3   (0x00006000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3_SHIFT   (0x0000000Du)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4   (0x00800000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4_SHIFT   (0x00000017u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5   (0xF0000000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5_SHIFT   (0x0000001Cu)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR   (0x00040000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR_SHIFT   (0x00000012u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR   (0x00400000u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR_SHIFT   (0x00000016u)

+

+#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR   (0x00000800u)

+#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR_SHIFT   (0x0000000Bu)

+

+

+/* CONTROL_SEC_ERR_STAT_DBUG0 */

+#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR   (0x00000010u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR_SHIFT   (0x00000004u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR   (0x00000004u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR_SHIFT   (0x00000002u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR   (0x00000001u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2   (0x00000008u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2_SHIFT   (0x00000003u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3   (0x0001FFE0u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3_SHIFT   (0x00000005u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4   (0x007C0000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4_SHIFT   (0x00000012u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5   (0xF8000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR   (0x00020000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR_SHIFT   (0x00000011u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR   (0x01000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR_SHIFT   (0x00000018u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR   (0x02000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR_SHIFT   (0x00000019u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR   (0x04000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR_SHIFT   (0x0000001Au)

+

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR   (0x00800000u)

+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR_SHIFT   (0x00000017u)

+

+

+/* CONTROL_SEC_ERR_STAT_DBUG1 */

+#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR   (0x00000200u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR_SHIFT   (0x00000009u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR   (0x00100000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR_SHIFT   (0x00000014u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR   (0x00080000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR_SHIFT   (0x00000013u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR   (0x00020000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR_SHIFT   (0x00000011u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR   (0x00010000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR_SHIFT   (0x00000010u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR   (0x02000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR_SHIFT   (0x00000019u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR   (0x08000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR_SHIFT   (0x0000001Bu)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR   (0x01000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR_SHIFT   (0x00000018u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR   (0x04000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR_SHIFT   (0x0000001Au)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR   (0x00000001u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR_SHIFT   (0x00000000u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR   (0x00000002u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR_SHIFT   (0x00000001u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR   (0x00008000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR_SHIFT   (0x0000000Fu)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2   (0x00000400u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2_SHIFT   (0x0000000Au)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3   (0x00006000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3_SHIFT   (0x0000000Du)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4   (0x00040000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4_SHIFT   (0x00000012u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5   (0x00800000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5_SHIFT   (0x00000017u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6   (0xF0000000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6_SHIFT   (0x0000001Cu)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR   (0x00400000u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR_SHIFT   (0x00000016u)

+

+#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR   (0x00000800u)

+#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR_SHIFT   (0x0000000Bu)

+

+

+/* CONTROL_KEK_SW_0 */

+#define CONTROL_KEK_SW_0_KEK_SW   (0xFFFFFFFFu)

+#define CONTROL_KEK_SW_0_KEK_SW_SHIFT   (0x00000000u)

+

+

+/* CONTROL_KEK_SW_1 */

+#define CONTROL_KEK_SW_1_KEK_SW   (0xFFFFFFFFu)

+#define CONTROL_KEK_SW_1_KEK_SW_SHIFT   (0x00000000u)

+

+

+/* CONTROL_KEK_SW_2 */

+#define CONTROL_KEK_SW_2_KEK_SW   (0xFFFFFFFFu)

+#define CONTROL_KEK_SW_2_KEK_SW_SHIFT   (0x00000000u)

+

+

+/* CONTROL_KEK_SW_3 */

+#define CONTROL_KEK_SW_3_KEK_SW   (0xFFFFFFFFu)

+#define CONTROL_KEK_SW_3_KEK_SW_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_0 */

+#define CONTROL_CMPK_BCH_0_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_0_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_1 */

+#define CONTROL_CMPK_BCH_1_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_1_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_2 */

+#define CONTROL_CMPK_BCH_2_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_2_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_3 */

+#define CONTROL_CMPK_BCH_3_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_3_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_4 */

+#define CONTROL_CMPK_BCH_4_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_4_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_5 */

+#define CONTROL_CMPK_BCH_5_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_5_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_6 */

+#define CONTROL_CMPK_BCH_6_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_6_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_7 */

+#define CONTROL_CMPK_BCH_7_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_7_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_BCH_8 */

+#define CONTROL_CMPK_BCH_8_CMPK_BCH   (0xFFFFFFFFu)

+#define CONTROL_CMPK_BCH_8_CMPK_BCH_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_0 */

+#define CONTROL_CMPK_0_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_0_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_1 */

+#define CONTROL_CMPK_1_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_1_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_2 */

+#define CONTROL_CMPK_2_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_2_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_3 */

+#define CONTROL_CMPK_3_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_3_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_4 */

+#define CONTROL_CMPK_4_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_4_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_5 */

+#define CONTROL_CMPK_5_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_5_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_6 */

+#define CONTROL_CMPK_6_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_6_CMPK_SHIFT   (0x00000000u)

+

+

+/* CONTROL_CMPK_7 */

+#define CONTROL_CMPK_7_CMPK   (0xFFFFFFFFu)

+#define CONTROL_CMPK_7_CMPK_SHIFT   (0x00000000u)

+

+

+/* SSM_END_FAST_SECRAM */

+#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM   (0x0000FC00u)

+#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_FAST_SECRAM_RSVD2   (0xFFFF0000u)

+#define CONTROL_SSM_END_FAST_SECRAM_RSVD2_SHIFT   (0x00000010u)

+

+

+/* SSM_FIREWALL_CONTROLLER */

+#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN   (0x00001000u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN   (0x00000800u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN_SHIFT   (0x0000000Bu)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN   (0x00000400u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN   (0x00000200u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN_SHIFT   (0x00000009u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN   (0x00000001u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN_SHIFT   (0x00000000u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN   (0x00000080u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN_SHIFT   (0x00000007u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN   (0x00000020u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN_SHIFT   (0x00000005u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN   (0x00000010u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN_SHIFT   (0x00000004u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN   (0x00000100u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN_SHIFT   (0x00000008u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN   (0x00000040u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN_SHIFT   (0x00000006u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN   (0x00000002u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN_SHIFT   (0x00000001u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN   (0x00000008u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN_SHIFT   (0x00000003u)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK   (0x00002000u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK_SHIFT   (0x0000000Du)

+

+#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN   (0x00000004u)

+#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN_SHIFT   (0x00000002u)

+

+

+/* SSM_START_SECURE_STACKED_RAM */

+#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM   (0xFFFF0000u)

+#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM_SHIFT   (0x00000010u)

+

+

+/* SSM_END_SECURE_STACKED_RAM */

+#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM   (0xFFFF0000u)

+#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM_SHIFT   (0x00000010u)

+

+

+/* SSM_START_SPM_STACK */

+#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK   (0xFFFFFC00u)

+#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK_SHIFT   (0x0000000Au)

+

+

+/* SSM_END_SPM_STACK */

+#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK   (0x0000FC00u)

+#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK   (0xFFFF0000u)

+#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK_SHIFT   (0x00000010u)

+

+

+/* SSM_START_MONITOR_RAMCODE */

+#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE   (0xFFFFFC00u)

+#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT   (0x0000000Au)

+

+

+/* SSM_END_MONITOR_RAMCODE */

+#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE   (0x0000FC00u)

+#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT   (0x00000010u)

+

+

+/* SSM_END_MONITOR_RAMDATA */

+#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA   (0x0000FC00u)

+#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE_SHIFT   (0x00000010u)

+

+

+/* SSM_START_MONITOR_CODE */

+#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE   (0xFFFFFC00u)

+#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE_SHIFT   (0x0000000Au)

+

+

+/* SSM_END_MONITOR_CODE */

+#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE   (0x0001FC00u)

+#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE   (0xFFFE0000u)

+#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE_SHIFT   (0x00000011u)

+

+

+/* SSM_START_MONITOR_PERIPH */

+#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_PERIPH */

+#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH   (0x0FFFF000u)

+#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH   (0xF0000000u)

+#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH_SHIFT   (0x0000001Cu)

+

+

+/* SSM_START_MONITOR_STACK */

+#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK   (0xFFFFFC00u)

+#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK_SHIFT   (0x0000000Au)

+

+

+/* SSM_END_MONITOR_STACK */

+#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK   (0x00007C00u)

+#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK   (0xFFFF8000u)

+#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK_SHIFT   (0x0000000Fu)

+

+

+/* SSM_START_MONITOR_RAMCODE_ETM */

+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_RAMCODE_ETM */

+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM   (0x0000F000u)

+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT   (0x00000010u)

+

+

+/* SSM_END_MONITOR_RAMDATA_ETM */

+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM   (0x0000F000u)

+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM_SHIFT   (0x00000010u)

+

+

+/* SSM_START_MONITOR_CODE_ETM */

+#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_CODE_ETM */

+#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM   (0x0001F000u)

+#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM   (0xFFFE0000u)

+#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT   (0x00000011u)

+

+

+/* SSM_START_MONITOR_STACK_ETM */

+#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_STACK_ETM */

+#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM   (0x0000F000u)

+#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT   (0x00000010u)

+

+

+/* SSM_START_MONITOR_SHARED_ETM */

+#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_SHARED_ETM */

+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM   (0x0000F000u)

+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM_SHIFT   (0x0000000Cu)

+

+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM   (0xFFFF0000u)

+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT   (0x00000010u)

+

+

+/* SSM_START_MONITOR_PERIPH_ETM */

+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_END_MONITOR_PERIPH_ETM */

+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM   (0xFFFFF000u)

+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM_SHIFT   (0x0000000Cu)

+

+

+/* SSM_CPSR_MODE_ENFC */

+#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON   (0x00000100u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON_SHIFT   (0x00000008u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON   (0x00000080u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON_SHIFT   (0x00000007u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON   (0x00000040u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON_SHIFT   (0x00000006u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC   (0x00000004u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC_SHIFT   (0x00000002u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC   (0x00000010u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC_SHIFT   (0x00000004u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC   (0x00000008u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC_SHIFT   (0x00000003u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC   (0x00000002u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC_SHIFT   (0x00000001u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC   (0x00000020u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC_SHIFT   (0x00000005u)

+

+#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC   (0x00000001u)

+#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC_SHIFT   (0x00000000u)

+

+

+/* SSM_END_L3_SECRAM */

+#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM   (0x0000FC00u)

+#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM_SHIFT   (0x0000000Au)

+

+#define CONTROL_SSM_END_L3_SECRAM_RSVD2   (0xFFFF0000u)

+#define CONTROL_SSM_END_L3_SECRAM_RSVD2_SHIFT   (0x00000010u)

+

+

+/* CORTEX_VBBLDO_CTRL */

+#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL   (0x00000004u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL_SHIFT   (0x00000002u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_HZ   (0x00000008u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_HZ_SHIFT   (0x00000003u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ   (0x00000020u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ_SHIFT   (0x00000005u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR   (0x00000010u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR_SHIFT   (0x00000004u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP   (0x00000002u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP_SHIFT   (0x00000001u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR   (0x00000001u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR_SHIFT   (0x00000000u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2   (0xFC000000u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2_SHIFT   (0x0000001Au)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB   (0x03E00000u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB_SHIFT   (0x00000015u)

+

+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB   (0x001F0000u)

+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB_SHIFT   (0x00000010u)

+

+

+/* CORE_SLDO_CTRL */

+#define CONTROL_CORE_SLDO_CTRL_RSVD2   (0xFC000000u)

+#define CONTROL_CORE_SLDO_CTRL_RSVD2_SHIFT   (0x0000001Au)

+

+#define CONTROL_CORE_SLDO_CTRL_VSET   (0x03FF0000u)

+#define CONTROL_CORE_SLDO_CTRL_VSET_SHIFT   (0x00000010u)

+

+

+/* MPU_SLDO_CTRL */

+#define CONTROL_MPU_SLDO_CTRL_RSVD2   (0xFC000000u)

+#define CONTROL_MPU_SLDO_CTRL_RSVD2_SHIFT   (0x0000001Au)

+

+#define CONTROL_MPU_SLDO_CTRL_VSET   (0x03FF0000u)

+#define CONTROL_MPU_SLDO_CTRL_VSET_SHIFT   (0x00000010u)

+

+

+/* REFCLK_LJCBLDO_CTRL */

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF   (0x00000040u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF_SHIFT   (0x00000006u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF   (0x00000080u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF_SHIFT   (0x00000007u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1   (0x00000001u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1_SHIFT   (0x00000000u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2   (0x00000002u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2_SHIFT   (0x00000001u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3   (0x00000004u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3_SHIFT   (0x00000002u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4   (0x00000008u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4_SHIFT   (0x00000003u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5   (0x00000010u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5_SHIFT   (0x00000004u)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2   (0xFC000000u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2_SHIFT   (0x0000001Au)

+

+#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET   (0x03FF0000u)

+#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET_SHIFT   (0x00000010u)

+

+

+/* CLK32KDIVRATIO_CTRL */

+#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN   (0x00000001u)

+#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN_SHIFT   (0x00000000u)

+

+

+/* BANDGAP_CTRL */

+#define CONTROL_BANDGAP_CTRL_BGROFF   (0x00000040u)

+#define CONTROL_BANDGAP_CTRL_BGROFF_SHIFT   (0x00000006u)

+

+#define CONTROL_BANDGAP_CTRL_CBIASSEL   (0x00000080u)

+#define CONTROL_BANDGAP_CTRL_CBIASSEL_SHIFT   (0x00000007u)

+

+#define CONTROL_BANDGAP_CTRL_CLRZ   (0x00000008u)

+#define CONTROL_BANDGAP_CTRL_CLRZ_SHIFT   (0x00000003u)

+

+#define CONTROL_BANDGAP_CTRL_CONTCONV   (0x00000004u)

+#define CONTROL_BANDGAP_CTRL_CONTCONV_SHIFT   (0x00000002u)

+

+#define CONTROL_BANDGAP_CTRL_DTEMP   (0x0000FF00u)

+#define CONTROL_BANDGAP_CTRL_DTEMP_SHIFT   (0x00000008u)

+

+#define CONTROL_BANDGAP_CTRL_ECOZ   (0x00000002u)

+#define CONTROL_BANDGAP_CTRL_ECOZ_SHIFT   (0x00000001u)

+

+#define CONTROL_BANDGAP_CTRL_SOC   (0x00000010u)

+#define CONTROL_BANDGAP_CTRL_SOC_SHIFT   (0x00000004u)

+

+#define CONTROL_BANDGAP_CTRL_TMPSOFF   (0x00000020u)

+#define CONTROL_BANDGAP_CTRL_TMPSOFF_SHIFT   (0x00000005u)

+

+#define CONTROL_BANDGAP_CTRL_TSHUT   (0x00000001u)

+#define CONTROL_BANDGAP_CTRL_TSHUT_SHIFT   (0x00000000u)

+

+

+/* BANDGAP_TRIM */

+#define CONTROL_BANDGAP_TRIM_DTRBGAPC   (0xFF000000u)

+#define CONTROL_BANDGAP_TRIM_DTRBGAPC_SHIFT   (0x00000018u)

+

+#define CONTROL_BANDGAP_TRIM_DTRBGAPV   (0x00FF0000u)

+#define CONTROL_BANDGAP_TRIM_DTRBGAPV_SHIFT   (0x00000010u)

+

+#define CONTROL_BANDGAP_TRIM_DTRTEMPS   (0x0000FF00u)

+#define CONTROL_BANDGAP_TRIM_DTRTEMPS_SHIFT   (0x00000008u)

+

+#define CONTROL_BANDGAP_TRIM_DTRTEMPSC   (0x000000FFu)

+#define CONTROL_BANDGAP_TRIM_DTRTEMPSC_SHIFT   (0x00000000u)

+

+

+/* PLL_CLKINPULOW_CTRL */

+#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL   (0x00000004u)

+#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL_SHIFT   (0x00000002u)

+

+#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL   (0x00000002u)

+#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL_SHIFT   (0x00000001u)

+

+#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL   (0x00000001u)

+#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL_SHIFT   (0x00000000u)

+

+

+/* MOSC_CTRL */

+#define CONTROL_MOSC_CTRL_RESSELECT   (0x00000001u)

+#define CONTROL_MOSC_CTRL_RESSELECT_SHIFT   (0x00000000u)

+

+

+/* RCOSC_CTRL */

+#define CONTROL_RCOSC_CTRL_STOPOSC   (0x00000001u)

+#define CONTROL_RCOSC_CTRL_STOPOSC_SHIFT   (0x00000000u)

+

+

+/* DEEPSLEEP_CTRL */

+#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT   (0x0000FFFFu)

+#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT_SHIFT   (0x00000000u)

+

+#define CONTROL_DEEPSLEEP_CTRL_DSENABLE   (0x00020000u)

+#define CONTROL_DEEPSLEEP_CTRL_DSENABLE_SHIFT   (0x00000011u)

+

+#define CONTROL_DEEPSLEEP_CTRL_RSVD2   (0xFFFC0000u)

+#define CONTROL_DEEPSLEEP_CTRL_RSVD2_SHIFT   (0x00000012u)

+

+

+/* PE_SCRATCHPAD_0 */

+#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0   (0xFFFFFFFFu)

+#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0_SHIFT   (0x00000000u)

+

+

+/* PE_SCRATCHPAD_1 */

+#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1   (0xFFFFFFFFu)

+#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1_SHIFT   (0x00000000u)

+

+

+/* PE_SCRATCHPAD_2 */

+#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2   (0xFFFFFFFFu)

+#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2_SHIFT   (0x00000000u)

+

+

+/* PE_SCRATCHPAD_3 */

+#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3   (0xFFFFFFFFu)

+#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3_SHIFT   (0x00000000u)

+

+

+/* DEVICE_ID */

+#define CONTROL_DEVICE_ID_DEVREV   (0xF0000000u)

+#define CONTROL_DEVICE_ID_DEVREV_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DEVICE_ID_MFGR   (0x00000FFEu)

+#define CONTROL_DEVICE_ID_MFGR_SHIFT   (0x00000001u)

+

+#define CONTROL_DEVICE_ID_PARTNUM   (0x0FFFF000u)

+#define CONTROL_DEVICE_ID_PARTNUM_SHIFT   (0x0000000Cu)

+

+

+/* DEV_FEATURE */

+#define CONTROL_DEV_FEATURE_CPSW   (0x00000002u)

+#define CONTROL_DEV_FEATURE_CPSW_SHIFT   (0x00000001u)

+

+#define CONTROL_DEV_FEATURE_DCAN   (0x00000080u)

+#define CONTROL_DEV_FEATURE_DCAN_SHIFT   (0x00000007u)

+

+#define CONTROL_DEV_FEATURE_ICSS   (0x00000001u)

+#define CONTROL_DEV_FEATURE_ICSS_SHIFT   (0x00000000u)

+

+#define CONTROL_DEV_FEATURE_ICSS_FEA   (0x00FF0000u)

+#define CONTROL_DEV_FEATURE_ICSS_FEA_SHIFT   (0x00000010u)

+

+#define CONTROL_DEV_FEATURE_RSVD2   (0x0000FC00u)

+#define CONTROL_DEV_FEATURE_RSVD2_SHIFT   (0x0000000Au)

+

+#define CONTROL_DEV_FEATURE_RSVD3   (0x1F000000u)

+#define CONTROL_DEV_FEATURE_RSVD3_SHIFT   (0x00000018u)

+

+#define CONTROL_DEV_FEATURE_RSVD4   (0xC0000000u)

+#define CONTROL_DEV_FEATURE_RSVD4_SHIFT   (0x0000001Eu)

+

+#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA   (0x00000200u)

+#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA_SHIFT   (0x00000009u)

+

+#define CONTROL_DEV_FEATURE_SGX   (0x20000000u)

+#define CONTROL_DEV_FEATURE_SGX_SHIFT   (0x0000001Du)

+

+

+/* INIT_PRIORITY_0 */

+#define CONTROL_INIT_PRIORITY_0_HOST_ARM   (0x00000003u)

+#define CONTROL_INIT_PRIORITY_0_HOST_ARM_SHIFT   (0x00000000u)

+

+#define CONTROL_INIT_PRIORITY_0_MMU   (0x000000C0u)

+#define CONTROL_INIT_PRIORITY_0_MMU_SHIFT   (0x00000006u)

+

+#define CONTROL_INIT_PRIORITY_0_P1500   (0x0000C000u)

+#define CONTROL_INIT_PRIORITY_0_P1500_SHIFT   (0x0000000Eu)

+

+#define CONTROL_INIT_PRIORITY_0_PRUSS0   (0x0000000Cu)

+#define CONTROL_INIT_PRIORITY_0_PRUSS0_SHIFT   (0x00000002u)

+

+#define CONTROL_INIT_PRIORITY_0_PRUSS1   (0x00000030u)

+#define CONTROL_INIT_PRIORITY_0_PRUSS1_SHIFT   (0x00000004u)

+

+#define CONTROL_INIT_PRIORITY_0_RSVD2   (0xF0000000u)

+#define CONTROL_INIT_PRIORITY_0_RSVD2_SHIFT   (0x0000001Cu)

+

+#define CONTROL_INIT_PRIORITY_0_TCRD0   (0x00030000u)

+#define CONTROL_INIT_PRIORITY_0_TCRD0_SHIFT   (0x00000010u)

+

+#define CONTROL_INIT_PRIORITY_0_TCRD1   (0x00300000u)

+#define CONTROL_INIT_PRIORITY_0_TCRD1_SHIFT   (0x00000014u)

+

+#define CONTROL_INIT_PRIORITY_0_TCRD2   (0x03000000u)

+#define CONTROL_INIT_PRIORITY_0_TCRD2_SHIFT   (0x00000018u)

+

+#define CONTROL_INIT_PRIORITY_0_TCWR0   (0x000C0000u)

+#define CONTROL_INIT_PRIORITY_0_TCWR0_SHIFT   (0x00000012u)

+

+#define CONTROL_INIT_PRIORITY_0_TCWR1   (0x00C00000u)

+#define CONTROL_INIT_PRIORITY_0_TCWR1_SHIFT   (0x00000016u)

+

+#define CONTROL_INIT_PRIORITY_0_TCWR2   (0x0C000000u)

+#define CONTROL_INIT_PRIORITY_0_TCWR2_SHIFT   (0x0000001Au)

+

+

+/* INIT_PRIORITY_1 */

+#define CONTROL_INIT_PRIORITY_1_CPSW   (0x00000003u)

+#define CONTROL_INIT_PRIORITY_1_CPSW_SHIFT   (0x00000000u)

+

+#define CONTROL_INIT_PRIORITY_1_DEBUG   (0x03000000u)

+#define CONTROL_INIT_PRIORITY_1_DEBUG_SHIFT   (0x00000018u)

+

+#define CONTROL_INIT_PRIORITY_1_LCD   (0x00C00000u)

+#define CONTROL_INIT_PRIORITY_1_LCD_SHIFT   (0x00000016u)

+

+#define CONTROL_INIT_PRIORITY_1_RSVD2   (0x0000FF00u)

+#define CONTROL_INIT_PRIORITY_1_RSVD2_SHIFT   (0x00000008u)

+

+#define CONTROL_INIT_PRIORITY_1_RSVD3   (0x000C0000u)

+#define CONTROL_INIT_PRIORITY_1_RSVD3_SHIFT   (0x00000012u)

+

+#define CONTROL_INIT_PRIORITY_1_RSVD4   (0xFC000000u)

+#define CONTROL_INIT_PRIORITY_1_RSVD4_SHIFT   (0x0000001Au)

+

+#define CONTROL_INIT_PRIORITY_1_SGX   (0x00300000u)

+#define CONTROL_INIT_PRIORITY_1_SGX_SHIFT   (0x00000014u)

+

+#define CONTROL_INIT_PRIORITY_1_USB_DMA   (0x00000030u)

+#define CONTROL_INIT_PRIORITY_1_USB_DMA_SHIFT   (0x00000004u)

+

+#define CONTROL_INIT_PRIORITY_1_USB_QMGR   (0x000000C0u)

+#define CONTROL_INIT_PRIORITY_1_USB_QMGR_SHIFT   (0x00000006u)

+

+

+/* MMU_CFG */

+#define CONTROL_MMU_CFG_MMU_ABORT   (0x00008000u)

+#define CONTROL_MMU_CFG_MMU_ABORT_SHIFT   (0x0000000Fu)

+

+#define CONTROL_MMU_CFG_MMU_DISABLE   (0x00000080u)

+#define CONTROL_MMU_CFG_MMU_DISABLE_SHIFT   (0x00000007u)

+

+#define CONTROL_MMU_CFG_RSVD2   (0x00007F00u)

+#define CONTROL_MMU_CFG_RSVD2_SHIFT   (0x00000008u)

+

+#define CONTROL_MMU_CFG_RSVD3   (0xFFFF0000u)

+#define CONTROL_MMU_CFG_RSVD3_SHIFT   (0x00000010u)

+

+

+/* TPTC_CFG */

+#define CONTROL_TPTC_CFG_TC0DBS   (0x00000003u)

+#define CONTROL_TPTC_CFG_TC0DBS_SHIFT   (0x00000000u)

+

+#define CONTROL_TPTC_CFG_TC1DBS   (0x0000000Cu)

+#define CONTROL_TPTC_CFG_TC1DBS_SHIFT   (0x00000002u)

+

+#define CONTROL_TPTC_CFG_TC2DBS   (0x00000030u)

+#define CONTROL_TPTC_CFG_TC2DBS_SHIFT   (0x00000004u)

+

+

+/* OCMC_CFG */

+#define CONTROL_OCMC_CFG_PAR_EN   (0x00000001u)

+#define CONTROL_OCMC_CFG_PAR_EN_SHIFT   (0x00000000u)

+

+#define CONTROL_OCMC_CFG_PAR_INT_CLR   (0x00000010u)

+#define CONTROL_OCMC_CFG_PAR_INT_CLR_SHIFT   (0x00000004u)

+

+#define CONTROL_OCMC_CFG_PAR_RESP_EN   (0x00000002u)

+#define CONTROL_OCMC_CFG_PAR_RESP_EN_SHIFT   (0x00000001u)

+

+#define CONTROL_OCMC_CFG_RSVD2   (0xFFFFFFE0u)

+#define CONTROL_OCMC_CFG_RSVD2_SHIFT   (0x00000005u)

+

+

+/* USB_CTRL0 */

+#define CONTROL_USB_CTRL0_CDET_EXTCTL   (0x00000400u)

+#define CONTROL_USB_CTRL0_CDET_EXTCTL_SHIFT   (0x0000000Au)

+

+#define CONTROL_USB_CTRL0_CHGDET_DIS   (0x00000004u)

+#define CONTROL_USB_CTRL0_CHGDET_DIS_SHIFT   (0x00000002u)

+

+#define CONTROL_USB_CTRL0_CHGDET_RSTRT   (0x00000008u)

+#define CONTROL_USB_CTRL0_CHGDET_RSTRT_SHIFT   (0x00000003u)

+

+#define CONTROL_USB_CTRL0_CHGISINK_EN   (0x00000040u)

+#define CONTROL_USB_CTRL0_CHGISINK_EN_SHIFT   (0x00000006u)

+

+#define CONTROL_USB_CTRL0_CHGVSRC_EN   (0x00000080u)

+#define CONTROL_USB_CTRL0_CHGVSRC_EN_SHIFT   (0x00000007u)

+

+#define CONTROL_USB_CTRL0_CM_PWRDN   (0x00000001u)

+#define CONTROL_USB_CTRL0_CM_PWRDN_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_CTRL0_DATAPOLARITY_INV   (0x00800000u)

+#define CONTROL_USB_CTRL0_DATAPOLARITY_INV_SHIFT   (0x00000017u)

+

+#define CONTROL_USB_CTRL0_DMGPIO_PD   (0x00040000u)

+#define CONTROL_USB_CTRL0_DMGPIO_PD_SHIFT   (0x00000012u)

+

+#define CONTROL_USB_CTRL0_DMPULLUP   (0x00000100u)

+#define CONTROL_USB_CTRL0_DMPULLUP_SHIFT   (0x00000008u)

+

+#define CONTROL_USB_CTRL0_DPGPIO_PD   (0x00020000u)

+#define CONTROL_USB_CTRL0_DPGPIO_PD_SHIFT   (0x00000011u)

+

+#define CONTROL_USB_CTRL0_DPPULLUP   (0x00000200u)

+#define CONTROL_USB_CTRL0_DPPULLUP_SHIFT   (0x00000009u)

+

+#define CONTROL_USB_CTRL0_GPIOMODE   (0x00001000u)

+#define CONTROL_USB_CTRL0_GPIOMODE_SHIFT   (0x0000000Cu)

+

+#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS   (0x00004000u)

+#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS_SHIFT   (0x0000000Eu)

+

+#define CONTROL_USB_CTRL0_GPIO_SIG_INV   (0x00002000u)

+#define CONTROL_USB_CTRL0_GPIO_SIG_INV_SHIFT   (0x0000000Du)

+

+#define CONTROL_USB_CTRL0_OTGSESSENDEN   (0x00100000u)

+#define CONTROL_USB_CTRL0_OTGSESSENDEN_SHIFT   (0x00000014u)

+

+#define CONTROL_USB_CTRL0_OTGVDET_EN   (0x00080000u)

+#define CONTROL_USB_CTRL0_OTGVDET_EN_SHIFT   (0x00000013u)

+

+#define CONTROL_USB_CTRL0_OTG_PWRDN   (0x00000002u)

+#define CONTROL_USB_CTRL0_OTG_PWRDN_SHIFT   (0x00000001u)

+

+#define CONTROL_USB_CTRL0_RSVD2   (0x00008000u)

+#define CONTROL_USB_CTRL0_RSVD2_SHIFT   (0x0000000Fu)

+

+#define CONTROL_USB_CTRL0_RSVD3   (0x00010000u)

+#define CONTROL_USB_CTRL0_RSVD3_SHIFT   (0x00000010u)

+

+#define CONTROL_USB_CTRL0_SINKONDP   (0x00000020u)

+#define CONTROL_USB_CTRL0_SINKONDP_SHIFT   (0x00000005u)

+

+#define CONTROL_USB_CTRL0_SPAREIN   (0xFF000000u)

+#define CONTROL_USB_CTRL0_SPAREIN_SHIFT   (0x00000018u)

+

+#define CONTROL_USB_CTRL0_SRCONDM   (0x00000010u)

+#define CONTROL_USB_CTRL0_SRCONDM_SHIFT   (0x00000004u)

+

+#define CONTROL_USB_CTRL0_USB_PHY_SMA1   (0x00200000u)

+#define CONTROL_USB_CTRL0_USB_PHY_SMA1_SHIFT   (0x00000015u)

+

+#define CONTROL_USB_CTRL0_USB_PHY_SMA2   (0x00400000u)

+#define CONTROL_USB_CTRL0_USB_PHY_SMA2_SHIFT   (0x00000016u)

+

+

+/* USB_STS0 */

+#define CONTROL_USB_STS0_CDET_DATADET   (0x00000004u)

+#define CONTROL_USB_STS0_CDET_DATADET_SHIFT   (0x00000002u)

+

+#define CONTROL_USB_STS0_CDET_DMDET   (0x00000010u)

+#define CONTROL_USB_STS0_CDET_DMDET_SHIFT   (0x00000004u)

+

+#define CONTROL_USB_STS0_CDET_DPDET   (0x00000008u)

+#define CONTROL_USB_STS0_CDET_DPDET_SHIFT   (0x00000003u)

+

+#define CONTROL_USB_STS0_CHGDETDONE   (0x00000001u)

+#define CONTROL_USB_STS0_CHGDETDONE_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_STS0_CHGDETECT   (0x00000002u)

+#define CONTROL_USB_STS0_CHGDETECT_SHIFT   (0x00000001u)

+

+#define CONTROL_USB_STS0_CHGDETSTS   (0x000000E0u)

+#define CONTROL_USB_STS0_CHGDETSTS_SHIFT   (0x00000005u)

+

+

+/* USB_CTRL1 */

+#define CONTROL_USB_CTRL1_CDET_EXTCTL   (0x00000400u)

+#define CONTROL_USB_CTRL1_CDET_EXTCTL_SHIFT   (0x0000000Au)

+

+#define CONTROL_USB_CTRL1_CHGDET_DIS   (0x00000004u)

+#define CONTROL_USB_CTRL1_CHGDET_DIS_SHIFT   (0x00000002u)

+

+#define CONTROL_USB_CTRL1_CHGDET_RSTRT   (0x00000008u)

+#define CONTROL_USB_CTRL1_CHGDET_RSTRT_SHIFT   (0x00000003u)

+

+#define CONTROL_USB_CTRL1_CHGISINK_EN   (0x00000040u)

+#define CONTROL_USB_CTRL1_CHGISINK_EN_SHIFT   (0x00000006u)

+

+#define CONTROL_USB_CTRL1_CHGVSRC_EN   (0x00000080u)

+#define CONTROL_USB_CTRL1_CHGVSRC_EN_SHIFT   (0x00000007u)

+

+#define CONTROL_USB_CTRL1_CM_PWRDN   (0x00000001u)

+#define CONTROL_USB_CTRL1_CM_PWRDN_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_CTRL1_DATAPOLARITY_INV   (0x00800000u)

+#define CONTROL_USB_CTRL1_DATAPOLARITY_INV_SHIFT   (0x00000017u)

+

+#define CONTROL_USB_CTRL1_DMGPIO_PD   (0x00040000u)

+#define CONTROL_USB_CTRL1_DMGPIO_PD_SHIFT   (0x00000012u)

+

+#define CONTROL_USB_CTRL1_DMPULLUP   (0x00000100u)

+#define CONTROL_USB_CTRL1_DMPULLUP_SHIFT   (0x00000008u)

+

+#define CONTROL_USB_CTRL1_DPGPIO_PD   (0x00020000u)

+#define CONTROL_USB_CTRL1_DPGPIO_PD_SHIFT   (0x00000011u)

+

+#define CONTROL_USB_CTRL1_DPPULLUP   (0x00000200u)

+#define CONTROL_USB_CTRL1_DPPULLUP_SHIFT   (0x00000009u)

+

+#define CONTROL_USB_CTRL1_GPIOMODE   (0x00001000u)

+#define CONTROL_USB_CTRL1_GPIOMODE_SHIFT   (0x0000000Cu)

+

+#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS   (0x00004000u)

+#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS_SHIFT   (0x0000000Eu)

+

+#define CONTROL_USB_CTRL1_GPIO_SIG_INV   (0x00002000u)

+#define CONTROL_USB_CTRL1_GPIO_SIG_INV_SHIFT   (0x0000000Du)

+

+#define CONTROL_USB_CTRL1_OTGSESSENDEN   (0x00100000u)

+#define CONTROL_USB_CTRL1_OTGSESSENDEN_SHIFT   (0x00000014u)

+

+#define CONTROL_USB_CTRL1_OTGVDET_EN   (0x00080000u)

+#define CONTROL_USB_CTRL1_OTGVDET_EN_SHIFT   (0x00000013u)

+

+#define CONTROL_USB_CTRL1_OTG_PWRDN   (0x00000002u)

+#define CONTROL_USB_CTRL1_OTG_PWRDN_SHIFT   (0x00000001u)

+

+#define CONTROL_USB_CTRL1_RSVD2   (0x00008000u)

+#define CONTROL_USB_CTRL1_RSVD2_SHIFT   (0x0000000Fu)

+

+#define CONTROL_USB_CTRL1_RSVD3   (0x00010000u)

+#define CONTROL_USB_CTRL1_RSVD3_SHIFT   (0x00000010u)

+

+#define CONTROL_USB_CTRL1_SINKONDP   (0x00000020u)

+#define CONTROL_USB_CTRL1_SINKONDP_SHIFT   (0x00000005u)

+

+#define CONTROL_USB_CTRL1_SPAREIN   (0xFF000000u)

+#define CONTROL_USB_CTRL1_SPAREIN_SHIFT   (0x00000018u)

+

+#define CONTROL_USB_CTRL1_SRCONDM   (0x00000010u)

+#define CONTROL_USB_CTRL1_SRCONDM_SHIFT   (0x00000004u)

+

+#define CONTROL_USB_CTRL1_USB_PHY_SMA1   (0x00200000u)

+#define CONTROL_USB_CTRL1_USB_PHY_SMA1_SHIFT   (0x00000015u)

+

+#define CONTROL_USB_CTRL1_USB_PHY_SMA2   (0x00400000u)

+#define CONTROL_USB_CTRL1_USB_PHY_SMA2_SHIFT   (0x00000016u)

+

+

+/* USB_STS1 */

+#define CONTROL_USB_STS1_CDET_DATADET   (0x00000004u)

+#define CONTROL_USB_STS1_CDET_DATADET_SHIFT   (0x00000002u)

+

+#define CONTROL_USB_STS1_CDET_DMDET   (0x00000010u)

+#define CONTROL_USB_STS1_CDET_DMDET_SHIFT   (0x00000004u)

+

+#define CONTROL_USB_STS1_CDET_DPDET   (0x00000008u)

+#define CONTROL_USB_STS1_CDET_DPDET_SHIFT   (0x00000003u)

+

+#define CONTROL_USB_STS1_CHGDETDONE   (0x00000001u)

+#define CONTROL_USB_STS1_CHGDETDONE_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_STS1_CHGDETECT   (0x00000002u)

+#define CONTROL_USB_STS1_CHGDETECT_SHIFT   (0x00000001u)

+

+#define CONTROL_USB_STS1_CHGDETSTS   (0x000000E0u)

+#define CONTROL_USB_STS1_CHGDETSTS_SHIFT   (0x00000005u)

+

+

+/* MAC_ID0_LO */

+#define CONTROL_MAC_ID0_LO_MACADDR_15_8   (0x000000FFu)

+#define CONTROL_MAC_ID0_LO_MACADDR_15_8_SHIFT   (0x00000000u)

+

+#define CONTROL_MAC_ID0_LO_MACADDR_7_0   (0x0000FF00u)

+#define CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT   (0x00000008u)

+

+

+/* MAC_ID0_HI */

+#define CONTROL_MAC_ID0_HI_MACADDR_23_16   (0xFF000000u)

+#define CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT   (0x00000018u)

+

+#define CONTROL_MAC_ID0_HI_MACADDR_31_24   (0x00FF0000u)

+#define CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT   (0x00000010u)

+

+#define CONTROL_MAC_ID0_HI_MACADDR_39_32   (0x0000FF00u)

+#define CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT   (0x00000008u)

+

+#define CONTROL_MAC_ID0_HI_MACADDR_47_40   (0x000000FFu)

+#define CONTROL_MAC_ID0_HI_MACADDR_47_40_SHIFT   (0x00000000u)

+

+

+/* MAC_ID1_LO */

+#define CONTROL_MAC_ID1_LO_MACADDR_15_8   (0x000000FFu)

+#define CONTROL_MAC_ID1_LO_MACADDR_15_8_SHIFT   (0x00000000u)

+

+#define CONTROL_MAC_ID1_LO_MACADDR_7_0   (0x0000FF00u)

+#define CONTROL_MAC_ID1_LO_MACADDR_7_0_SHIFT   (0x00000008u)

+

+

+/* MAC_ID1_HI */

+#define CONTROL_MAC_ID1_HI_MACADDR_23_16   (0xFF000000u)

+#define CONTROL_MAC_ID1_HI_MACADDR_23_16_SHIFT   (0x00000018u)

+

+#define CONTROL_MAC_ID1_HI_MACADDR_31_24   (0x00FF0000u)

+#define CONTROL_MAC_ID1_HI_MACADDR_31_24_SHIFT   (0x00000010u)

+

+#define CONTROL_MAC_ID1_HI_MACADDR_39_32   (0x0000FF00u)

+#define CONTROL_MAC_ID1_HI_MACADDR_39_32_SHIFT   (0x00000008u)

+

+#define CONTROL_MAC_ID1_HI_MACADDR_47_40   (0x000000FFu)

+#define CONTROL_MAC_ID1_HI_MACADDR_47_40_SHIFT   (0x00000000u)

+

+

+/* DCAN_RAMINIT */

+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE   (0x00000100u)

+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE_SHIFT   (0x00000008u)

+

+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START   (0x00000001u)

+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START_SHIFT   (0x00000000u)

+

+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE   (0x00000200u)

+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE_SHIFT   (0x00000009u)

+

+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START   (0x00000002u)

+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START_SHIFT   (0x00000001u)

+

+#define CONTROL_DCAN_RAMINIT_RSVD2   (0xFFFFFC00u)

+#define CONTROL_DCAN_RAMINIT_RSVD2_SHIFT   (0x0000000Au)

+

+

+/* USB_WKUP_CTRL */

+#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN   (0x00000001u)

+#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN   (0x00000100u)

+#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN_SHIFT   (0x00000008u)

+

+#define CONTROL_USB_WKUP_CTRL_RSVD2   (0xFFFFFE00u)

+#define CONTROL_USB_WKUP_CTRL_RSVD2_SHIFT   (0x00000009u)

+

+

+/* GMII_SEL */

+#define CONTROL_GMII_SEL_GMII1_SEL   (0x00000003u)

+#define CONTROL_GMII_SEL_GMII1_SEL_SHIFT   (0x00000000u)

+

+#define CONTROL_GMII_SEL_GMII2_SEL   (0x0000000Cu)

+#define CONTROL_GMII_SEL_GMII2_SEL_SHIFT   (0x00000002u)

+

+#define CONTROL_GMII_SEL_RGMII1_IDMODE   (0x00000010u)

+#define CONTROL_GMII_SEL_RGMII1_IDMODE_SHIFT   (0x00000004u)

+

+#define CONTROL_GMII_SEL_RGMII2_IDMOE   (0x00000020u)

+#define CONTROL_GMII_SEL_RGMII2_IDMOE_SHIFT   (0x00000005u)

+

+#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN   (0x00000040u)

+#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN_SHIFT   (0x00000006u)

+

+#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN   (0x00000080u)

+#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN_SHIFT   (0x00000007u)

+

+

+/* PWMSS_CTRL */

+#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN   (0x00000002u)

+#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN_SHIFT   (0x00000001u)

+

+#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN   (0x00000001u)

+#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN_SHIFT   (0x00000000u)

+

+#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN   (0x00000004u)

+#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN_SHIFT   (0x00000002u)

+

+

+/* MREQPRIO_0 */

+#define CONTROL_MREQPRIO_0_CPSW   (0x00070000u)

+#define CONTROL_MREQPRIO_0_CPSW_SHIFT   (0x00000010u)

+

+#define CONTROL_MREQPRIO_0_PRUSS1_PRU0   (0x00000700u)

+#define CONTROL_MREQPRIO_0_PRUSS1_PRU0_SHIFT   (0x00000008u)

+

+#define CONTROL_MREQPRIO_0_PRUSS1_PRU1   (0x00007000u)

+#define CONTROL_MREQPRIO_0_PRUSS1_PRU1_SHIFT   (0x0000000Cu)

+

+#define CONTROL_MREQPRIO_0_RSVD2   (0x00000080u)

+#define CONTROL_MREQPRIO_0_RSVD2_SHIFT   (0x00000007u)

+

+#define CONTROL_MREQPRIO_0_RSVD3   (0x00000800u)

+#define CONTROL_MREQPRIO_0_RSVD3_SHIFT   (0x0000000Bu)

+

+#define CONTROL_MREQPRIO_0_RSVD4   (0x00008000u)

+#define CONTROL_MREQPRIO_0_RSVD4_SHIFT   (0x0000000Fu)

+

+#define CONTROL_MREQPRIO_0_RSVD5   (0x00080000u)

+#define CONTROL_MREQPRIO_0_RSVD5_SHIFT   (0x00000013u)

+

+#define CONTROL_MREQPRIO_0_RSVD6   (0x00800000u)

+#define CONTROL_MREQPRIO_0_RSVD6_SHIFT   (0x00000017u)

+

+#define CONTROL_MREQPRIO_0_RSVD7   (0x08000000u)

+#define CONTROL_MREQPRIO_0_RSVD7_SHIFT   (0x0000001Bu)

+

+#define CONTROL_MREQPRIO_0_RSVD8   (0x80000000u)

+#define CONTROL_MREQPRIO_0_RSVD8_SHIFT   (0x0000001Fu)

+

+#define CONTROL_MREQPRIO_0_SAB_INIT0   (0x00000007u)

+#define CONTROL_MREQPRIO_0_SAB_INIT0_SHIFT   (0x00000000u)

+

+#define CONTROL_MREQPRIO_0_SAB_INIT1   (0x00000070u)

+#define CONTROL_MREQPRIO_0_SAB_INIT1_SHIFT   (0x00000004u)

+

+#define CONTROL_MREQPRIO_0_SGX   (0x70000000u)

+#define CONTROL_MREQPRIO_0_SGX_SHIFT   (0x0000001Cu)

+

+#define CONTROL_MREQPRIO_0_USB0   (0x00700000u)

+#define CONTROL_MREQPRIO_0_USB0_SHIFT   (0x00000014u)

+

+#define CONTROL_MREQPRIO_0_USB1   (0x07000000u)

+#define CONTROL_MREQPRIO_0_USB1_SHIFT   (0x00000018u)

+

+

+/* MREQPRIO_1 */

+#define CONTROL_MREQPRIO_1_EXP   (0x00000007u)

+#define CONTROL_MREQPRIO_1_EXP_SHIFT   (0x00000000u)

+

+

+/* HW_EVENT_SEL_GRP1 */

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1   (0x000000FFu)

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1_SHIFT   (0x00000000u)

+

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2   (0x0000FF00u)

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2_SHIFT   (0x00000008u)

+

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3   (0x00FF0000u)

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3_SHIFT   (0x00000010u)

+

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4   (0xFF000000u)

+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4_SHIFT   (0x00000018u)

+

+

+/* HW_EVENT_SEL_GRP2 */

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5   (0x000000FFu)

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5_SHIFT   (0x00000000u)

+

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6   (0x0000FF00u)

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6_SHIFT   (0x00000008u)

+

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7   (0x00FF0000u)

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7_SHIFT   (0x00000010u)

+

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8   (0xFF000000u)

+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8_SHIFT   (0x00000018u)

+

+

+/* HW_EVENT_SEL_GRP3 */

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10   (0x0000FF00u)

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10_SHIFT   (0x00000008u)

+

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11   (0x00FF0000u)

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11_SHIFT   (0x00000010u)

+

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12   (0xFF000000u)

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12_SHIFT   (0x00000018u)

+

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9   (0x000000FFu)

+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9_SHIFT   (0x00000000u)

+

+

+/* HW_EVENT_SEL_GRP4 */

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13   (0x000000FFu)

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13_SHIFT   (0x00000000u)

+

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14   (0x0000FF00u)

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14_SHIFT   (0x00000008u)

+

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15   (0x00FF0000u)

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15_SHIFT   (0x00000010u)

+

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16   (0xFF000000u)

+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16_SHIFT   (0x00000018u)

+

+

+/* SMRT_CTRL */

+#define CONTROL_SMRT_CTRL_SR0_SLEEP   (0x00000001u)

+#define CONTROL_SMRT_CTRL_SR0_SLEEP_SHIFT   (0x00000000u)

+

+#define CONTROL_SMRT_CTRL_SR1_SLEEP   (0x00000002u)

+#define CONTROL_SMRT_CTRL_SR1_SLEEP_SHIFT   (0x00000001u)

+

+

+/* SABTOOTH_HW_DEBUG_SEL */

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN   (0x00000200u)

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN_SHIFT   (0x00000009u)

+

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL   (0x0000000Fu)

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL_SHIFT   (0x00000000u)

+

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3   (0xFFFFFC00u)

+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3_SHIFT   (0x0000000Au)

+

+

+/* SABTOOTH_HW_DBG_INFO */

+#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO   (0xFFFFFFFFu)

+#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO_SHIFT   (0x00000000u)

+

+

+/* MRGN_MODE0 */

+#define CONTROL_MRGN_MODE0_MMODE0   (0x00000003u)

+#define CONTROL_MRGN_MODE0_MMODE0_SHIFT   (0x00000000u)

+

+#define CONTROL_MRGN_MODE0_MMODE1   (0x0000000Cu)

+#define CONTROL_MRGN_MODE0_MMODE1_SHIFT   (0x00000002u)

+

+#define CONTROL_MRGN_MODE0_MMODE10   (0x00300000u)

+#define CONTROL_MRGN_MODE0_MMODE10_SHIFT   (0x00000014u)

+

+#define CONTROL_MRGN_MODE0_MMODE11   (0x00C00000u)

+#define CONTROL_MRGN_MODE0_MMODE11_SHIFT   (0x00000016u)

+

+#define CONTROL_MRGN_MODE0_MMODE12   (0x03000000u)

+#define CONTROL_MRGN_MODE0_MMODE12_SHIFT   (0x00000018u)

+

+#define CONTROL_MRGN_MODE0_MMODE13   (0x0C000000u)

+#define CONTROL_MRGN_MODE0_MMODE13_SHIFT   (0x0000001Au)

+

+#define CONTROL_MRGN_MODE0_MMODE14   (0x30000000u)

+#define CONTROL_MRGN_MODE0_MMODE14_SHIFT   (0x0000001Cu)

+

+#define CONTROL_MRGN_MODE0_MMODE15   (0xC0000000u)

+#define CONTROL_MRGN_MODE0_MMODE15_SHIFT   (0x0000001Eu)

+

+#define CONTROL_MRGN_MODE0_MMODE2   (0x00000030u)

+#define CONTROL_MRGN_MODE0_MMODE2_SHIFT   (0x00000004u)

+

+#define CONTROL_MRGN_MODE0_MMODE3   (0x000000C0u)

+#define CONTROL_MRGN_MODE0_MMODE3_SHIFT   (0x00000006u)

+

+#define CONTROL_MRGN_MODE0_MMODE4   (0x00000300u)

+#define CONTROL_MRGN_MODE0_MMODE4_SHIFT   (0x00000008u)

+

+#define CONTROL_MRGN_MODE0_MMODE5   (0x00000C00u)

+#define CONTROL_MRGN_MODE0_MMODE5_SHIFT   (0x0000000Au)

+

+#define CONTROL_MRGN_MODE0_MMODE6   (0x00003000u)

+#define CONTROL_MRGN_MODE0_MMODE6_SHIFT   (0x0000000Cu)

+

+#define CONTROL_MRGN_MODE0_MMODE7   (0x0000C000u)

+#define CONTROL_MRGN_MODE0_MMODE7_SHIFT   (0x0000000Eu)

+

+#define CONTROL_MRGN_MODE0_MMODE8   (0x00030000u)

+#define CONTROL_MRGN_MODE0_MMODE8_SHIFT   (0x00000010u)

+

+#define CONTROL_MRGN_MODE0_MMODE9   (0x000C0000u)

+#define CONTROL_MRGN_MODE0_MMODE9_SHIFT   (0x00000012u)

+

+

+/* MRGN_MODE1 */

+#define CONTROL_MRGN_MODE1_MMODE16   (0x00000003u)

+#define CONTROL_MRGN_MODE1_MMODE16_SHIFT   (0x00000000u)

+

+#define CONTROL_MRGN_MODE1_MMODE17   (0x0000000Cu)

+#define CONTROL_MRGN_MODE1_MMODE17_SHIFT   (0x00000002u)

+

+#define CONTROL_MRGN_MODE1_MMODE18   (0x00000030u)

+#define CONTROL_MRGN_MODE1_MMODE18_SHIFT   (0x00000004u)

+

+#define CONTROL_MRGN_MODE1_MMODE19   (0x000000C0u)

+#define CONTROL_MRGN_MODE1_MMODE19_SHIFT   (0x00000006u)

+

+

+/* VDD_MPU_OPP_050 */

+#define CONTROL_VDD_MPU_OPP_050_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_MPU_OPP_050_NTARGET_SHIFT   (0x00000000u)

+

+

+/* VDD_MPU_OPP_100 */

+#define CONTROL_VDD_MPU_OPP_100_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_MPU_OPP_100_NTARGET_SHIFT   (0x00000000u)

+

+

+/* VDD_MPU_OPP_119 */

+#define CONTROL_VDD_MPU_OPP_119_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_MPU_OPP_119_NTARGET_SHIFT   (0x00000000u)

+

+

+/* VDD_MPU_OPP_TURBO */

+#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET_SHIFT   (0x00000000u)

+

+

+/* VDD_CORE_OPP_050 */

+#define CONTROL_VDD_CORE_OPP_050_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_CORE_OPP_050_NTARGET_SHIFT   (0x00000000u)

+

+

+/* VDD_CORE_OPP_100 */

+#define CONTROL_VDD_CORE_OPP_100_NTARGET   (0x00FFFFFFu)

+#define CONTROL_VDD_CORE_OPP_100_NTARGET_SHIFT   (0x00000000u)

+

+

+/* BB_SCALE */

+#define CONTROL_BB_SCALE_BBIAS   (0x00000003u)

+#define CONTROL_BB_SCALE_BBIAS_SHIFT   (0x00000000u)

+

+#define CONTROL_BB_SCALE_RSVD2   (0xFFFFF000u)

+#define CONTROL_BB_SCALE_RSVD2_SHIFT   (0x0000000Cu)

+

+#define CONTROL_BB_SCALE_SCALE   (0x00000F00u)

+#define CONTROL_BB_SCALE_SCALE_SHIFT   (0x00000008u)

+

+

+/* USB_VID_PID */

+#define CONTROL_USB_VID_PID_USB_PID   (0x0000FFFFu)

+#define CONTROL_USB_VID_PID_USB_PID_SHIFT   (0x00000000u)

+

+#define CONTROL_USB_VID_PID_USB_VID   (0xFFFF0000u)

+#define CONTROL_USB_VID_PID_USB_VID_SHIFT   (0x00000010u)

+

+

+/* EFUSE_SMA */

+#define CONTROL_EFUSE_SMA_EFUSE_SMA   (0xFFFFFFFFu)

+#define CONTROL_EFUSE_SMA_EFUSE_SMA_SHIFT   (0x00000000u)

+

+

+/* CONF_GPMC_ADx */

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD0 */

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD1 */

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD2 */

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD3 */

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD4 */

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD5 */

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD6 */

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD7 */

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD8 */

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD9 */

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD10 */

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD11 */

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD12 */

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD13 */

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD14 */

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_AD15 */

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A0 */

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A1 */

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A2 */

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A3 */

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A4 */

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A5 */

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A6 */

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A7 */

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A8 */

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A9 */

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A10 */

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_A11 */

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_WAIT0 */

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_WPN */

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_BE1N */

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_CSN0 */

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_CSN1 */

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_CSN2 */

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_CSN3 */

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_CLK */

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_ADVN_ALE */

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_OEN_REN */

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_WEN */

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_GPMC_BE0N_CLE */

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE   (0x00000007u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA0 */

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA1 */

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA2 */

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA3 */

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA4 */

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA5 */

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA6 */

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA7 */

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA8 */

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA9 */

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA10 */

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA11 */

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA12 */

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA13 */

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA14 */

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA15 */

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA16 */

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA17 */

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA18 */

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL_SHIFT   (0x00000006u)

+

+/* CONF_LCD_DATA19 */

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA20 */

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL_SHIFT   (0x00000006u)

+

+/* CONF_LCD_DATA21 */

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_DATA22 */

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL_SHIFT   (0x00000006u)

+

+/* CONF_LCD_DATA20 */

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+

+

+

+

+

+

+

+/* CONF_LCD_VSYNC */

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_HSYNC */

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_PCLK */

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_LCD_AC_BIAS_EN */

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE   (0x00000007u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_DAT3 */

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_DAT2 */

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_DAT1 */

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_DAT0 */

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_CLK */

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MMC0_CMD */

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE   (0x00000007u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_COL */

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_CRS */

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXERR */

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXEN */

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXDV */

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXD3 */

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXD2 */

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXD1 */

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXD0 */

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_TXCLK */

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXCLK */

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXD3 */

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXD2 */

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXD1 */

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MII1_RXD0 */

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE   (0x00000007u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_RMII1_REFCLK */

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MDIO_DATA */

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE   (0x00000007u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MDIO_CLK */

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_SPI0_SCLK */

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE   (0x00000007u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_SPI0_D0 */

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE   (0x00000007u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_SPI0_D1 */

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE   (0x00000007u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_SPI0_CS0 */

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE   (0x00000007u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_SPI0_CS1 */

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE   (0x00000007u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_ECAP0_IN_PWM0_OUT */

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE   (0x00000007u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART0_CTSN */

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART0_RTSN */

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART0_RXD */

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART0_TXD */

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART1_CTSN */

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART1_RTSN */

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART1_RXD */

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_UART1_TXD */

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE   (0x00000007u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_I2C0_SDA */

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE   (0x00000007u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN   (0x00000008u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_I2C0_SCL */

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE   (0x00000007u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN   (0x00000008u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_I2C0_SDA */

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE   (0x00000007u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN   (0x00000008u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_I2C0_SCL */

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE   (0x00000007u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN   (0x00000008u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+

+/* CONF_MCASP0_ACLKX */

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_FSX */

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_AXR0 */

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_AHCLKR */

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_ACLKR */

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_FSR */

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_AXR1 */

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_MCASP0_AHCLKX */

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE   (0x00000007u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN   (0x00000008u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_XDMA_EVENT_INTR0 */

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE   (0x00000007u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_XDMA_EVENT_INTR1 */

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE   (0x00000007u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_NRESETIN_OUT */

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE   (0x00000007u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_PORZ */

+#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE   (0x00000007u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN   (0x00000008u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_NNMI */

+#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE   (0x00000007u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN   (0x00000008u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC0_IN */

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC0_OUT */

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC0_VSS */

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_TMS */

+#define CONTROL_CONF_TMS_CONF_TMS_MMODE   (0x00000007u)

+#define CONTROL_CONF_TMS_CONF_TMS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_TMS_CONF_TMS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_TMS_CONF_TMS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_TMS_CONF_TMS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_TMS_CONF_TMS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_TDI */

+#define CONTROL_CONF_TDI_CONF_TDI_MMODE   (0x00000007u)

+#define CONTROL_CONF_TDI_CONF_TDI_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_TDI_CONF_TDI_PUDEN   (0x00000008u)

+#define CONTROL_CONF_TDI_CONF_TDI_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_TDI_CONF_TDI_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_TDI_CONF_TDI_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_TDO */

+#define CONTROL_CONF_TDO_CONF_TDO_MMODE   (0x00000007u)

+#define CONTROL_CONF_TDO_CONF_TDO_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_TDO_CONF_TDO_PUDEN   (0x00000008u)

+#define CONTROL_CONF_TDO_CONF_TDO_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_TDO_CONF_TDO_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_TDO_CONF_TDO_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_TCK */

+#define CONTROL_CONF_TCK_CONF_TCK_MMODE   (0x00000007u)

+#define CONTROL_CONF_TCK_CONF_TCK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_TCK_CONF_TCK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_TCK_CONF_TCK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_TCK_CONF_TCK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_TCK_CONF_TCK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_NTRST */

+#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE   (0x00000007u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN   (0x00000008u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_EMU0 */

+#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE   (0x00000007u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_EMU1 */

+#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE   (0x00000007u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC1_IN */

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC1_OUT */

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_OSC1_VSS */

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_MMODE   (0x00000007u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_OSC1_VSS_CONF_OSC1_VSS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_RTC_PORZ */

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_MMODE   (0x00000007u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUDEN   (0x00000008u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_RTC_PORZ_CONF_RTC_PORZ_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_PMIC_POWER_EN */

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_MMODE   (0x00000007u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_PMIC_POWER_EN_CONF_PMIC_POWER_EN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_EXT_WAKEUP */

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_MMODE   (0x00000007u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUDEN   (0x00000008u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_EXT_WAKEUP_CONF_EXT_WAKEUP_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_ENZ_KALDO_1P8V */

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_MMODE   (0x00000007u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUDEN   (0x00000008u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_ENZ_KALDO_1P8V_CONF_ENZ_KALDO_1P8V_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_DM */

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_DM_CONF_USB0_DM_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_DP */

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_DP_CONF_USB0_DP_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_CE */

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_CE_CONF_USB0_CE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_ID */

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_ID_CONF_USB0_ID_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_VBUS */

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_VBUS_CONF_USB0_VBUS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB0_DRVVBUS */

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB0_DRVVBUS_CONF_USB0_DRVVBUS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_DM */

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_DM_CONF_USB1_DM_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_DP */

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_DP_CONF_USB1_DP_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_CE */

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_CE_CONF_USB1_CE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_ID */

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_ID_CONF_USB1_ID_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_VBUS */

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_VBUS_CONF_USB1_VBUS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_USB1_DRVVBUS */

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_MMODE   (0x00000007u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_USB1_DRVVBUS_CONF_USB1_DRVVBUS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_RESETN */

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_RESETN_CONF_DDR_RESETN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_CSN0 */

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_CSN0_CONF_DDR_CSN0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_CKE */

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RSVD2   (0x000FFF80u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RSVD2_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_CKE_CONF_DDR_CK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_NCK */

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_NCK_CONF_DDR_NCK_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_CASN */

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_CASN_CONF_DDR_CASN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_RASN */

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_RASN_CONF_DDR_RASN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_WEN */

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_WEN_CONF_DDR_WEN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_BA0 */

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_BA0_CONF_DDR_BA0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_BA1 */

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_BA1_CONF_DDR_BA1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_BA2 */

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_BA2_CONF_DDR_BA2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A0 */

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A0_CONF_DDR_A0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A1 */

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A1_CONF_DDR_A1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A2 */

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A2_CONF_DDR_A2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A3 */

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A3_CONF_DDR_A3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A4 */

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A4_CONF_DDR_A4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A5 */

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A5_CONF_DDR_A5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A6 */

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A6_CONF_DDR_A6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A7 */

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A7_CONF_DDR_A7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A8 */

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A8_CONF_DDR_A8_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A9 */

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A9_CONF_DDR_A9_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A10 */

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A10_CONF_DDR_A10_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A11 */

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A11_CONF_DDR_A11_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A12 */

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A12_CONF_DDR_A12_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A13 */

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A13_CONF_DDR_A13_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A14 */

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A14_CONF_DDR_A14_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_A15 */

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_A15_CONF_DDR_A15_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_ODT */

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_ODT_CONF_DDR_ODT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D0 */

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D0_CONF_DDR_D0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D1 */

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D1_CONF_DDR_D1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D2 */

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D2_CONF_DDR_D2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D3 */

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D3_CONF_DDR_D3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D4 */

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D4_CONF_DDR_D4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D5 */

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D5_CONF_DDR_D5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D6 */

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D6_CONF_DDR_D6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D7 */

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D7_CONF_DDR_D7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D8 */

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D8_CONF_DDR_D8_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D9 */

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D9_CONF_DDR_D9_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D10 */

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D10_CONF_DDR_D10_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D11 */

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D11_CONF_DDR_D11_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D12 */

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D12_CONF_DDR_D12_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D13 */

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D13_CONF_DDR_D13_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D14 */

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D14_CONF_DDR_D14_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_D15 */

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_D15_CONF_DDR_D15_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQM0 */

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQM0_CONF_DDR_DQM0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQM1 */

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQM1_CONF_DDR_DQM1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQS0 */

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQS0_CONF_DDR_DQS0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQSN0 */

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQSN0_CONF_DDR_DQSN0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQS1 */

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQS1_CONF_DDR_DQS1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_DQSN1 */

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_DQSN1_CONF_DDR_DQSN1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_VREF */

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_VREF_CONF_DDR_VREF_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_VTP */

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_VTP_CONF_DDR_VTP_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_STRBEN0 */

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_STRBEN0_CONF_DDR_STRBEN0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_DDR_STRBEN1 */

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_MMODE   (0x00000007u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_DDR_STRBEN1_CONF_DDR_STRBEN1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN7 */

+#define CONTROL_CONF_AIN7_CONF_AIN7_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN7_CONF_AIN7_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN7_CONF_AIN7_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN7_CONF_AIN7_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN7_CONF_AIN7_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN7_CONF_AIN7_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN7_CONF_AIN7_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN6 */

+#define CONTROL_CONF_AIN6_CONF_AIN6_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN6_CONF_AIN6_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN6_CONF_AIN6_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN6_CONF_AIN6_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN6_CONF_AIN6_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN6_CONF_AIN6_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN6_CONF_AIN6_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN5 */

+#define CONTROL_CONF_AIN5_CONF_AIN5_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN5_CONF_AIN5_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN5_CONF_AIN5_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN5_CONF_AIN5_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN5_CONF_AIN5_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN5_CONF_AIN5_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN5_CONF_AIN5_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN4 */

+#define CONTROL_CONF_AIN4_CONF_AIN4_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN4_CONF_AIN4_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN4_CONF_AIN4_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN4_CONF_AIN4_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN4_CONF_AIN4_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN4_CONF_AIN4_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN4_CONF_AIN4_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN3 */

+#define CONTROL_CONF_AIN3_CONF_AIN3_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN3_CONF_AIN3_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN3_CONF_AIN3_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN3_CONF_AIN3_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN3_CONF_AIN3_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN3_CONF_AIN3_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN3_CONF_AIN3_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN2 */

+#define CONTROL_CONF_AIN2_CONF_AIN2_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN2_CONF_AIN2_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN2_CONF_AIN2_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN2_CONF_AIN2_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN2_CONF_AIN2_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN2_CONF_AIN2_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN2_CONF_AIN2_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN1 */

+#define CONTROL_CONF_AIN1_CONF_AIN1_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN1_CONF_AIN1_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN1_CONF_AIN1_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN1_CONF_AIN1_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN1_CONF_AIN1_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN1_CONF_AIN1_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN1_CONF_AIN1_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AIN0 */

+#define CONTROL_CONF_AIN0_CONF_AIN0_MMODE   (0x00000007u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AIN0_CONF_AIN0_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AIN0_CONF_AIN0_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AIN0_CONF_AIN0_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AIN0_CONF_AIN0_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AIN0_CONF_AIN0_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AIN0_CONF_AIN0_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_VREFP */

+#define CONTROL_CONF_VREFP_CONF_VREFP_MMODE   (0x00000007u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_VREFP_CONF_VREFP_PUDEN   (0x00000008u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_VREFP_CONF_VREFP_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_VREFP_CONF_VREFP_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_VREFP_CONF_VREFP_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_VREFP_CONF_VREFP_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_VREFP_CONF_VREFP_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_VREFN */

+#define CONTROL_CONF_VREFN_CONF_VREFN_MMODE   (0x00000007u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_VREFN_CONF_VREFN_PUDEN   (0x00000008u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_VREFN_CONF_VREFN_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_VREFN_CONF_VREFN_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_VREFN_CONF_VREFN_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_VREFN_CONF_VREFN_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_VREFN_CONF_VREFN_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AVDD */

+#define CONTROL_CONF_AVDD_CONF_AVDD_MMODE   (0x00000007u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AVDD_CONF_AVDD_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AVDD_CONF_AVDD_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AVDD_CONF_AVDD_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AVDD_CONF_AVDD_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AVDD_CONF_AVDD_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AVDD_CONF_AVDD_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_AVSS */

+#define CONTROL_CONF_AVSS_CONF_AVSS_MMODE   (0x00000007u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_AVSS_CONF_AVSS_PUDEN   (0x00000008u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_AVSS_CONF_AVSS_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_AVSS_CONF_AVSS_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_AVSS_CONF_AVSS_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_AVSS_CONF_AVSS_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_AVSS_CONF_AVSS_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_IFORCE */

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_MMODE   (0x00000007u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_IFORCE_CONF_IFORCE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_VSENSE */

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_MMODE   (0x00000007u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUDEN   (0x00000008u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_VSENSE_CONF_VSENSE_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CONF_TESTOUT */

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_MMODE   (0x00000007u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_MMODE_SHIFT   (0x00000000u)

+

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUDEN   (0x00000008u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUDEN_SHIFT   (0x00000003u)

+

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUTYPESEL   (0x00000010u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_PUTYPESEL_SHIFT   (0x00000004u)

+

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RSVD   (0x000FFF80u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RSVD_SHIFT   (0x00000007u)

+

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RXACTIVE   (0x00000020u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_RXACTIVE_SHIFT   (0x00000005u)

+

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_SLEWCTRL   (0x00000040u)

+#define CONTROL_CONF_TESTOUT_CONF_TESTOUT_SLEWCTRL_SHIFT   (0x00000006u)

+

+

+/* CQDETECT_STATUS */

+#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A   (0x00000800u)

+#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_A_SHIFT   (0x0000000Bu)

+

+#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B   (0x00001000u)

+#define CONTROL_CQDETECT_STATUS_CQERR_GEMAC_B_SHIFT   (0x0000000Cu)

+

+#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL   (0x00002000u)

+#define CONTROL_CQDETECT_STATUS_CQERR_GENERAL_SHIFT   (0x0000000Du)

+

+#define CONTROL_CQDETECT_STATUS_CQERR_GPMC   (0x00000100u)

+#define CONTROL_CQDETECT_STATUS_CQERR_GPMC_SHIFT   (0x00000008u)

+

+#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A   (0x00000200u)

+#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_A_SHIFT   (0x00000009u)

+

+#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B   (0x00000400u)

+#define CONTROL_CQDETECT_STATUS_CQERR_MMCSD_B_SHIFT   (0x0000000Au)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A   (0x00080000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_A_SHIFT   (0x00000013u)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B   (0x00100000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_GEMAC_B_SHIFT   (0x00000014u)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL   (0x00200000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_GENERAL_SHIFT   (0x00000015u)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC   (0x00010000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_GPMC_SHIFT   (0x00000010u)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A   (0x00020000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_A_SHIFT   (0x00000011u)

+

+#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B   (0x00040000u)

+#define CONTROL_CQDETECT_STATUS_CQMODE_MMCSD_B_SHIFT   (0x00000012u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A   (0x00000008u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_A_SHIFT   (0x00000003u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B   (0x00000010u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GEMAC_B_SHIFT   (0x00000004u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL   (0x00000020u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GENERAL_SHIFT   (0x00000005u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC   (0x00000001u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_GPMC_SHIFT   (0x00000000u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A   (0x00000002u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_A_SHIFT   (0x00000001u)

+

+#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B   (0x00000004u)

+#define CONTROL_CQDETECT_STATUS_CQSTAT_MMCSD_B_SHIFT   (0x00000002u)

+

+#define CONTROL_CQDETECT_STATUS_RSVD2   (0x0000C000u)

+#define CONTROL_CQDETECT_STATUS_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_CQDETECT_STATUS_RSVD3   (0xFFC00000u)

+#define CONTROL_CQDETECT_STATUS_RSVD3_SHIFT   (0x00000016u)

+

+

+/* DDR_IO_CTRL */

+#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL   (0x80000000u)

+#define CONTROL_DDR_IO_CTRL_DDR3_RST_DEF_VAL_SHIFT   (0x0000001Fu)

+

+#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE   (0x40000000u)

+#define CONTROL_DDR_IO_CTRL_DDR_WUCLK_DISABLE_SHIFT   (0x0000001Eu)

+

+#define CONTROL_DDR_IO_CTRL_MDDR_SEL   (0x10000000u)

+#define CONTROL_DDR_IO_CTRL_MDDR_SEL_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_IO_CTRL_RSVD2   (0x20000000u)

+#define CONTROL_DDR_IO_CTRL_RSVD2_SHIFT   (0x0000001Du)

+

+

+/* VTP_CTRL */

+#define CONTROL_VTP_CTRL_CLRZ   (0x00000001u)

+#define CONTROL_VTP_CTRL_CLRZ_SHIFT   (0x00000000u)

+

+#define CONTROL_VTP_CTRL_ENABLE   (0x00000040u)

+#define CONTROL_VTP_CTRL_ENABLE_SHIFT   (0x00000006u)

+

+#define CONTROL_VTP_CTRL_FILTER   (0x0000000Eu)

+#define CONTROL_VTP_CTRL_FILTER_SHIFT   (0x00000001u)

+

+#define CONTROL_VTP_CTRL_LOCK   (0x00000010u)

+#define CONTROL_VTP_CTRL_LOCK_SHIFT   (0x00000004u)

+

+#define CONTROL_VTP_CTRL_NCIN   (0x00007F00u)

+#define CONTROL_VTP_CTRL_NCIN_SHIFT   (0x00000008u)

+

+#define CONTROL_VTP_CTRL_PCIN   (0x007F0000u)

+#define CONTROL_VTP_CTRL_PCIN_SHIFT   (0x00000010u)

+

+#define CONTROL_VTP_CTRL_READY   (0x00000020u)

+#define CONTROL_VTP_CTRL_READY_SHIFT   (0x00000005u)

+

+#define CONTROL_VTP_CTRL_RSVD2   (0x00008000u)

+#define CONTROL_VTP_CTRL_RSVD2_SHIFT   (0x0000000Fu)

+

+#define CONTROL_VTP_CTRL_RSVD3   (0xFF800000u)

+#define CONTROL_VTP_CTRL_RSVD3_SHIFT   (0x00000017u)

+

+

+/* VREF_CTRL */

+#define CONTROL_VREF_CTRL_DDR_VREF_CCAP   (0x00000018u)

+#define CONTROL_VREF_CTRL_DDR_VREF_CCAP_SHIFT   (0x00000003u)

+

+#define CONTROL_VREF_CTRL_DDR_VREF_EN   (0x00000001u)

+#define CONTROL_VREF_CTRL_DDR_VREF_EN_SHIFT   (0x00000000u)

+

+#define CONTROL_VREF_CTRL_DDR_VREF_TAP   (0x00000006u)

+#define CONTROL_VREF_CTRL_DDR_VREF_TAP_SHIFT   (0x00000001u)

+

+

+/* SERDES_REFCLK_CTL */

+#define CONTROL_SERDES_REFCLK_CTL_PWRDN   (0x00000001u)

+#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SHIFT   (0x00000000u)

+

+#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE   (0x00000002u)

+#define CONTROL_SERDES_REFCLK_CTL_PWRDN_SE_SHIFT   (0x00000001u)

+

+

+/* TPCC_EVT_MUX_0_3 */

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_0   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_0_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_1   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_1_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_2   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_2_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_3   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_0_3_EVT_MUX_3_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_0_3_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_4_7 */

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_4   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_4_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_5   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_5_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_6   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_6_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_7   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_4_7_EVT_MUX_7_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_4_7_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_8_11 */

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_10   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_10_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_11   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_11_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_8   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_8_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_9   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_8_11_EVT_MUX_9_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_8_11_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_12_15 */

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_12   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_12_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_13   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_13_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_14   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_14_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_15   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_12_15_EVT_MUX_15_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_12_15_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_16_19 */

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_16   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_16_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_17   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_17_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_18   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_18_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_19   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_16_19_EVT_MUX_19_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_16_19_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_20_23 */

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_20   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_20_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_21   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_21_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_22   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_22_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_23   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_20_23_EVT_MUX_23_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_20_23_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_24_27 */

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_24   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_24_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_25   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_25_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_26   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_26_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_27   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_24_27_EVT_MUX_27_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_24_27_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_28_31 */

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_28   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_28_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_29   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_29_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_30   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_30_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_31   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_28_31_EVT_MUX_31_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_28_31_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_32_35 */

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_32   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_32_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_33   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_33_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_34   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_34_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_35   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_32_35_EVT_MUX_35_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_32_35_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_36_39 */

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_36   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_36_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_37   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_37_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_38   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_38_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_39   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_36_39_EVT_MUX_39_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_36_39_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_40_43 */

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_40   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_40_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_41   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_41_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_42   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_42_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_43   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_40_43_EVT_MUX_43_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_40_43_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_44_47 */

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_44   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_44_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_45   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_45_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_46   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_46_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_47   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_44_47_EVT_MUX_47_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_44_47_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_48_51 */

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_48   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_48_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_49   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_49_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_50   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_50_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_51   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_48_51_EVT_MUX_51_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_48_51_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_52_55 */

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_52   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_52_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_53   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_53_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_54   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_54_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_55   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_52_55_EVT_MUX_55_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_52_55_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_56_59 */

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_56   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_56_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_57   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_57_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_58   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_58_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_59   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_56_59_EVT_MUX_59_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_56_59_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TPCC_EVT_MUX_60_63 */

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_60   (0x3F000000u)

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_60_SHIFT   (0x00000018u)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_61   (0x003F0000u)

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_61_SHIFT   (0x00000010u)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_62   (0x00003F00u)

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_62_SHIFT   (0x00000008u)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_63   (0x0000003Fu)

+#define CONTROL_TPCC_EVT_MUX_60_63_EVT_MUX_63_SHIFT   (0x00000000u)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD2   (0x0000C000u)

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD2_SHIFT   (0x0000000Eu)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD3   (0x00C00000u)

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD3_SHIFT   (0x00000016u)

+

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD4   (0xC0000000u)

+#define CONTROL_TPCC_EVT_MUX_60_63_RSVD4_SHIFT   (0x0000001Eu)

+

+

+/* TIMER_EVT_CAPT */

+#define CONTROL_TIMER_EVT_CAPT_RSVD2   (0x0000E000u)

+#define CONTROL_TIMER_EVT_CAPT_RSVD2_SHIFT   (0x0000000Du)

+

+#define CONTROL_TIMER_EVT_CAPT_RSVD3   (0xFFE00000u)

+#define CONTROL_TIMER_EVT_CAPT_RSVD3_SHIFT   (0x00000015u)

+

+#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT   (0x0000001Fu)

+#define CONTROL_TIMER_EVT_CAPT_TIMER5_EVTCAPT_SHIFT   (0x00000000u)

+

+#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT   (0x00001F00u)

+#define CONTROL_TIMER_EVT_CAPT_TIMER6_EVTCAPT_SHIFT   (0x00000008u)

+

+#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT   (0x001F0000u)

+#define CONTROL_TIMER_EVT_CAPT_TIMER7_EVTCAPT_SHIFT   (0x00000010u)

+

+

+/* ECAP_EVT_CAPT */

+#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT   (0x0000001Fu)

+#define CONTROL_ECAP_EVT_CAPT_ECAP0_EVTCAPT_SHIFT   (0x00000000u)

+

+#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT   (0x00001F00u)

+#define CONTROL_ECAP_EVT_CAPT_ECAP1_EVTCAPT_SHIFT   (0x00000008u)

+

+#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT   (0x001F0000u)

+#define CONTROL_ECAP_EVT_CAPT_ECAP2_EVTCAPT_SHIFT   (0x00000010u)

+

+#define CONTROL_ECAP_EVT_CAPT_RSVD2   (0x0000E000u)

+#define CONTROL_ECAP_EVT_CAPT_RSVD2_SHIFT   (0x0000000Du)

+

+#define CONTROL_ECAP_EVT_CAPT_RSVD3   (0xFFE00000u)

+#define CONTROL_ECAP_EVT_CAPT_RSVD3_SHIFT   (0x00000015u)

+

+

+/* ADC_EVT_CAPT */

+#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT   (0x0000000Fu)

+#define CONTROL_ADC_EVT_CAPT_ADC_EVTCAPT_SHIFT   (0x00000000u)

+

+

+/* RESET_ISO */

+#define CONTROL_RESET_ISO_ISO_CONTROL   (0x00000001u)

+#define CONTROL_RESET_ISO_ISO_CONTROL_SHIFT   (0x00000000u)

+

+

+/* SMA0 */

+#define CONTROL_SMA0_SMA0   (0xFFFFFFFFu)

+#define CONTROL_SMA0_SMA0_SHIFT   (0x00000000u)

+

+

+/* DDR_CKE_CTRL */

+#define CONTROL_DDR_CKE_CTRL_DDR_CKE_CTRL   (0x00000001u)

+#define CONTROL_DDR_CKE_CTRL_DDR_CKE_CTRL_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_CKE_CTRL_SMA1   (0xFFFFFFFEu)

+#define CONTROL_DDR_CKE_CTRL_SMA1_SHIFT   (0x00000001u)

+

+

+/* SMA2 */

+#define CONTROL_SMA2_SMA2   (0xFFFFFFFFu)

+#define CONTROL_SMA2_SMA2_SHIFT   (0x00000000u)

+

+

+/* M3_TXEV_EOI */

+#define CONTROL_M3_TXEV_EOI_M3_TXEV_EOI   (0x00000001u)

+#define CONTROL_M3_TXEV_EOI_M3_TXEV_EOI_SHIFT   (0x00000000u)

+

+#define CONTROL_M3_TXEV_EOI_SMA3   (0xFFFFFFFEu)

+#define CONTROL_M3_TXEV_EOI_SMA3_SHIFT   (0x00000001u)

+

+

+/* IPC_MSG_REG0 */

+#define CONTROL_IPC_MSG_REG0_IPC_MSG_REG0   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG0_IPC_MSG_REG0_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG1 */

+#define CONTROL_IPC_MSG_REG1_IPC_MSG_REG1   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG1_IPC_MSG_REG1_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG2 */

+#define CONTROL_IPC_MSG_REG2_IPC_MSG_REG2   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG2_IPC_MSG_REG2_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG3 */

+#define CONTROL_IPC_MSG_REG3_IPC_MSG_REG3   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG3_IPC_MSG_REG3_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG4 */

+#define CONTROL_IPC_MSG_REG4_IPC_MSG_REG4   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG4_IPC_MSG_REG4_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG5 */

+#define CONTROL_IPC_MSG_REG5_IPC_MSG_REG5   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG5_IPC_MSG_REG5_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG6 */

+#define CONTROL_IPC_MSG_REG6_IPC_MSG_REG6   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG6_IPC_MSG_REG6_SHIFT   (0x00000000u)

+

+

+/* IPC_MSG_REG7 */

+#define CONTROL_IPC_MSG_REG7_IPC_MSG_REG7   (0xFFFFFFFFu)

+#define CONTROL_IPC_MSG_REG7_IPC_MSG_REG7_SHIFT   (0x00000000u)

+

+

+/* DDR_CMD0_IOCTRL */

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD0   (0x001FFC00u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD0_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD1   (0xFFE00000u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_GP_WD1_SHIFT   (0x00000015u)

+

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_CMD0_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+

+/* DDR_CMD1_IOCTRL */

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD0   (0x001FFC00u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD0_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD1   (0xFFE00000u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_GP_WD1_SHIFT   (0x00000015u)

+

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_CMD1_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+

+/* DDR_CMD2_IOCTRL */

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD0   (0x001FFC00u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD0_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD1   (0xFFE00000u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_GP_WD1_SHIFT   (0x00000015u)

+

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_CMD2_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+

+/* DDR_DATA0_IOCTRL */

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DM   (0x00040000u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DM_SHIFT   (0x00000012u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQ   (0x0003FC00u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQS   (0x00080000u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT   (0x00000013u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DM   (0x10000000u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DM_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQ   (0x0FF00000u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT   (0x00000014u)

+

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQS   (0x20000000u)

+#define CONTROL_DDR_DATA0_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT   (0x0000001Du)

+

+

+/* DDR_DATA1_IOCTRL */

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DM   (0x00040000u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DM_SHIFT   (0x00000012u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQ   (0x0003FC00u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQS   (0x00080000u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT   (0x00000013u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DM   (0x10000000u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DM_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQ   (0x0FF00000u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT   (0x00000014u)

+

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQS   (0x20000000u)

+#define CONTROL_DDR_DATA1_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT   (0x0000001Du)

+

+

+/* DDR_DATA2_IOCTRL */

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DM   (0x00040000u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DM_SHIFT   (0x00000012u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQ   (0x0003FC00u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQS   (0x00080000u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT   (0x00000013u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DM   (0x10000000u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DM_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQ   (0x0FF00000u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT   (0x00000014u)

+

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQS   (0x20000000u)

+#define CONTROL_DDR_DATA2_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT   (0x0000001Du)

+

+

+/* DDR_DATA3_IOCTRL */

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DM   (0x00040000u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DM_SHIFT   (0x00000012u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQ   (0x0003FC00u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQS   (0x00080000u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT   (0x00000013u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DM   (0x10000000u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DM_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQ   (0x0FF00000u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT   (0x00000014u)

+

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQS   (0x20000000u)

+#define CONTROL_DDR_DATA3_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT   (0x0000001Du)

+

+

+/* DDR_DATA4_IOCTRL */

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I   (0x00000007u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_SHIFT   (0x00000000u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_CLK   (0x000000E0u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_I_CLK_SHIFT   (0x00000005u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR   (0x00000018u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_SHIFT   (0x00000003u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_CLK   (0x00000300u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_SR_CLK_SHIFT   (0x00000008u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DM   (0x00040000u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DM_SHIFT   (0x00000012u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQ   (0x0003FC00u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQ_SHIFT   (0x0000000Au)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQS   (0x00080000u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD0_DQS_SHIFT   (0x00000013u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DM   (0x10000000u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DM_SHIFT   (0x0000001Cu)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQ   (0x0FF00000u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQ_SHIFT   (0x00000014u)

+

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQS   (0x20000000u)

+#define CONTROL_DDR_DATA4_IOCTRL_IO_CONFIG_WD1_DQS_SHIFT   (0x0000001Du)

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/cpsw/src/include/hw_cpsw_ale.h b/cpsw/src/include/hw_cpsw_ale.h
new file mode 100755
index 0000000..7ffaf03
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_ale.h
@@ -0,0 +1,304 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_ale_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CPSW_ALE_H_
+#define _HW_CPSW_ALE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_ALE_IDVER   (0x0)
+#define CPSW_ALE_CONTROL   (0x8)
+#define CPSW_ALE_PRESCALE   (0x10)
+#define CPSW_ALE_UNKNOWN_VLAN   (0x18)
+#define CPSW_ALE_TBLCTL   (0x20)
+#define CPSW_ALE_TBLW(n)   (0x34 + ((2- (n)) * 4))
+#define CPSW_ALE_PORTCTL(n)   (0x40 + (n * 4))
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* ALE_IDVER */
+#define CPSW_ALE_IDVER_ALE_IDENT   (0xFFFF0000u)
+#define CPSW_ALE_IDVER_ALE_IDENT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_IDVER_ALE_MAJ_VER   (0x0000FF00u)
+#define CPSW_ALE_IDVER_ALE_MAJ_VER_SHIFT   (0x00000008u)
+
+#define CPSW_ALE_IDVER_ALE_MINOR_VER   (0x000000FFu)
+#define CPSW_ALE_IDVER_ALE_MINOR_VER_SHIFT   (0x00000000u)
+
+
+/* ALE_CONTROL */
+#define CPSW_ALE_CONTROL_AGE_OUT_NOW   (0x20000000u)
+#define CPSW_ALE_CONTROL_AGE_OUT_NOW_SHIFT   (0x0000001Du)
+
+#define CPSW_ALE_CONTROL_ALE_BYPASS   (0x00000010u)
+#define CPSW_ALE_CONTROL_ALE_BYPASS_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_CONTROL_ALE_VLAN_AWARE   (0x00000004u)
+#define CPSW_ALE_CONTROL_ALE_VLAN_AWARE_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_CONTROL_CLEAR_TABLE   (0x40000000u)
+#define CPSW_ALE_CONTROL_CLEAR_TABLE_SHIFT   (0x0000001Eu)
+
+#define CPSW_ALE_CONTROL_ENABLE_ALE   (0x80000000u)
+#define CPSW_ALE_CONTROL_ENABLE_ALE_SHIFT   (0x0000001Fu)
+
+#define CPSW_ALE_CONTROL_ENABLE_AUTH_MODE   (0x00000002u)
+#define CPSW_ALE_CONTROL_ENABLE_AUTH_MODE_SHIFT   (0x00000001u)
+
+#define CPSW_ALE_CONTROL_ENABLE_OUI_DENY   (0x00000020u)
+#define CPSW_ALE_CONTROL_ENABLE_OUI_DENY_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_CONTROL_ENABLE_RATE_LIMIT   (0x00000001u)
+#define CPSW_ALE_CONTROL_ENABLE_RATE_LIMIT_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_CONTROL_EN_P0_UNI_FLOOD   (0x00000100u)
+#define CPSW_ALE_CONTROL_EN_P0_UNI_FLOOD_SHIFT   (0x00000008u)
+
+#define CPSW_ALE_CONTROL_EN_VID0_MODE   (0x00000040u)
+#define CPSW_ALE_CONTROL_EN_VID0_MODE_SHIFT   (0x00000006u)
+
+#define CPSW_ALE_CONTROL_LEARN_NO_VID   (0x00000080u)
+#define CPSW_ALE_CONTROL_LEARN_NO_VID_SHIFT   (0x00000007u)
+
+#define CPSW_ALE_CONTROL_RATE_LIMIT_TX   (0x00000008u)
+#define CPSW_ALE_CONTROL_RATE_LIMIT_TX_SHIFT   (0x00000003u)
+
+
+/* ALE_PRESCALE */
+#define CPSW_ALE_PRESCALE_ALE_PRESCALE   (0x000FFFFFu)
+#define CPSW_ALE_PRESCALE_ALE_PRESCALE_SHIFT   (0x00000000u)
+
+
+/* ALE_UNKNOWN_VLAN */
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_FORCE_UNTA   (0x3F000000u)
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_FORCE_UNTA_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_MCAST_FLO   (0x00003F00u)
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_MCAST_FLO_SHIFT   (0x00000008u)
+
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_REG_MCAST   (0x003F0000u)
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_REG_MCAST_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_VLAN_MEM   (0x0000003Fu)
+#define CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_VLAN_MEM_SHIFT   (0x00000000u)
+
+
+/* ALE_TBLCTL */
+#define CPSW_ALE_TBLCTL_ENTRY_POINTER   (0x000003FFu)
+#define CPSW_ALE_TBLCTL_ENTRY_POINTER_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_TBLCTL_WRITE_RDZ   (0x80000000u)
+#define CPSW_ALE_TBLCTL_WRITE_RDZ_SHIFT   (0x0000001Fu)
+
+
+/* ALE_PORTCTL0 */
+#define CPSW_ALE_PORTCTL0_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL0_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL0_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL0_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL0_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL0_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL0_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL0_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL0_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL0_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL0_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL0_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL0_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL0_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+/* ALE_PORTCTL1 */
+#define CPSW_ALE_PORTCTL1_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL1_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL1_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL1_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL1_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL1_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL1_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL1_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL1_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL1_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL1_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL1_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL1_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL1_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+/* ALE_PORTCTL2 */
+#define CPSW_ALE_PORTCTL2_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL2_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL2_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL2_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL2_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL2_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL2_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL2_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL2_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL2_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL2_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL2_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL2_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL2_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+/* ALE_PORTCTL3 */
+#define CPSW_ALE_PORTCTL3_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL3_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL3_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL3_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL3_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL3_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL3_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL3_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL3_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL3_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL3_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL3_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL3_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL3_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+/* ALE_PORTCTL4 */
+#define CPSW_ALE_PORTCTL4_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL4_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL4_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL4_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL4_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL4_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL4_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL4_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL4_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL4_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL4_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL4_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL4_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL4_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+/* ALE_PORTCTL5 */
+#define CPSW_ALE_PORTCTL5_BCAST_LIMIT   (0xFF000000u)
+#define CPSW_ALE_PORTCTL5_BCAST_LIMIT_SHIFT   (0x00000018u)
+
+#define CPSW_ALE_PORTCTL5_DROP_UNTAGGED   (0x00000004u)
+#define CPSW_ALE_PORTCTL5_DROP_UNTAGGED_SHIFT   (0x00000002u)
+
+#define CPSW_ALE_PORTCTL5_MCAST_LIMIT   (0x00FF0000u)
+#define CPSW_ALE_PORTCTL5_MCAST_LIMIT_SHIFT   (0x00000010u)
+
+#define CPSW_ALE_PORTCTL5_NO_LEARN   (0x00000010u)
+#define CPSW_ALE_PORTCTL5_NO_LEARN_SHIFT   (0x00000004u)
+
+#define CPSW_ALE_PORTCTL5_NO_SA_UPDATE   (0x00000020u)
+#define CPSW_ALE_PORTCTL5_NO_SA_UPDATE_SHIFT   (0x00000005u)
+
+#define CPSW_ALE_PORTCTL5_PORT_STATE   (0x00000003u)
+#define CPSW_ALE_PORTCTL5_PORT_STATE_SHIFT   (0x00000000u)
+
+#define CPSW_ALE_PORTCTL5_VID_INGRESS_CHECK   (0x00000008u)
+#define CPSW_ALE_PORTCTL5_VID_INGRESS_CHECK_SHIFT   (0x00000003u)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_cpsw_cpdma.h b/cpsw/src/include/hw_cpsw_cpdma.h
new file mode 100755
index 0000000..94ddb0d
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_cpdma.h
@@ -0,0 +1,1038 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_CPDMA_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CPSW_CPDMA_H_
+#define _HW_CPSW_CPDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_CPDMA_TX_IDVER   (0x0)
+#define CPSW_CPDMA_TX_CONTROL   (0x4)
+#define CPSW_CPDMA_TX_TEARDOWN   (0x8)
+#define CPSW_CPDMA_RX_IDVER   (0x10)
+#define CPSW_CPDMA_RX_CONTROL   (0x14)
+#define CPSW_CPDMA_RX_TEARDOWN   (0x18)
+#define CPSW_CPDMA_CPDMA_SOFT_RESET   (0x1c)
+#define CPSW_CPDMA_DMACONTROL   (0x20)
+#define CPSW_CPDMA_DMASTATUS   (0x24)
+#define CPSW_CPDMA_RX_BUFFER_OFFSET   (0x28)
+#define CPSW_CPDMA_EMCONTROL   (0x2c)
+#define CPSW_CPDMA_TX_PRI_RATE(n)   (0x30 + (n * 4))
+#define CPSW_CPDMA_TX_INTSTAT_RAW   (0x80)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED   (0x84)
+#define CPSW_CPDMA_TX_INTMASK_SET   (0x88)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR   (0x8c)
+#define CPSW_CPDMA_CPDMA_IN_VECTOR   (0x90)
+#define CPSW_CPDMA_CPDMA_EOI_VECTOR   (0x94)
+#define CPSW_CPDMA_RX_INTSTAT_RAW   (0xa0)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED   (0xa4)
+#define CPSW_CPDMA_RX_INTMASK_SET   (0xa8)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR   (0xac)
+#define CPSW_CPDMA_DMA_INTSTAT_RAW   (0xb0)
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED   (0xb4)
+#define CPSW_CPDMA_DMA_INTMASK_SET   (0xb8)
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR   (0xbc)
+#define CPSW_CPDMA_RX_PENDTHRESH(n)   (0xc0 + (n * 4))
+#define CPSW_CPDMA_RX_FREEBUFFER(n)   (0xe0 + (n * 4))
+#define CPSW_CPDMA_TX_HDP(n)   (0x200 + (n * 4))
+#define CPSW_CPDMA_RX_HDP(n)   (0x220 + (n * 4))
+#define CPSW_CPDMA_TX_CP(n)   (0x240 + (n * 4))
+#define CPSW_CPDMA_RX_CP(n)   (0x260 + (n * 4))
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* TX_IDVER */
+#define CPSW_CPDMA_TX_IDVER_TX_IDENT   (0xFFFF0000u)
+#define CPSW_CPDMA_TX_IDVER_TX_IDENT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_IDVER_TX_MAJOR_VER   (0x0000FF00u)
+#define CPSW_CPDMA_TX_IDVER_TX_MAJOR_VER_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_TX_IDVER_TX_MINOR_VER   (0x000000FFu)
+#define CPSW_CPDMA_TX_IDVER_TX_MINOR_VER_SHIFT   (0x00000000u)
+
+
+/* TX_CONTROL */
+#define CPSW_CPDMA_TX_CONTROL_TX_EN   (0x00000001u)
+#define CPSW_CPDMA_TX_CONTROL_TX_EN_SHIFT   (0x00000000u)
+
+
+/* TX_TEARDOWN */
+#define CPSW_CPDMA_TX_TEARDOWN_TX_TDN_CH   (0x00000007u)
+#define CPSW_CPDMA_TX_TEARDOWN_TX_TDN_CH_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_TX_TEARDOWN_TX_TDN_RDY   (0x80000000u)
+#define CPSW_CPDMA_TX_TEARDOWN_TX_TDN_RDY_SHIFT   (0x0000001Fu)
+
+
+/* RX_IDVER */
+#define CPSW_CPDMA_RX_IDVER_RX_IDENT   (0xFFFF0000u)
+#define CPSW_CPDMA_RX_IDVER_RX_IDENT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_RX_IDVER_RX_MAJOR_VER   (0x0000FF00u)
+#define CPSW_CPDMA_RX_IDVER_RX_MAJOR_VER_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_RX_IDVER_RX_MINOR_VER   (0x000000FFu)
+#define CPSW_CPDMA_RX_IDVER_RX_MINOR_VER_SHIFT   (0x00000000u)
+
+
+/* RX_CONTROL */
+#define CPSW_CPDMA_RX_CONTROL_RX_EN   (0x00000001u)
+#define CPSW_CPDMA_RX_CONTROL_RX_EN_SHIFT   (0x00000000u)
+
+
+/* RX_TEARDOWN */
+#define CPSW_CPDMA_RX_TEARDOWN_RX_TDN_CH   (0x00000007u)
+#define CPSW_CPDMA_RX_TEARDOWN_RX_TDN_CH_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_RX_TEARDOWN_RX_TDN_RDY   (0x80000000u)
+#define CPSW_CPDMA_RX_TEARDOWN_RX_TDN_RDY_SHIFT   (0x0000001Fu)
+
+
+/* CPDMA_SOFT_RESET */
+#define CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET   (0x00000001u)
+#define CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET_SHIFT   (0x00000000u)
+
+
+/* DMACONTROL */
+#define CPSW_CPDMA_DMACONTROL_CMD_IDLE   (0x00000008u)
+#define CPSW_CPDMA_DMACONTROL_CMD_IDLE_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_DMACONTROL_RX_CEF   (0x00000010u)
+#define CPSW_CPDMA_DMACONTROL_RX_CEF_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_DMACONTROL_RX_OFFLEN_BLOCK   (0x00000004u)
+#define CPSW_CPDMA_DMACONTROL_RX_OFFLEN_BLOCK_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_DMACONTROL_RX_OWNERSHIP   (0x00000002u)
+#define CPSW_CPDMA_DMACONTROL_RX_OWNERSHIP_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_DMACONTROL_TX_PTYPE   (0x00000001u)
+#define CPSW_CPDMA_DMACONTROL_TX_PTYPE_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_DMACONTROL_TX_RLIM   (0x0000FF00u)
+#define CPSW_CPDMA_DMACONTROL_TX_RLIM_SHIFT   (0x00000008u)
+
+
+/* DMASTATUS */
+#define CPSW_CPDMA_DMASTATUS_IDLE   (0x80000000u)
+#define CPSW_CPDMA_DMASTATUS_IDLE_SHIFT   (0x0000001Fu)
+
+#define CPSW_CPDMA_DMASTATUS_RX_ERR_CH   (0x00000700u)
+#define CPSW_CPDMA_DMASTATUS_RX_ERR_CH_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE   (0x0000F000u)
+#define CPSW_CPDMA_DMASTATUS_RX_HOST_ERR_CODE_SHIFT   (0x0000000Cu)
+
+#define CPSW_CPDMA_DMASTATUS_TX_ERR_CH   (0x00070000u)
+#define CPSW_CPDMA_DMASTATUS_TX_ERR_CH_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE   (0x00F00000u)
+#define CPSW_CPDMA_DMASTATUS_TX_HOST_ERR_CODE_SHIFT   (0x00000014u)
+
+
+/* RX_BUFFER_OFFSET */
+#define CPSW_CPDMA_RX_BUFFER_OFFSET_RX_BUFFER_OFFSET   (0x0000FFFFu)
+#define CPSW_CPDMA_RX_BUFFER_OFFSET_RX_BUFFER_OFFSET_SHIFT   (0x00000000u)
+
+
+/* EMCONTROL */
+#define CPSW_CPDMA_EMCONTROL_FREE   (0x00000001u)
+#define CPSW_CPDMA_EMCONTROL_FREE_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_EMCONTROL_SOFT   (0x00000002u)
+#define CPSW_CPDMA_EMCONTROL_SOFT_SHIFT   (0x00000001u)
+
+
+/* TX_PRI0_RATE */
+#define CPSW_CPDMA_TX_PRI0_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI0_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI0_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI0_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI1_RATE */
+#define CPSW_CPDMA_TX_PRI1_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI1_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI1_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI1_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI2_RATE */
+#define CPSW_CPDMA_TX_PRI2_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI2_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI2_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI2_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI3_RATE */
+#define CPSW_CPDMA_TX_PRI3_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI3_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI3_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI3_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI4_RATE */
+#define CPSW_CPDMA_TX_PRI4_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI4_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI4_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI4_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI5_RATE */
+#define CPSW_CPDMA_TX_PRI5_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI5_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI5_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI5_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI6_RATE */
+#define CPSW_CPDMA_TX_PRI6_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI6_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI6_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI6_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_PRI7_RATE */
+#define CPSW_CPDMA_TX_PRI7_RATE_PRIN_IDLE_CNT   (0x3FFF0000u)
+#define CPSW_CPDMA_TX_PRI7_RATE_PRIN_IDLE_CNT_SHIFT   (0x00000010u)
+
+#define CPSW_CPDMA_TX_PRI7_RATE_PRIN_SEND_CNT   (0x00003FFFu)
+#define CPSW_CPDMA_TX_PRI7_RATE_PRIN_SEND_CNT_SHIFT   (0x00000000u)
+
+
+/* TX_INTSTAT_RAW */
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX0_PEND   (0x00000001u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX0_PEND_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX1_PEND   (0x00000002u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX1_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX2_PEND   (0x00000004u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX2_PEND_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX3_PEND   (0x00000008u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX3_PEND_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX4_PEND   (0x00000010u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX4_PEND_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX5_PEND   (0x00000020u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX5_PEND_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX6_PEND   (0x00000040u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX6_PEND_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX7_PEND   (0x00000080u)
+#define CPSW_CPDMA_TX_INTSTAT_RAW_TX7_PEND_SHIFT   (0x00000007u)
+
+
+/* TX_INTSTAT_MASKED */
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX0_PEND   (0x00000001u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX0_PEND_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX1_PEND   (0x00000002u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX1_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX2_PEND   (0x00000004u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX2_PEND_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX3_PEND   (0x00000008u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX3_PEND_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX4_PEND   (0x00000010u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX4_PEND_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX5_PEND   (0x00000020u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX5_PEND_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX6_PEND   (0x00000040u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX6_PEND_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX7_PEND   (0x00000080u)
+#define CPSW_CPDMA_TX_INTSTAT_MASKED_TX7_PEND_SHIFT   (0x00000007u)
+
+
+/* TX_INTMASK_SET */
+#define CPSW_CPDMA_TX_INTMASK_SET_TX0_MASK   (0x00000001u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX0_MASK_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX1_MASK   (0x00000002u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX1_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX2_MASK   (0x00000004u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX2_MASK_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX3_MASK   (0x00000008u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX3_MASK_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX4_MASK   (0x00000010u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX4_MASK_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX5_MASK   (0x00000020u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX5_MASK_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX6_MASK   (0x00000040u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX6_MASK_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_TX_INTMASK_SET_TX7_MASK   (0x00000080u)
+#define CPSW_CPDMA_TX_INTMASK_SET_TX7_MASK_SHIFT   (0x00000007u)
+
+
+/* TX_INTMASK_CLEAR */
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX0_MASK   (0x00000001u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX0_MASK_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX1_MASK   (0x00000002u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX1_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX2_MASK   (0x00000004u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX2_MASK_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX3_MASK   (0x00000008u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX3_MASK_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX4_MASK   (0x00000010u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX4_MASK_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX5_MASK   (0x00000020u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX5_MASK_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX6_MASK   (0x00000040u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX6_MASK_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX7_MASK   (0x00000080u)
+#define CPSW_CPDMA_TX_INTMASK_CLEAR_TX7_MASK_SHIFT   (0x00000007u)
+
+
+/* CPDMA_IN_VECTOR */
+#define CPSW_CPDMA_CPDMA_IN_VECTOR_DMA_IN_VECTOR   (0xFFFFFFFFu)
+#define CPSW_CPDMA_CPDMA_IN_VECTOR_DMA_IN_VECTOR_SHIFT   (0x00000000u)
+
+
+/* CPDMA_EOI_VECTOR */
+#define CPSW_CPDMA_CPDMA_EOI_VECTOR_DMA_EOI_VECTOR   (0x0000001Fu)
+#define CPSW_CPDMA_CPDMA_EOI_VECTOR_DMA_EOI_VECTOR_SHIFT   (0x00000000u)
+
+
+/* RX_INTSTAT_RAW */
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX0_PEND   (0x00000001u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX0_PEND_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX0_THRESH_PEND   (0x00000100u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX0_THRESH_PEND_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX1_PEND   (0x00000002u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX1_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX1_THRESH_PEND   (0x00000200u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX1_THRESH_PEND_SHIFT   (0x00000009u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX2_PEND   (0x00000004u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX2_PEND_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX2_THRESH_PEND   (0x00000400u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX2_THRESH_PEND_SHIFT   (0x0000000Au)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX3_PEND   (0x00000008u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX3_PEND_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX3_THRESH_PEND   (0x00000800u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX3_THRESH_PEND_SHIFT   (0x0000000Bu)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX4_PEND   (0x00000010u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX4_PEND_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX4_THRESH_PEND   (0x00001000u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX4_THRESH_PEND_SHIFT   (0x0000000Cu)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX5_PEND   (0x00000020u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX5_PEND_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX5_THRESH_PEND   (0x00002000u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX5_THRESH_PEND_SHIFT   (0x0000000Du)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX6_PEND   (0x00000040u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX6_PEND_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX6_THRESH_PEND   (0x00004000u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX6_THRESH_PEND_SHIFT   (0x0000000Eu)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX7_PEND   (0x00000080u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX7_PEND_SHIFT   (0x00000007u)
+
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX7_THRESH_PEND   (0x00008000u)
+#define CPSW_CPDMA_RX_INTSTAT_RAW_RX7_THRESH_PEND_SHIFT   (0x0000000Fu)
+
+
+/* RX_INTSTAT_MASKED */
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX0_PEND   (0x00000001u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX0_PEND_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX0_THRESH_PEND   (0x00000100u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX0_THRESH_PEND_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX1_PEND   (0x00000002u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX1_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX1_THRESH_PEND   (0x00000200u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX1_THRESH_PEND_SHIFT   (0x00000009u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX2_PEND   (0x00000004u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX2_PEND_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX2_THRESH_PEND   (0x00000400u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX2_THRESH_PEND_SHIFT   (0x0000000Au)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX3_PEND   (0x00000008u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX3_PEND_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX3_THRESH_PEND   (0x00000800u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX3_THRESH_PEND_SHIFT   (0x0000000Bu)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX4_PEND   (0x00000010u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX4_PEND_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX4_THRESH_PEND   (0x00001000u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX4_THRESH_PEND_SHIFT   (0x0000000Cu)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX5_PEND   (0x00000020u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX5_PEND_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX5_THRESH_PEND   (0x00002000u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX5_THRESH_PEND_SHIFT   (0x0000000Du)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX6_PEND   (0x00000040u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX6_PEND_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX6_THRESH_PEND   (0x00004000u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX6_THRESH_PEND_SHIFT   (0x0000000Eu)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX7_PEND   (0x00000080u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX7_PEND_SHIFT   (0x00000007u)
+
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX7_THRESH_PEND   (0x00008000u)
+#define CPSW_CPDMA_RX_INTSTAT_MASKED_RX7_THRESH_PEND_SHIFT   (0x0000000Fu)
+
+
+/* RX_INTMASK_SET */
+#define CPSW_CPDMA_RX_INTMASK_SET_RX0_PEND_MASK   (0x00000001u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX0_PEND_MASK_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX0_THRESH_PEND_MASK   (0x00000100u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX0_THRESH_PEND_MASK_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX1_PEND_MASK   (0x00000002u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX1_PEND_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX1_THRESH_PEND_MASK   (0x00000200u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX1_THRESH_PEND_MASK_SHIFT   (0x00000009u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX2_PEND_MASK   (0x00000004u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX2_PEND_MASK_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX2_THRESH_PEND_MASK   (0x00000400u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX2_THRESH_PEND_MASK_SHIFT   (0x0000000Au)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX3_PEND_MASK   (0x00000008u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX3_PEND_MASK_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX3_THRESH_PEND_MASK   (0x00000800u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX3_THRESH_PEND_MASK_SHIFT   (0x0000000Bu)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX4_PEND_MASK   (0x00000010u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX4_PEND_MASK_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX4_THRESH_PEND_MASK   (0x00001000u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX4_THRESH_PEND_MASK_SHIFT   (0x0000000Cu)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX5_PEND_MASK   (0x00000020u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX5_PEND_MASK_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX5_THRESH_PEND_MASK   (0x00002000u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX5_THRESH_PEND_MASK_SHIFT   (0x0000000Du)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX6_PEND_MASK   (0x00000040u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX6_PEND_MASK_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX6_THRESH_PEND_MASK   (0x00004000u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX6_THRESH_PEND_MASK_SHIFT   (0x0000000Eu)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX7_PEND_MASK   (0x00000080u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX7_PEND_MASK_SHIFT   (0x00000007u)
+
+#define CPSW_CPDMA_RX_INTMASK_SET_RX7_THRESH_PEND_MASK   (0x00008000u)
+#define CPSW_CPDMA_RX_INTMASK_SET_RX7_THRESH_PEND_MASK_SHIFT   (0x0000000Fu)
+
+
+/* RX_INTMASK_CLEAR */
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX0_PEND_MASK   (0x00000001u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX0_PEND_MASK_SHIFT   (0x00000000u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX0_THRESH_PEND_MASK   (0x00000100u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX0_THRESH_PEND_MASK_SHIFT   (0x00000008u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX1_PEND_MASK   (0x00000002u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX1_PEND_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX1_THRESH_PEND_MASK   (0x00000200u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX1_THRESH_PEND_MASK_SHIFT   (0x00000009u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX2_PEND_MASK   (0x00000004u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX2_PEND_MASK_SHIFT   (0x00000002u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX2_THRESH_PEND_MASK   (0x00000400u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX2_THRESH_PEND_MASK_SHIFT   (0x0000000Au)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX3_PEND_MASK   (0x00000008u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX3_PEND_MASK_SHIFT   (0x00000003u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX3_THRESH_PEND_MASK   (0x00000800u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX3_THRESH_PEND_MASK_SHIFT   (0x0000000Bu)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX4_PEND_MASK   (0x00000010u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX4_PEND_MASK_SHIFT   (0x00000004u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX4_THRESH_PEND_MASK   (0x00001000u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX4_THRESH_PEND_MASK_SHIFT   (0x0000000Cu)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX5_PEND_MASK   (0x00000020u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX5_PEND_MASK_SHIFT   (0x00000005u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX5_THRESH_PEND_MASK   (0x00002000u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX5_THRESH_PEND_MASK_SHIFT   (0x0000000Du)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX6_PEND_MASK   (0x00000040u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX6_PEND_MASK_SHIFT   (0x00000006u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX6_THRESH_PEND_MASK   (0x00004000u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX6_THRESH_PEND_MASK_SHIFT   (0x0000000Eu)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX7_PEND_MASK   (0x00000080u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX7_PEND_MASK_SHIFT   (0x00000007u)
+
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX7_THRESH_PEND_MASK   (0x00008000u)
+#define CPSW_CPDMA_RX_INTMASK_CLEAR_RX7_THRESH_PEND_MASK_SHIFT   (0x0000000Fu)
+
+
+/* DMA_INTSTAT_RAW */
+#define CPSW_CPDMA_DMA_INTSTAT_RAW_HOST_PEND   (0x00000002u)
+#define CPSW_CPDMA_DMA_INTSTAT_RAW_HOST_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_DMA_INTSTAT_RAW_STAT_PEND   (0x00000001u)
+#define CPSW_CPDMA_DMA_INTSTAT_RAW_STAT_PEND_SHIFT   (0x00000000u)
+
+
+/* DMA_INTSTAT_MASKED */
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED_HOST_PEND   (0x00000002u)
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED_HOST_PEND_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED_STAT_PEND   (0x00000001u)
+#define CPSW_CPDMA_DMA_INTSTAT_MASKED_STAT_PEND_SHIFT   (0x00000000u)
+
+
+/* DMA_INTMASK_SET */
+#define CPSW_CPDMA_DMA_INTMASK_SET_HOST_ERR_INT_MASK   (0x00000002u)
+#define CPSW_CPDMA_DMA_INTMASK_SET_HOST_ERR_INT_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_DMA_INTMASK_SET_STAT_INT_MASK   (0x00000001u)
+#define CPSW_CPDMA_DMA_INTMASK_SET_STAT_INT_MASK_SHIFT   (0x00000000u)
+
+
+/* DMA_INTMASK_CLEAR */
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR_HOST_ERR_INT_MASK   (0x00000002u)
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR_HOST_ERR_INT_MASK_SHIFT   (0x00000001u)
+
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR_STAT_INT_MASK   (0x00000001u)
+#define CPSW_CPDMA_DMA_INTMASK_CLEAR_STAT_INT_MASK_SHIFT   (0x00000000u)
+
+
+/* RX0_PENDTHRESH */
+#define CPSW_CPDMA_RX0_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX0_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX1_PENDTHRESH */
+#define CPSW_CPDMA_RX1_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX1_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX2_PENDTHRESH */
+#define CPSW_CPDMA_RX2_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX2_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX3_PENDTHRESH */
+#define CPSW_CPDMA_RX3_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX3_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX4_PENDTHRESH */
+#define CPSW_CPDMA_RX4_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX4_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX5_PENDTHRESH */
+#define CPSW_CPDMA_RX5_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX5_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX6_PENDTHRESH */
+#define CPSW_CPDMA_RX6_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX6_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX7_PENDTHRESH */
+#define CPSW_CPDMA_RX7_PENDTHRESH_RX_PENDTHRESH   (0x000000FFu)
+#define CPSW_CPDMA_RX7_PENDTHRESH_RX_PENDTHRESH_SHIFT   (0x00000000u)
+
+
+/* RX0_FREEBUFFER */
+#define CPSW_CPDMA_RX0_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX0_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX1_FREEBUFFER */
+#define CPSW_CPDMA_RX1_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX1_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX2_FREEBUFFER */
+#define CPSW_CPDMA_RX2_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX2_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX3_FREEBUFFER */
+#define CPSW_CPDMA_RX3_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX3_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX4_FREEBUFFER */
+#define CPSW_CPDMA_RX4_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX4_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX5_FREEBUFFER */
+#define CPSW_CPDMA_RX5_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX5_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX6_FREEBUFFER */
+#define CPSW_CPDMA_RX6_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX6_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RX7_FREEBUFFER */
+#define CPSW_CPDMA_RX7_FREEBUFFER_RX_FREEBUFFER   (0x0000FFFFu)
+#define CPSW_CPDMA_RX7_FREEBUFFER_RX_FREEBUFFER_SHIFT   (0x00000000u)
+
+
+/* RXGOODFRAMES */
+#define CPSW_CPDMA_RXGOODFRAMES_RXGOODFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXGOODFRAMES_RXGOODFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXBROADCASTFRAMES */
+#define CPSW_CPDMA_RXBROADCASTFRAMES_RXBROADCASTFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXBROADCASTFRAMES_RXBROADCASTFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXMULTICASTFRAMES */
+#define CPSW_CPDMA_RXMULTICASTFRAMES_RXMULTICASTFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXMULTICASTFRAMES_RXMULTICASTFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXPAUSEFRAMES */
+#define CPSW_CPDMA_RXPAUSEFRAMES_RXPAUSEFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXPAUSEFRAMES_RXPAUSEFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXCRCERRORS */
+#define CPSW_CPDMA_RXCRCERRORS_RXCRCERRORS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXCRCERRORS_RXCRCERRORS_SHIFT   (0x00000000u)
+
+
+/* RXALIGNCODEERRORS */
+#define CPSW_CPDMA_RXALIGNCODEERRORS_RXALIGNCODEERRORS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXALIGNCODEERRORS_RXALIGNCODEERRORS_SHIFT   (0x00000000u)
+
+
+/* RXOVERSIZEDFRAMES */
+#define CPSW_CPDMA_RXOVERSIZEDFRAMES_RXOVERSIZEDFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXOVERSIZEDFRAMES_RXOVERSIZEDFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXJABBERFRAMES */
+#define CPSW_CPDMA_RXJABBERFRAMES_RXJABBERFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXJABBERFRAMES_RXJABBERFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXUNDERSIZEDFRAMES */
+#define CPSW_CPDMA_RXUNDERSIZEDFRAMES_RXUNDERSIZEDFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXUNDERSIZEDFRAMES_RXUNDERSIZEDFRAMES_SHIFT   (0x00000000u)
+
+
+/* RXFRAGMENTS */
+#define CPSW_CPDMA_RXFRAGMENTS_RXFRAGMENTS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXFRAGMENTS_RXFRAGMENTS_SHIFT   (0x00000000u)
+
+
+/* RXOCTETS */
+#define CPSW_CPDMA_RXOCTETS_RXOCTETS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXOCTETS_RXOCTETS_SHIFT   (0x00000000u)
+
+
+/* TXGOODFRAMES */
+#define CPSW_CPDMA_TXGOODFRAMES_TXGOODFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXGOODFRAMES_TXGOODFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXBROADCASTFRAMES */
+#define CPSW_CPDMA_TXBROADCASTFRAMES_TXBROADCASTFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXBROADCASTFRAMES_TXBROADCASTFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXMULTICASTFRAMES */
+#define CPSW_CPDMA_TXMULTICASTFRAMES_TXMULTICASTFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXMULTICASTFRAMES_TXMULTICASTFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXPAUSEFRAMES */
+#define CPSW_CPDMA_TXPAUSEFRAMES_TXPAUSEFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXPAUSEFRAMES_TXPAUSEFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXDEFERREDFRAMES */
+#define CPSW_CPDMA_TXDEFERREDFRAMES_TXDEFERREDFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXDEFERREDFRAMES_TXDEFERREDFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXCOLLISIONFRAMES */
+#define CPSW_CPDMA_TXCOLLISIONFRAMES_TXCOLLISIONFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXCOLLISIONFRAMES_TXCOLLISIONFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXSINGLECOLLFRAMES */
+#define CPSW_CPDMA_TXSINGLECOLLFRAMES_TXSINGLECOLLFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXSINGLECOLLFRAMES_TXSINGLECOLLFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXMULTCOLLFRAMES */
+#define CPSW_CPDMA_TXMULTCOLLFRAMES_TXMULTCOLLFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXMULTCOLLFRAMES_TXMULTCOLLFRAMES_SHIFT   (0x00000000u)
+
+
+/* TXEXCESSIVECOLLISIONS */
+#define CPSW_CPDMA_TXEXCESSIVECOLLISIONS_TXEXCESSIVECOLLISIONS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXEXCESSIVECOLLISIONS_TXEXCESSIVECOLLISIONS_SHIFT   (0x00000000u)
+
+
+/* TXLATECOLLISIONS */
+#define CPSW_CPDMA_TXLATECOLLISIONS_TXLATECOLLISIONS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXLATECOLLISIONS_TXLATECOLLISIONS_SHIFT   (0x00000000u)
+
+
+/* TXUNDERRUN */
+#define CPSW_CPDMA_TXUNDERRUN_TXUNDERRUN   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXUNDERRUN_TXUNDERRUN_SHIFT   (0x00000000u)
+
+
+/* TXCARRIERSENSEERRORS */
+#define CPSW_CPDMA_TXCARRIERSENSEERRORS_TXCARRIERSENSEERRORS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXCARRIERSENSEERRORS_TXCARRIERSENSEERRORS_SHIFT   (0x00000000u)
+
+
+/* TXOCTETS */
+#define CPSW_CPDMA_TXOCTETS_TXOCTETS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TXOCTETS_TXOCTETS_SHIFT   (0x00000000u)
+
+
+/* 64OCTETFRAMES */
+#define CPSW_CPDMA_64OCTETFRAMES_64OCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_64OCTETFRAMES_64OCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* 65T127OCTETFRAMES */
+#define CPSW_CPDMA_65T127OCTETFRAMES_65T127OCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_65T127OCTETFRAMES_65T127OCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* 128T255OCTETFRAMES */
+#define CPSW_CPDMA_128T255OCTETFRAMES_128T255OCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_128T255OCTETFRAMES_128T255OCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* 256T511OCTETFRAMES */
+#define CPSW_CPDMA_256T511OCTETFRAMES_256T511OCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_256T511OCTETFRAMES_256T511OCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* 512T1023OCTETFRAMES */
+#define CPSW_CPDMA_512T1023OCTETFRAMES_512T1023OCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_512T1023OCTETFRAMES_512T1023OCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* 1024TUPOCTETFRAMES */
+#define CPSW_CPDMA_1024TUPOCTETFRAMES_1024TUPOCTETFRAMES   (0xFFFFFFFFu)
+#define CPSW_CPDMA_1024TUPOCTETFRAMES_1024TUPOCTETFRAMES_SHIFT   (0x00000000u)
+
+
+/* NETOCTETS */
+#define CPSW_CPDMA_NETOCTETS_NETOCTETS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_NETOCTETS_NETOCTETS_SHIFT   (0x00000000u)
+
+
+/* RXSOFOVERRUNS */
+#define CPSW_CPDMA_RXSOFOVERRUNS_RXSOFOVERRUNS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXSOFOVERRUNS_RXSOFOVERRUNS_SHIFT   (0x00000000u)
+
+
+/* RXMOFOVERRUNS */
+#define CPSW_CPDMA_RXMOFOVERRUNS_RXMOFOVERRUNS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXMOFOVERRUNS_RXMOFOVERRUNS_SHIFT   (0x00000000u)
+
+
+/* RXDMAOVERRUNS */
+#define CPSW_CPDMA_RXDMAOVERRUNS_RXDMAOVERRUNS   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RXDMAOVERRUNS_RXDMAOVERRUNS_SHIFT   (0x00000000u)
+
+
+/* TX0_HDP */
+#define CPSW_CPDMA_TX0_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX0_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX1_HDP */
+#define CPSW_CPDMA_TX1_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX1_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX2_HDP */
+#define CPSW_CPDMA_TX2_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX2_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX3_HDP */
+#define CPSW_CPDMA_TX3_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX3_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX4_HDP */
+#define CPSW_CPDMA_TX4_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX4_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX5_HDP */
+#define CPSW_CPDMA_TX5_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX5_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX6_HDP */
+#define CPSW_CPDMA_TX6_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX6_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX7_HDP */
+#define CPSW_CPDMA_TX7_HDP_TX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX7_HDP_TX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX0_HDP */
+#define CPSW_CPDMA_RX0_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX0_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX1_HDP */
+#define CPSW_CPDMA_RX1_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX1_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX2_HDP */
+#define CPSW_CPDMA_RX2_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX2_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX3_HDP */
+#define CPSW_CPDMA_RX3_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX3_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX4_HDP */
+#define CPSW_CPDMA_RX4_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX4_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX5_HDP */
+#define CPSW_CPDMA_RX5_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX5_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX6_HDP */
+#define CPSW_CPDMA_RX6_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX6_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* RX7_HDP */
+#define CPSW_CPDMA_RX7_HDP_RX_HDP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX7_HDP_RX_HDP_SHIFT   (0x00000000u)
+
+
+/* TX0_CP */
+#define CPSW_CPDMA_TX0_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX0_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX1_CP */
+#define CPSW_CPDMA_TX1_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX1_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX2_CP */
+#define CPSW_CPDMA_TX2_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX2_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX3_CP */
+#define CPSW_CPDMA_TX3_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX3_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX4_CP */
+#define CPSW_CPDMA_TX4_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX4_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX5_CP */
+#define CPSW_CPDMA_TX5_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX5_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX6_CP */
+#define CPSW_CPDMA_TX6_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX6_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* TX7_CP */
+#define CPSW_CPDMA_TX7_CP_TX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_TX7_CP_TX_CP_SHIFT   (0x00000000u)
+
+
+/* RX0_CP */
+#define CPSW_CPDMA_RX0_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX0_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX1_CP */
+#define CPSW_CPDMA_RX1_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX1_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX2_CP */
+#define CPSW_CPDMA_RX2_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX2_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX3_CP */
+#define CPSW_CPDMA_RX3_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX3_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX4_CP */
+#define CPSW_CPDMA_RX4_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX4_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX5_CP */
+#define CPSW_CPDMA_RX5_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX5_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX6_CP */
+#define CPSW_CPDMA_RX6_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX6_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+/* RX7_CP */
+#define CPSW_CPDMA_RX7_CP_RX_CP   (0xFFFFFFFFu)
+#define CPSW_CPDMA_RX7_CP_RX_CP_SHIFT   (0x00000000u)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_cpsw_port.h b/cpsw/src/include/hw_cpsw_port.h
new file mode 100755
index 0000000..02eab5d
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_port.h
@@ -0,0 +1,1173 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_port_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CPSW_PORT_H_
+#define _HW_CPSW_PORT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_PORT_CONTROL   (0x0)
+#define CPSW_PORT_MAX_BLKS   (0x8)
+#define CPSW_PORT_BLK_CNT   (0xc)
+#define CPSW_PORT_TX_IN_CTL   (0x10)
+#define CPSW_PORT_PORT_VLAN   (0x14)
+#define CPSW_PORT_TX_PRI_MAP   (0x18)
+#define CPSW_PORT_CPDMA_TX_PRI_MAP0   (0x1c)
+#define CPSW_PORT_CPDMA_RX_CH_MAP0   (0x20)
+#define CPSW_PORT_RX_DSCP_PRI_MAP(n)   (0x30 + (n * 4))
+#define CPSW_PORT_TS_SEQ_MTYPE   (0x1c)
+#define CPSW_PORT_SA_LO  (0x20)
+#define CPSW_PORT_SA_HI   (0x24)
+#define CPSW_PORT_SEND_PERCENT   (0x28)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* P0_CONTROL */
+#define CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH   (0x70000000u)
+#define CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH_SHIFT   (0x0000001Cu)
+
+#define CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN   (0x00010000u)
+#define CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED   (0x01000000u)
+#define CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN   (0x00100000u)
+#define CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN   (0x00200000u)
+#define CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN_SHIFT   (0x00000015u)
+
+
+/* P0_MAX_BLKS */
+#define CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS   (0x0000000Fu)
+#define CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS   (0x000001F0u)
+#define CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_SHIFT   (0x00000004u)
+
+
+/* P0_BLK_CNT */
+#define CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT   (0x0000000Fu)
+#define CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT   (0x000001F0u)
+#define CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT_SHIFT   (0x00000004u)
+
+
+/* P0_TX_IN_CTL */
+#define CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM   (0x0000F000u)
+#define CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL   (0x00030000u)
+#define CPSW_PORT_P0_TX_IN_CTL_TX_IN_DUAL_MAC   (0x00010000u)
+#define CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS   (0x000003FFu)
+#define CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN   (0x00F00000u)
+#define CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN_SHIFT   (0x00000014u)
+
+
+/* P0_PORT_VLAN */
+#define CPSW_PORT_P0_PORT_VLAN_PORT_CFI   (0x00001000u)
+#define CPSW_PORT_P0_PORT_VLAN_PORT_CFI_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_PORT_VLAN_PORT_PRI   (0x0000E000u)
+#define CPSW_PORT_P0_PORT_VLAN_PORT_PRI_SHIFT   (0x0000000Du)
+
+#define CPSW_PORT_P0_PORT_VLAN_PORT_VID   (0x00000FFFu)
+#define CPSW_PORT_P0_PORT_VLAN_PORT_VID_SHIFT   (0x00000000u)
+
+
+/* P0_TX_PRI_MAP */
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI0   (0x00000003u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI1   (0x00000030u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI2   (0x00000300u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI3   (0x00003000u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI4   (0x00030000u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI5   (0x00300000u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI6   (0x03000000u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI7   (0x30000000u)
+#define CPSW_PORT_P0_TX_PRI_MAP_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P0_CPDMA_TX_PRI_MAP */
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0   (0x00000007u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1   (0x00000070u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2   (0x00000700u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3   (0x00007000u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4   (0x00070000u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5   (0x00700000u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6   (0x07000000u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7   (0x70000000u)
+#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P0_CPDMA_RX_CH_MAP */
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0   (0x00000007u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1   (0x00000070u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2   (0x00000700u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3   (0x00007000u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0   (0x00070000u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1   (0x00700000u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2   (0x07000000u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3   (0x70000000u)
+#define CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP0 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP1 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15_SHIFT   (0x0000001Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9_SHIFT   (0x00000004u)
+
+
+/* P0_RX_DSCP_PRI_MAP2 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP3 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP4 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP5 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP6 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55_SHIFT   (0x0000001Cu)
+
+
+/* P0_RX_DSCP_PRI_MAP7 */
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56   (0x00000007u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57   (0x00000070u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58   (0x00000700u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59   (0x00007000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60   (0x00070000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61   (0x00700000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62   (0x07000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63   (0x70000000u)
+#define CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63_SHIFT   (0x0000001Cu)
+
+
+/* P1_CONTROL */
+#define CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN   (0x00010000u)
+#define CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED   (0x01000000u)
+#define CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_129   (0x00000200u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_129_SHIFT   (0x00000009u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_130   (0x00000400u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_130_SHIFT   (0x0000000Au)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_131   (0x00000800u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_131_SHIFT   (0x0000000Bu)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_132   (0x00001000u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_132_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_319   (0x00002000u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_319_SHIFT   (0x0000000Du)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_320   (0x00004000u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_320_SHIFT   (0x0000000Eu)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN   (0x00000010u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN   (0x00000004u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN_SHIFT   (0x00000002u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN   (0x00000008u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN_SHIFT   (0x00000003u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_RX_EN   (0x00000001u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_RX_EN_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_CONTROL_P1_TS_TX_EN   (0x00000002u)
+#define CPSW_PORT_P1_CONTROL_P1_TS_TX_EN_SHIFT   (0x00000001u)
+
+#define CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN   (0x00100000u)
+#define CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN   (0x00200000u)
+#define CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN_SHIFT   (0x00000015u)
+
+
+/* P1_MAX_BLKS */
+#define CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS   (0x0000000Fu)
+#define CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS   (0x000001F0u)
+#define CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS_SHIFT   (0x00000004u)
+
+
+/* P1_BLK_CNT */
+#define CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT   (0x0000000Fu)
+#define CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT   (0x000001F0u)
+#define CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT_SHIFT   (0x00000004u)
+
+
+/* P1_TX_IN_CTL */
+#define CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM   (0x0F000000u)
+#define CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM   (0x0000F000u)
+#define CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL   (0x00030000u)
+#define CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS   (0x000003FFu)
+#define CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN   (0x00F00000u)
+#define CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN_SHIFT   (0x00000014u)
+
+
+/* P1_PORT_VLAN */
+#define CPSW_PORT_P1_PORT_VLAN_PORT_CFI   (0x00001000u)
+#define CPSW_PORT_P1_PORT_VLAN_PORT_CFI_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_PORT_VLAN_PORT_PRI   (0x0000E000u)
+#define CPSW_PORT_P1_PORT_VLAN_PORT_PRI_SHIFT   (0x0000000Du)
+
+#define CPSW_PORT_P1_PORT_VLAN_PORT_VID   (0x00000FFFu)
+#define CPSW_PORT_P1_PORT_VLAN_PORT_VID_SHIFT   (0x00000000u)
+
+
+/* P1_TX_PRI_MAP */
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI0   (0x00000003u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI1   (0x00000030u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI2   (0x00000300u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI3   (0x00003000u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI4   (0x00030000u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI5   (0x00300000u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI6   (0x03000000u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI7   (0x30000000u)
+#define CPSW_PORT_P1_TX_PRI_MAP_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P1_TS_SEQ_MTYPE */
+#define CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN   (0x0000FFFFu)
+#define CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET   (0x003F0000u)
+#define CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET_SHIFT   (0x00000010u)
+
+
+/* P1_SA_LO */
+#define CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8   (0x000000FFu)
+#define CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0   (0x0000FF00u)
+#define CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_SHIFT   (0x00000008u)
+
+
+/* P1_SA_HI */
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16   (0xFF000000u)
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24   (0x00FF0000u)
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32   (0x0000FF00u)
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40   (0x000000FFu)
+#define CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40_SHIFT   (0x00000000u)
+
+
+/* P1_SEND_PERCENT */
+#define CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT   (0x0000007Fu)
+#define CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT   (0x00007F00u)
+#define CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT   (0x007F0000u)
+#define CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT_SHIFT   (0x00000010u)
+
+
+/* P1_RX_DSCP_PRI_MAP0 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP1 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15_SHIFT   (0x0000001Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9_SHIFT   (0x00000004u)
+
+
+/* P1_RX_DSCP_PRI_MAP2 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP3 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP4 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP5 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP6 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55_SHIFT   (0x0000001Cu)
+
+
+/* P1_RX_DSCP_PRI_MAP7 */
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56   (0x00000007u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57   (0x00000070u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58   (0x00000700u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59   (0x00007000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60   (0x00070000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61   (0x00700000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62   (0x07000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63   (0x70000000u)
+#define CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63_SHIFT   (0x0000001Cu)
+
+
+/* P2_CONTROL */
+#define CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN   (0x00010000u)
+#define CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED   (0x01000000u)
+#define CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_129   (0x00080000u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_129_SHIFT   (0x00000013u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_130   (0x00000400u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_130_SHIFT   (0x0000000Au)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_131   (0x00000800u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_131_SHIFT   (0x0000000Bu)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_132   (0x00001000u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_132_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_319   (0x00002000u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_319_SHIFT   (0x0000000Du)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_320   (0x00004000u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_320_SHIFT   (0x0000000Eu)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN   (0x00000010u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN   (0x00000004u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN_SHIFT   (0x00000002u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN   (0x00000008u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN_SHIFT   (0x00000003u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_RX_EN   (0x00000001u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_RX_EN_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_CONTROL_P2_TS_TX_EN   (0x00000002u)
+#define CPSW_PORT_P2_CONTROL_P2_TS_TX_EN_SHIFT   (0x00000001u)
+
+#define CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN   (0x00100000u)
+#define CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN   (0x00200000u)
+#define CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN_SHIFT   (0x00000015u)
+
+
+/* P2_MAX_BLKS */
+#define CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS   (0x0000000Fu)
+#define CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS   (0x000001F0u)
+#define CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS_SHIFT   (0x00000004u)
+
+
+/* P2_BLK_CNT */
+#define CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT   (0x0000000Fu)
+#define CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT   (0x000001F0u)
+#define CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT_SHIFT   (0x00000004u)
+
+
+/* P2_TX_IN_CTL */
+#define CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM   (0x0F000000u)
+#define CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM   (0x0000F000u)
+#define CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL   (0x00030000u)
+#define CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS   (0x000003FFu)
+#define CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN   (0x00F00000u)
+#define CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN_SHIFT   (0x00000014u)
+
+
+/* P2_PORT_VLAN */
+#define CPSW_PORT_P2_PORT_VLAN_PORT_CFI   (0x00001000u)
+#define CPSW_PORT_P2_PORT_VLAN_PORT_CFI_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_PORT_VLAN_PORT_PRI   (0x0000E000u)
+#define CPSW_PORT_P2_PORT_VLAN_PORT_PRI_SHIFT   (0x0000000Du)
+
+#define CPSW_PORT_P2_PORT_VLAN_PORT_VID   (0x00000FFFu)
+#define CPSW_PORT_P2_PORT_VLAN_PORT_VID_SHIFT   (0x00000000u)
+
+
+/* P2_TX_PRI_MAP */
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI0   (0x00000003u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI1   (0x00000030u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI2   (0x00000300u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI3   (0x00003000u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI4   (0x00030000u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI5   (0x00300000u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI6   (0x03000000u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI7   (0x30000000u)
+#define CPSW_PORT_P2_TX_PRI_MAP_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P2_TS_SEQ_MTYPE */
+#define CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN   (0x0000FFFFu)
+#define CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET   (0x003F0000u)
+#define CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET_SHIFT   (0x00000010u)
+
+
+/* P2_SA_LO */
+#define CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8   (0x000000FFu)
+#define CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0   (0x0000FF00u)
+#define CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0_SHIFT   (0x00000008u)
+
+
+/* P2_SA_HI */
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16   (0xFF000000u)
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23   (0x00FF0000u)
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32   (0x0000FF00u)
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40   (0x000000FFu)
+#define CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40_SHIFT   (0x00000000u)
+
+
+/* P2_SEND_PERCENT */
+#define CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT   (0x0000007Fu)
+#define CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT   (0x00007F00u)
+#define CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT   (0x007F0000u)
+#define CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT_SHIFT   (0x00000010u)
+
+
+/* P2_RX_DSCP_PRI_MAP0 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP1 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15_SHIFT   (0x0000001Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9_SHIFT   (0x00000004u)
+
+
+/* P2_RX_DSCP_PRI_MAP2 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP3 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP4 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP5 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP6 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55_SHIFT   (0x0000001Cu)
+
+
+/* P2_RX_DSCP_PRI_MAP7 */
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56   (0x00000007u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56_SHIFT   (0x00000000u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57   (0x00000070u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57_SHIFT   (0x00000004u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58   (0x00000700u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58_SHIFT   (0x00000008u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59   (0x00007000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59_SHIFT   (0x0000000Cu)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60   (0x00070000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60_SHIFT   (0x00000010u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61   (0x00700000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61_SHIFT   (0x00000014u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62   (0x07000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62_SHIFT   (0x00000018u)
+
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63   (0x70000000u)
+#define CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63_SHIFT   (0x0000001Cu)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_cpsw_sl.h b/cpsw/src/include/hw_cpsw_sl.h
new file mode 100755
index 0000000..468fe7d
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_sl.h
@@ -0,0 +1,240 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_sl_cred.h
+ *
+ ============================================================================ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_CPSW_SL_H_
+#define _HW_CPSW_SL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_SL_IDVER   (0x0)
+#define CPSW_SL_MACCONTROL   (0x4)
+#define CPSW_SL_MACSTATUS   (0x8)
+#define CPSW_SL_SOFT_RESET   (0xc)
+#define CPSW_SL_RX_MAXLEN  (0x10)
+#define CPSW_SL_BOFFTEST  (0x14)
+#define CPSW_SL_RX_PAUSE   (0x18)
+#define CPSW_SL_TX_PAUSE   (0x1c)
+#define CPSW_SL_EMCONTROL   (0x20)
+#define CPSW_SL_RX_PRI_MAP   (0x24)
+#define CPSW_SL_TX_GAP   (0x28)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* SL1_IDVER */
+#define CPSW_SL_IDVER_IDENT   (0xFFFF0000u)
+#define CPSW_SL_IDVER_IDENT_SHIFT   (0x00000010u)
+
+#define CPSW_SL_IDVER_X   (0x00000700u)
+#define CPSW_SL_IDVER_X_SHIFT   (0x00000008u)
+
+#define CPSW_SL_IDVER_Y   (0x000000FFu)
+#define CPSW_SL_IDVER_Y_SHIFT   (0x00000000u)
+
+#define CPSW_SL_IDVER_Z   (0x0000F800u)
+#define CPSW_SL_IDVER_Z_SHIFT   (0x0000000Bu)
+
+
+/* SL1_MACCONTROL */
+#define CPSW_SL_MACCONTROL_CMD_IDLE   (0x00000800u)
+#define CPSW_SL_MACCONTROL_CMD_IDLE_SHIFT   (0x0000000Bu)
+
+#define CPSW_SL_MACCONTROL_EXT_EN   (0x00040000u)
+#define CPSW_SL_MACCONTROL_EXT_EN_SHIFT   (0x00000012u)
+
+#define CPSW_SL_MACCONTROL_FULLDUPLEX   (0x00000001u)
+#define CPSW_SL_MACCONTROL_FULLDUPLEX_SHIFT   (0x00000000u)
+
+#define CPSW_SL_MACCONTROL_GIG   (0x00000080u)
+#define CPSW_SL_MACCONTROL_GIG_SHIFT   (0x00000007u)
+
+#define CPSW_SL_MACCONTROL_GIG_FORCE   (0x00020000u)
+#define CPSW_SL_MACCONTROL_GIG_FORCE_SHIFT   (0x00000011u)
+
+#define CPSW_SL_MACCONTROL_GMII_EN   (0x00000020u)
+#define CPSW_SL_MACCONTROL_GMII_EN_SHIFT   (0x00000005u)
+
+#define CPSW_SL_MACCONTROL_IFCTL_A   (0x00008000u)
+#define CPSW_SL_MACCONTROL_IFCTL_A_SHIFT   (0x0000000Fu)
+
+#define CPSW_SL_MACCONTROL_IFCTL_B   (0x00010000u)
+#define CPSW_SL_MACCONTROL_IFCTL_B_SHIFT   (0x00000010u)
+
+#define CPSW_SL_MACCONTROL_LOOPBACK   (0x00000002u)
+#define CPSW_SL_MACCONTROL_LOOPBACK_SHIFT   (0x00000001u)
+
+#define CPSW_SL_MACCONTROL_MTEST   (0x00000004u)
+#define CPSW_SL_MACCONTROL_MTEST_SHIFT   (0x00000002u)
+
+#define CPSW_SL_MACCONTROL_RX_CEF_EN   (0x00400000u)
+#define CPSW_SL_MACCONTROL_RX_CEF_EN_SHIFT   (0x00000016u)
+
+#define CPSW_SL_MACCONTROL_RX_CMF_EN   (0x01000000u)
+#define CPSW_SL_MACCONTROL_RX_CMF_EN_SHIFT   (0x00000018u)
+
+#define CPSW_SL_MACCONTROL_RX_CSF_EN   (0x00800000u)
+#define CPSW_SL_MACCONTROL_RX_CSF_EN_SHIFT   (0x00000017u)
+
+#define CPSW_SL_MACCONTROL_RX_FLOW_EN   (0x00000008u)
+#define CPSW_SL_MACCONTROL_RX_FLOW_EN_SHIFT   (0x00000003u)
+
+#define CPSW_SL_MACCONTROL_TX_FLOW_EN   (0x00000010u)
+#define CPSW_SL_MACCONTROL_TX_FLOW_EN_SHIFT   (0x00000004u)
+
+#define CPSW_SL_MACCONTROL_TX_PACE   (0x00000040u)
+#define CPSW_SL_MACCONTROL_TX_PACE_SHIFT   (0x00000006u)
+
+#define CPSW_SL_MACCONTROL_TX_SHORT_GAP_EN   (0x00000400u)
+#define CPSW_SL_MACCONTROL_TX_SHORT_GAP_EN_SHIFT   (0x0000000Au)
+
+#define CPSW_SL_MACCONTROL_TX_SHORT_GAP_LIM_EN   (0x00200000u)
+#define CPSW_SL_MACCONTROL_TX_SHORT_GAP_LIM_EN_SHIFT   (0x00000015u)
+
+
+/* SL1_MACSTATUS */
+#define CPSW_SL_MACSTATUS_EXT_FULLDUPLEX   (0x00000008u)
+#define CPSW_SL_MACSTATUS_EXT_FULLDUPLEX_SHIFT   (0x00000003u)
+
+#define CPSW_SL_MACSTATUS_EXT_GIG   (0x00000010u)
+#define CPSW_SL_MACSTATUS_EXT_GIG_SHIFT   (0x00000004u)
+
+#define CPSW_SL_MACSTATUS_IDLE   (0x80000000u)
+#define CPSW_SL_MACSTATUS_IDLE_SHIFT   (0x0000001Fu)
+
+#define CPSW_SL_MACSTATUS_RX_FLOW_ACT   (0x00000002u)
+#define CPSW_SL_MACSTATUS_RX_FLOW_ACT_SHIFT   (0x00000001u)
+
+#define CPSW_SL_MACSTATUS_TX_FLOW_ACT   (0x00000001u)
+#define CPSW_SL_MACSTATUS_TX_FLOW_ACT_SHIFT   (0x00000000u)
+
+
+/* SL1_SOFT_RESET */
+#define CPSW_SL_SOFT_RESET_SOFT_RESET   (0x00000001u)
+#define CPSW_SL_SOFT_RESET_SOFT_RESET_SHIFT   (0x00000000u)
+
+
+/* SL1_RX_MAXLEN */
+#define CPSW_SL_RX_MAXLEN_RX_MAXLEN   (0x00003FFFu)
+#define CPSW_SL_RX_MAXLEN_RX_MAXLEN_SHIFT   (0x00000000u)
+
+
+/* SL1_BOFFTEST */
+#define CPSW_SL_BOFFTEST_COLL_COUNT   (0x0000F000u)
+#define CPSW_SL_BOFFTEST_COLL_COUNT_SHIFT   (0x0000000Cu)
+
+#define CPSW_SL_BOFFTEST_PACEVAL   (0x7C000000u)
+#define CPSW_SL_BOFFTEST_PACEVAL_SHIFT   (0x0000001Au)
+
+#define CPSW_SL_BOFFTEST_RNDNUM   (0x03FF0000u)
+#define CPSW_SL_BOFFTEST_RNDNUM_SHIFT   (0x00000010u)
+
+#define CPSW_SL_BOFFTEST_TX_BACKOFF   (0x000003FFu)
+#define CPSW_SL_BOFFTEST_TX_BACKOFF_SHIFT   (0x00000000u)
+
+
+/* SL1_EMCONTROL */
+#define CPSW_SL_EMCONTROL_FREE   (0x00000001u)
+#define CPSW_SL_EMCONTROL_FREE_SHIFT   (0x00000000u)
+
+#define CPSW_SL_EMCONTROL_SOFT   (0x00000002u)
+#define CPSW_SL_EMCONTROL_SOFT_SHIFT   (0x00000001u)
+
+
+/* SL1_RX_PRI_MAP */
+#define CPSW_SL_RX_PRI_MAP_PRI0   (0x00000007u)
+#define CPSW_SL_RX_PRI_MAP_PRI0_SHIFT   (0x00000000u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI1   (0x00000070u)
+#define CPSW_SL_RX_PRI_MAP_PRI1_SHIFT   (0x00000004u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI2   (0x00000700u)
+#define CPSW_SL_RX_PRI_MAP_PRI2_SHIFT   (0x00000008u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI3   (0x00007000u)
+#define CPSW_SL_RX_PRI_MAP_PRI3_SHIFT   (0x0000000Cu)
+
+#define CPSW_SL_RX_PRI_MAP_PRI4   (0x00070000u)
+#define CPSW_SL_RX_PRI_MAP_PRI4_SHIFT   (0x00000010u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI5   (0x00700000u)
+#define CPSW_SL_RX_PRI_MAP_PRI5_SHIFT   (0x00000014u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI6   (0x07000000u)
+#define CPSW_SL_RX_PRI_MAP_PRI6_SHIFT   (0x00000018u)
+
+#define CPSW_SL_RX_PRI_MAP_PRI7   (0x70000000u)
+#define CPSW_SL_RX_PRI_MAP_PRI7_SHIFT   (0x0000001Cu)
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_cpsw_ss.h b/cpsw/src/include/hw_cpsw_ss.h
new file mode 100755
index 0000000..1b1047a
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_ss.h
@@ -0,0 +1,227 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_ss_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CPSW_SS_H_
+#define _HW_CPSW_SS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_SS_ID_VER   (0x0)
+#define CPSW_SS_CONTROL   (0x4)
+#define CPSW_SS_SOFT_RESET   (0x8)
+#define CPSW_SS_STAT_PORT_EN   (0xc)
+#define CPSW_SS_PTYPE   (0x10)
+#define CPSW_SS_SOFT_IDLE   (0x14)
+#define CPSW_SS_THRU_RATE   (0x18)
+#define CPSW_SS_GAP_THRESH   (0x1c)
+#define CPSW_SS_TX_START_WDS   (0x20)
+#define CPSW_SS_FLOW_CONTROL   (0x24)
+#define CPSW_SS_VLAN_LTYPE   (0x28)
+#define CPSW_SS_TS_LTYPE   (0x2c)
+#define CPSW_SS_DLR_LTYPE   (0x30)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* ID_VER */
+#define CPSW_SS_ID_VER_CPSW_3G_IDENT   (0xFFFF0000u)
+#define CPSW_SS_ID_VER_CPSW_3G_IDENT_SHIFT   (0x00000010u)
+
+#define CPSW_SS_ID_VER_CPSW_3G_MAJ_VER   (0x00000700u)
+#define CPSW_SS_ID_VER_CPSW_3G_MAJ_VER_SHIFT   (0x00000008u)
+
+#define CPSW_SS_ID_VER_CPSW_3G_MINOR_VER   (0x000000FFu)
+#define CPSW_SS_ID_VER_CPSW_3G_MINOR_VER_SHIFT   (0x00000000u)
+
+#define CPSW_SS_ID_VER_CPSW_3G_RTL_VER   (0x0000F800u)
+#define CPSW_SS_ID_VER_CPSW_3G_RTL_VER_SHIFT   (0x0000000Bu)
+
+
+/* CONTROL */
+#define CPSW_SS_CONTROL_DLR_EN   (0x00000008u)
+#define CPSW_SS_CONTROL_DLR_EN_SHIFT   (0x00000003u)
+
+#define CPSW_SS_CONTROL_FIFO_LOOPBACK   (0x00000001u)
+#define CPSW_SS_CONTROL_FIFO_LOOPBACK_SHIFT   (0x00000000u)
+
+#define CPSW_SS_CONTROL_RX_VLAN_ENCAP   (0x00000004u)
+#define CPSW_SS_CONTROL_RX_VLAN_ENCAP_SHIFT   (0x00000002u)
+
+#define CPSW_SS_CONTROL_VLAN_AWARE   (0x00000002u)
+#define CPSW_SS_CONTROL_VLAN_AWARE_SHIFT   (0x00000001u)
+
+
+/* SOFT_RESET */
+#define CPSW_SS_SOFT_RESET_SOFT_RESET   (0x00000001u)
+#define CPSW_SS_SOFT_RESET_SOFT_RESET_SHIFT   (0x00000000u)
+
+
+/* STAT_PORT_EN */
+#define CPSW_SS_STAT_PORT_EN_P0_STAT_EN   (0x00000001u)
+#define CPSW_SS_STAT_PORT_EN_P0_STAT_EN_SHIFT   (0x00000000u)
+
+#define CPSW_SS_STAT_PORT_EN_P1_STAT_EN   (0x00000002u)
+#define CPSW_SS_STAT_PORT_EN_P1_STAT_EN_SHIFT   (0x00000001u)
+
+#define CPSW_SS_STAT_PORT_EN_P2_STAT_EN   (0x00000004u)
+#define CPSW_SS_STAT_PORT_EN_P2_STAT_EN_SHIFT   (0x00000002u)
+
+
+/* PTYPE */
+#define CPSW_SS_PTYPE_ESC_PRI_LD_VAL   (0x0000001Fu)
+#define CPSW_SS_PTYPE_ESC_PRI_LD_VAL_SHIFT   (0x00000000u)
+
+#define CPSW_SS_PTYPE_P0_PTYPE_ESC   (0x00000100u)
+#define CPSW_SS_PTYPE_P0_PTYPE_ESC_SHIFT   (0x00000008u)
+
+#define CPSW_SS_PTYPE_P1_PRI1_SHAPE_EN   (0x00010000u)
+#define CPSW_SS_PTYPE_P1_PRI1_SHAPE_EN_SHIFT   (0x00000010u)
+
+#define CPSW_SS_PTYPE_P1_PRI2_SHAPE_EN   (0x00020000u)
+#define CPSW_SS_PTYPE_P1_PRI2_SHAPE_EN_SHIFT   (0x00000011u)
+
+#define CPSW_SS_PTYPE_P1_PRI3_SHAPE_EN   (0x00040000u)
+#define CPSW_SS_PTYPE_P1_PRI3_SHAPE_EN_SHIFT   (0x00000012u)
+
+#define CPSW_SS_PTYPE_P1_PTYPE_ESC   (0x00000200u)
+#define CPSW_SS_PTYPE_P1_PTYPE_ESC_SHIFT   (0x00000009u)
+
+#define CPSW_SS_PTYPE_P2_PRI1_SHAPE_EN   (0x00080000u)
+#define CPSW_SS_PTYPE_P2_PRI1_SHAPE_EN_SHIFT   (0x00000013u)
+
+#define CPSW_SS_PTYPE_P2_PRI2_SHAPE_EN   (0x00100000u)
+#define CPSW_SS_PTYPE_P2_PRI2_SHAPE_EN_SHIFT   (0x00000014u)
+
+#define CPSW_SS_PTYPE_P2_PRI3_SHAPE_EN   (0x00200000u)
+#define CPSW_SS_PTYPE_P2_PRI3_SHAPE_EN_SHIFT   (0x00000015u)
+
+#define CPSW_SS_PTYPE_P2_PTYPE_ESC   (0x00000400u)
+#define CPSW_SS_PTYPE_P2_PTYPE_ESC_SHIFT   (0x0000000Au)
+
+
+/* SOFT_IDLE */
+#define CPSW_SS_SOFT_IDLE_SOFT_IDLE   (0x00000001u)
+#define CPSW_SS_SOFT_IDLE_SOFT_IDLE_SHIFT   (0x00000000u)
+
+
+/* THRU_RATE */
+#define CPSW_SS_THRU_RATE_CPDMA_THRU_RATE   (0x0000000Fu)
+#define CPSW_SS_THRU_RATE_CPDMA_THRU_RATE_SHIFT   (0x00000000u)
+
+#define CPSW_SS_THRU_RATE_SL_RX_THRU_RATE   (0x0000F000u)
+#define CPSW_SS_THRU_RATE_SL_RX_THRU_RATE_SHIFT   (0x0000000Cu)
+
+
+/* GAP_THRESH */
+#define CPSW_SS_GAP_THRESH_GAP_THRESH   (0x0000001Fu)
+#define CPSW_SS_GAP_THRESH_GAP_THRESH_SHIFT   (0x00000000u)
+
+
+/* TX_START_WDS */
+#define CPSW_SS_TX_START_WDS_TX_START_WDS   (0x000007FFu)
+#define CPSW_SS_TX_START_WDS_TX_START_WDS_SHIFT   (0x00000000u)
+
+
+/* FLOW_CONTROL */
+#define CPSW_SS_FLOW_CONTROL_P0_FLOW_EN   (0x00000001u)
+#define CPSW_SS_FLOW_CONTROL_P0_FLOW_EN_SHIFT   (0x00000000u)
+
+#define CPSW_SS_FLOW_CONTROL_P1_FLOW_EN   (0x00000002u)
+#define CPSW_SS_FLOW_CONTROL_P1_FLOW_EN_SHIFT   (0x00000001u)
+
+#define CPSW_SS_FLOW_CONTROL_P2_FLOW_EN   (0x00000004u)
+#define CPSW_SS_FLOW_CONTROL_P2_FLOW_EN_SHIFT   (0x00000002u)
+
+
+/* VLAN_LTYPE */
+#define CPSW_SS_VLAN_LTYPE_VLAN_LTYPE1   (0x0000FFFFu)
+#define CPSW_SS_VLAN_LTYPE_VLAN_LTYPE1_SHIFT   (0x00000000u)
+
+#define CPSW_SS_VLAN_LTYPE_VLAN_LTYPE2   (0xFFFF0000u)
+#define CPSW_SS_VLAN_LTYPE_VLAN_LTYPE2_SHIFT   (0x00000010u)
+
+
+/* TS_LTYPE */
+#define CPSW_SS_TS_LTYPE_TS_LTYPE1   (0x0000FFFFu)
+#define CPSW_SS_TS_LTYPE_TS_LTYPE1_SHIFT   (0x00000000u)
+
+#define CPSW_SS_TS_LTYPE_TS_LTYPE2   (0x003F0000u)
+#define CPSW_SS_TS_LTYPE_TS_LTYPE2_SHIFT   (0x00000010u)
+
+
+/* DLR_LTYPE */
+#define CPSW_SS_DLR_LTYPE_DLR_LTYPE   (0x0000FFFFu)
+#define CPSW_SS_DLR_LTYPE_DLR_LTYPE_SHIFT   (0x00000000u)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_cpsw_wr.h b/cpsw/src/include/hw_cpsw_wr.h
new file mode 100755
index 0000000..3fbd754
--- /dev/null
+++ b/cpsw/src/include/hw_cpsw_wr.h
@@ -0,0 +1,313 @@
+
+
+/**
+ *  @Component:   CPSW
+ *
+ *  @Filename:    cpsw_wr_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CPSW_WR_H_
+#define _HW_CPSW_WR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CPSW_WR_IDVER   (0x0)
+#define CPSW_WR_SOFT_RESET   (0x04)
+#define CPSW_WR_CONTROL   (0x08)
+#define CPSW_WR_INT_CONTROL   (0x0c)
+#define CPSW_WR_C_RX_THRESH_EN(n)   (0x10 + (n * 16))
+#define CPSW_WR_C_RX_EN(n)   (0x14 + (n * 16))
+#define CPSW_WR_C_TX_EN(n)   (0x18 + (n * 16))
+#define CPSW_WR_C_MISC_EN(n)   (0x1c + (n * 16))
+#define CPSW_WR_C_RX_THRESH_STAT(n)   (0x40 + (n * 16))
+#define CPSW_WR_C_RX_STAT(n)   (0x44 + (n * 16))
+#define CPSW_WR_C_TX_STAT(n)   (0x48 + (n * 16))
+#define CPSW_WR_C_MISC_STAT(n)   (0x4c + (n * 16))
+#define CPSW_WR_C_RX_IMAX(n)   (0x70 + (n * 8))
+#define CPSW_WR_C_TX_IMAX(n)   (0x74 + (n * 8))
+#define CPSW_WR_RGMII_CTL   (0x88)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* IDVER */
+#define CPSW_WR_IDVER_CUSTOM   (0x000000C0u)
+#define CPSW_WR_IDVER_CUSTOM_SHIFT   (0x00000006u)
+
+#define CPSW_WR_IDVER_FUNCTION   (0x0FFF0000u)
+#define CPSW_WR_IDVER_FUNCTION_SHIFT   (0x00000010u)
+
+#define CPSW_WR_IDVER_MAJOR   (0x00000700u)
+#define CPSW_WR_IDVER_MAJOR_SHIFT   (0x00000008u)
+
+#define CPSW_WR_IDVER_MINOR   (0x0000003Fu)
+#define CPSW_WR_IDVER_MINOR_SHIFT   (0x00000000u)
+
+#define CPSW_WR_IDVER_RTL   (0x0000F800u)
+#define CPSW_WR_IDVER_RTL_SHIFT   (0x0000000Bu)
+
+#define CPSW_WR_IDVER_SCHEME   (0xFFF00000u)
+#define CPSW_WR_IDVER_SCHEME_SHIFT   (0x00000014u)
+
+
+/* SOFT_RESET */
+#define CPSW_WR_SOFT_RESET_SOFT_RESET   (0x00000001u)
+#define CPSW_WR_SOFT_RESET_SOFT_RESET_SHIFT   (0x00000000u)
+
+
+/* CONTROL */
+#define CPSW_WR_CONTROL_MMR_RESET      (0x0000000Au)
+#define CPSW_WR_CONTROL_MMR_IDLEMODE   (0x00000003u)
+#define CPSW_WR_CONTROL_MMR_IDLEMODE_SHIFT   (0x00000000u)
+
+#define CPSW_WR_CONTROL_MMR_STDBYMODE   (0x0000000Cu)
+#define CPSW_WR_CONTROL_MMR_STDBYMODE_SHIFT   (0x00000002u)
+
+
+/* INT_CONTROL */
+#define CPSW_WR_INT_CONTROL_INT_PACE_EN   (0x003F0000u)
+#define CPSW_WR_INT_CONTROL_INT_PACE_EN_SHIFT   (0x00000010u)
+
+#define CPSW_WR_INT_CONTROL_INT_PRESCALE   (0x00000FFFu)
+#define CPSW_WR_INT_CONTROL_INT_PRESCALE_SHIFT   (0x00000000u)
+
+#define CPSW_WR_INT_CONTROL_INT_TEST   (0x80000000u)
+#define CPSW_WR_INT_CONTROL_INT_TEST_SHIFT   (0x0000001Fu)
+
+
+/* C0_RX_THRESH_EN */
+#define CPSW_WR_C0_RX_THRESH_EN_C0_RX_THRESH_EN   (0x000000FFu)
+#define CPSW_WR_C0_RX_THRESH_EN_C0_RX_THRESH_EN_SHIFT   (0x00000000u)
+
+
+/* C0_RX_EN */
+#define CPSW_WR_C0_RX_EN_C0_RX_EN   (0x000000FFu)
+#define CPSW_WR_C0_RX_EN_C0_RX_EN_SHIFT   (0x00000000u)
+
+
+/* C0_TX_EN */
+#define CPSW_WR_C0_TX_EN_C0_TX_EN   (0x000000FFu)
+#define CPSW_WR_C0_TX_EN_C0_TX_EN_SHIFT   (0x00000000u)
+
+
+/* C0_MISC_EN */
+#define CPSW_WR_C0_MISC_EN_C0_MISC_EN   (0x0000001Fu)
+#define CPSW_WR_C0_MISC_EN_C0_MISC_EN_SHIFT   (0x00000000u)
+
+
+/* C1_RX_THRESH_EN */
+#define CPSW_WR_C1_RX_THRESH_EN_C1_RX_THRESH_EN   (0x000000FFu)
+#define CPSW_WR_C1_RX_THRESH_EN_C1_RX_THRESH_EN_SHIFT   (0x00000000u)
+
+
+/* C1_RX_EN */
+#define CPSW_WR_C1_RX_EN_C1_RX_EN   (0x000000FFu)
+#define CPSW_WR_C1_RX_EN_C1_RX_EN_SHIFT   (0x00000000u)
+
+
+/* C1_TX_EN */
+#define CPSW_WR_C1_TX_EN_C1_TX_EN   (0x000000FFu)
+#define CPSW_WR_C1_TX_EN_C1_TX_EN_SHIFT   (0x00000000u)
+
+
+/* C1_MISC_EN */
+#define CPSW_WR_C1_MISC_EN_C1_MISC_EN   (0x0000001Fu)
+#define CPSW_WR_C1_MISC_EN_C1_MISC_EN_SHIFT   (0x00000000u)
+
+
+/* C2_RX_THRESH_EN */
+#define CPSW_WR_C2_RX_THRESH_EN_C2_RX_THRESH_EN   (0x000000FFu)
+#define CPSW_WR_C2_RX_THRESH_EN_C2_RX_THRESH_EN_SHIFT   (0x00000000u)
+
+
+/* C2_RX_EN */
+#define CPSW_WR_C2_RX_EN_C2_RX_EN   (0x000000FFu)
+#define CPSW_WR_C2_RX_EN_C2_RX_EN_SHIFT   (0x00000000u)
+
+
+/* C2_TX_EN */
+#define CPSW_WR_C2_TX_EN_C2_TX_EN   (0x000000FFu)
+#define CPSW_WR_C2_TX_EN_C2_TX_EN_SHIFT   (0x00000000u)
+
+
+/* C2_MISC_EN */
+#define CPSW_WR_C2_MISC_EN_C2_MISC_EN   (0x0000001Fu)
+#define CPSW_WR_C2_MISC_EN_C2_MISC_EN_SHIFT   (0x00000000u)
+
+
+/* C0_RX_THRESH_STAT */
+#define CPSW_WR_C0_RX_THRESH_STAT_C0_RX_THRESH_STAT   (0x000000FFu)
+#define CPSW_WR_C0_RX_THRESH_STAT_C0_RX_THRESH_STAT_SHIFT   (0x00000000u)
+
+
+/* C0_RX_STAT */
+#define CPSW_WR_C0_RX_STAT_C0_RX_STAT   (0x000000FFu)
+#define CPSW_WR_C0_RX_STAT_C0_RX_STAT_SHIFT   (0x00000000u)
+
+
+/* C0_TX_STAT */
+#define CPSW_WR_C0_TX_STAT_C0_TX_STAT   (0x000000FFu)
+#define CPSW_WR_C0_TX_STAT_C0_TX_STAT_SHIFT   (0x00000000u)
+
+
+/* C0_MISC_STAT */
+#define CPSW_WR_C0_MISC_STAT_C0_MISC_STAT   (0x0000001Fu)
+#define CPSW_WR_C0_MISC_STAT_C0_MISC_STAT_SHIFT   (0x00000000u)
+
+
+/* C1_RX_THRESH_STAT */
+#define CPSW_WR_C1_RX_THRESH_STAT_C1_RX_THRESH_STAT   (0x000000FFu)
+#define CPSW_WR_C1_RX_THRESH_STAT_C1_RX_THRESH_STAT_SHIFT   (0x00000000u)
+
+
+/* C1_RX_STAT */
+#define CPSW_WR_C1_RX_STAT_C1_RX_STAT   (0x000000FFu)
+#define CPSW_WR_C1_RX_STAT_C1_RX_STAT_SHIFT   (0x00000000u)
+
+
+/* C1_TX_STAT */
+#define CPSW_WR_C1_TX_STAT_C1_TX_STAT   (0x000000FFu)
+#define CPSW_WR_C1_TX_STAT_C1_TX_STAT_SHIFT   (0x00000000u)
+
+
+/* C1_MISC_STAT */
+#define CPSW_WR_C1_MISC_STAT_C1_MISC_STAT   (0x0000001Fu)
+#define CPSW_WR_C1_MISC_STAT_C1_MISC_STAT_SHIFT   (0x00000000u)
+
+
+/* C2_RX_THRESH_STAT */
+#define CPSW_WR_C2_RX_THRESH_STAT_C2_RX_THRESH_STAT   (0x000000FFu)
+#define CPSW_WR_C2_RX_THRESH_STAT_C2_RX_THRESH_STAT_SHIFT   (0x00000000u)
+
+
+/* C2_RX_STAT */
+#define CPSW_WR_C2_RX_STAT_C2_RX_STAT   (0x000000FFu)
+#define CPSW_WR_C2_RX_STAT_C2_RX_STAT_SHIFT   (0x00000000u)
+
+
+/* C2_TX_STAT */
+#define CPSW_WR_C2_TX_STAT_C2_TX_STAT   (0x000000FFu)
+#define CPSW_WR_C2_TX_STAT_C2_TX_STAT_SHIFT   (0x00000000u)
+
+
+/* C2_MISC_STAT */
+#define CPSW_WR_C2_MISC_STAT_C2_MISC_STAT   (0x0000001Fu)
+#define CPSW_WR_C2_MISC_STAT_C2_MISC_STAT_SHIFT   (0x00000000u)
+
+
+/* C0_RX_IMAX */
+#define CPSW_WR_C0_RX_IMAX_C0_RX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C0_RX_IMAX_C0_RX_IMAX_SHIFT   (0x00000000u)
+
+
+/* C0_TX_IMAX */
+#define CPSW_WR_C0_TX_IMAX_C0_TX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C0_TX_IMAX_C0_TX_IMAX_SHIFT   (0x00000000u)
+
+
+/* C1_RX_IMAX */
+#define CPSW_WR_C1_RX_IMAX_C1_RX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C1_RX_IMAX_C1_RX_IMAX_SHIFT   (0x00000000u)
+
+
+/* C1_TX_IMAX */
+#define CPSW_WR_C1_TX_IMAX_C1_TX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C1_TX_IMAX_C1_TX_IMAX_SHIFT   (0x00000000u)
+
+
+/* C2_RX_IMAX */
+#define CPSW_WR_C2_RX_IMAX_C2_RX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C2_RX_IMAX_C2_RX_IMAX_SHIFT   (0x00000000u)
+
+
+/* C2_TX_IMAX */
+#define CPSW_WR_C2_TX_IMAX_C2_TX_IMAX   (0x0000003Fu)
+#define CPSW_WR_C2_TX_IMAX_C2_TX_IMAX_SHIFT   (0x00000000u)
+
+
+/* RGMII_CTL */
+#define CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX   (0x00000008u)
+#define CPSW_WR_RGMII_CTL_RGMII1_FULLDUPLEX_SHIFT   (0x00000003u)
+
+#define CPSW_WR_RGMII_CTL_RGMII1_LINK   (0x00000001u)
+#define CPSW_WR_RGMII_CTL_RGMII1_LINK_SHIFT   (0x00000000u)
+
+#define CPSW_WR_RGMII_CTL_RGMII1_SPEED   (0x00000006u)
+#define CPSW_WR_RGMII_CTL_RGMII1_SPEED_SHIFT   (0x00000001u)
+
+#define CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX   (0x00000080u)
+#define CPSW_WR_RGMII_CTL_RGMII2_FULLDUPLEX_SHIFT   (0x00000007u)
+
+#define CPSW_WR_RGMII_CTL_RGMII2_LINK   (0x00000010u)
+#define CPSW_WR_RGMII_CTL_RGMII2_LINK_SHIFT   (0x00000004u)
+
+#define CPSW_WR_RGMII_CTL_RGMII2_SPEED   (0x00000060u)
+#define CPSW_WR_RGMII_CTL_RGMII2_SPEED_SHIFT   (0x00000005u)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_mdio.h b/cpsw/src/include/hw_mdio.h
new file mode 100755
index 0000000..1372a1d
--- /dev/null
+++ b/cpsw/src/include/hw_mdio.h
@@ -0,0 +1,257 @@
+/**
+ * \file  hw_mdio.h
+ *
+ * \brief MDIO register definitions
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_MDIO_H_
+#define _HW_MDIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MDIO_REVID		(0x0)
+#define MDIO_CONTROL		(0x4)
+#define MDIO_ALIVE		(0x8)
+#define MDIO_LINK		(0xC)
+#define MDIO_LINKINTRAW		(0x10)
+#define MDIO_LINKINTMASKED	(0x14)
+#define MDIO_USERINTRAW		(0x20)
+#define MDIO_USERINTMASKED	(0x24)
+#define MDIO_USERINTMASKSET	(0x28)
+#define MDIO_USERINTMASKCLEAR	(0x2C)
+#define MDIO_USERACCESS0	(0x80)
+#define MDIO_USERPHYSEL0	(0x84)
+#define MDIO_USERACCESS1	(0x88)
+#define MDIO_USERPHYSEL1	(0x8C)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define MDIO_REVID_REV (0xFFFFFFFFu)
+#define MDIO_REVID_REV_SHIFT (0x00000000u)
+
+
+/* CONTROL */
+
+#define MDIO_CONTROL_IDLE (0x80000000u)
+#define MDIO_CONTROL_IDLE_SHIFT (0x0000001Fu)
+/*----IDLE Tokens----*/
+#define MDIO_CONTROL_IDLE_NO (0x00000000u)
+#define MDIO_CONTROL_IDLE_YES (0x00000001u)
+
+#define MDIO_CONTROL_ENABLE (0x40000000u)
+#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001Eu)
+
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000u)
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018u)
+
+
+#define MDIO_CONTROL_PREAMBLE (0x00100000u)
+#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014u)
+/*----PREAMBLE Tokens----*/
+
+#define MDIO_CONTROL_FAULT (0x00080000u)
+#define MDIO_CONTROL_FAULT_SHIFT (0x00000013u)
+
+#define MDIO_CONTROL_FAULTENB (0x00040000u)
+#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012u)
+/*----FAULTENB Tokens----*/
+
+
+
+#define MDIO_CONTROL_CLKDIV (0x0000FFFFu)
+#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000u)
+/*----CLKDIV Tokens----*/
+
+
+/* ALIVE */
+
+#define MDIO_ALIVE_REGVAL (0xFFFFFFFFu)
+#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000u)
+
+
+/* LINK */
+
+#define MDIO_LINK_REGVAL (0xFFFFFFFFu)
+#define MDIO_LINK_REGVAL_SHIFT (0x00000000u)
+
+
+/* LINKINTRAW */
+
+
+#define MDIO_LINKINTRAW_USERPHY1 (0x00000002u)
+#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001u)
+
+#define MDIO_LINKINTRAW_USERPHY0 (0x00000001u)
+#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000u)
+
+
+/* LINKINTMASKED */
+
+
+#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002u)
+#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001u)
+
+#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001u)
+#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000u)
+
+
+/* USERINTRAW */
+
+
+#define MDIO_USERINTRAW_USERACCESS1 (0x00000002u)
+#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001u)
+
+#define MDIO_USERINTRAW_USERACCESS0 (0x00000001u)
+#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000u)
+
+
+/* USERINTMASKED */
+
+
+#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002u)
+#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001u)
+
+#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001u)
+#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000u)
+
+
+/* USERINTMASKSET */
+
+
+#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002u)
+#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001u)
+
+#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001u)
+#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000u)
+
+
+/* USERINTMASKCLEAR */
+
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002u)
+#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001u)
+
+#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001u)
+#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000u)
+
+
+/* USERACCESS0 */
+
+#define MDIO_USERACCESS0_GO (0x80000000u)
+#define MDIO_USERACCESS0_GO_SHIFT (0x0000001Fu)
+
+#define MDIO_USERACCESS0_WRITE (0x40000000u)
+#define MDIO_USERACCESS0_READ  (0x00000000u)
+#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001Eu)
+
+#define MDIO_USERACCESS0_ACK (0x20000000u)
+#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001Du)
+
+
+#define MDIO_USERACCESS0_REGADR (0x03E00000u)
+#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015u)
+
+#define MDIO_USERACCESS0_PHYADR (0x001F0000u)
+#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010u)
+
+#define MDIO_USERACCESS0_DATA (0x0000FFFFu)
+#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000u)
+
+
+/* USERPHYSEL0 */
+
+
+#define MDIO_USERPHYSEL0_LINKSEL (0x00000080u)
+#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007u)
+
+#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040u)
+#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006u)
+
+
+#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001Fu)
+#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000u)
+
+
+/* USERACCESS1 */
+
+#define MDIO_USERACCESS1_GO (0x80000000u)
+#define MDIO_USERACCESS1_GO_SHIFT (0x0000001Fu)
+
+#define MDIO_USERACCESS1_WRITE (0x40000000u)
+#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001Eu)
+
+#define MDIO_USERACCESS1_ACK (0x20000000u)
+#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001Du)
+
+
+#define MDIO_USERACCESS1_REGADR (0x03E00000u)
+#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015u)
+
+#define MDIO_USERACCESS1_PHYADR (0x001F0000u)
+#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010u)
+
+#define MDIO_USERACCESS1_DATA (0x0000FFFFu)
+#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000u)
+
+
+/* USERPHYSEL1 */
+
+
+#define MDIO_USERPHYSEL1_LINKSEL (0x00000080u)
+#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007u)
+
+#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040u)
+#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006u)
+
+
+#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001Fu)
+#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000u)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cpsw/src/include/hw_types.h b/cpsw/src/include/hw_types.h
new file mode 100755
index 0000000..f4ba2e5
--- /dev/null
+++ b/cpsw/src/include/hw_types.h
@@ -0,0 +1,87 @@
+/**
+ * \file  hw_types.h
+ *
+ * \brief Common type definitions and macros
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_TYPES_H_
+#define _HW_TYPES_H_
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x)                                                              \
+        (*((volatile unsigned int *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile unsigned short *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((unsigned int)(x) & 0xF0000000) | 0x02000000 |                \
+              (((unsigned int)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((unsigned int)(x) & 0xF0000000) | 0x02000000 |               \
+               (((unsigned int)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((unsigned int)(x) & 0xF0000000) | 0x02000000 |               \
+               (((unsigned int)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+#define TRUE    1
+#define FALSE   0
+
+#endif // __HW_TYPES_H__
diff --git a/cpsw/src/include/locator.h b/cpsw/src/include/locator.h
new file mode 100755
index 0000000..388bf8e
--- /dev/null
+++ b/cpsw/src/include/locator.h
@@ -0,0 +1,50 @@
+/*

+ * locator.h

+ *

+ * declarations for locator services for ethernet. 

+ *

+*/

+/*

+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without modification,

+ * are permitted provided that the following conditions are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright notice,

+ *    this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright notice,

+ *    this list of conditions and the following disclaimer in the documentation

+ *    and/or other materials provided with the distribution.

+ * 3. The name of the author may not be used to endorse or promote products

+ *    derived from this software without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED

+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT

+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT

+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING

+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY

+ * OF SUCH DAMAGE.

+ *

+ * This file is part of the lwIP TCP/IP stack.

+ *

+ * Author: Adam Dunkels <adam@sics.se>

+ *

+*/

+

+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/

+ * ALL RIGHTS RESERVED

+ */

+#ifndef __LOCATOR_H__

+#define __LOCATOR_H__

+

+/******************************************************************************

+**                      EXTERNAL FUNCTION PROTOTYPES

+*******************************************************************************/

+extern void LocatorConfig(unsigned char *macArray, const char *appTitle);

+

+#endif // __LOCATOR_H__

diff --git a/cpsw/src/include/lwip_bbb.h b/cpsw/src/include/lwip_bbb.h
new file mode 100644
index 0000000..c7624b5
--- /dev/null
+++ b/cpsw/src/include/lwip_bbb.h
@@ -0,0 +1,51 @@
+#ifndef __LWIP_BBB_H__
+#define __LWIP_BBB_H__
+
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef LEN_MAC_ADDRESS
+#define LEN_MAC_ADDRESS                    (6)
+#endif
+
+/**
+ * @brief The possible IP modes, Static, DHCP or AutoIP
+ * For use in the lwipIf struct.
+ */
+typedef enum IPMode
+{
+    IPADDR_USE_STATIC,
+    IPADDR_USE_DHCP,
+    IPADDR_USE_AUTOIP 
+} IPMode;
+
+/**
+ * @brief Used to pass the addresses for the LWIP
+ * initialization routines(Ip address, NetMask, GW, mode and MAC).
+ * 
+ */
+typedef struct lwipIf
+{
+    ip4_addr_t ipAddr; /* IP Address */
+    ip4_addr_t netMask; /* Net Mask */
+    ip4_addr_t gwAddr; /* Gate Way Address */
+    IPMode ipMode; /* IP Address mode*/
+    unsigned char macArray[LEN_MAC_ADDRESS]; /* MAC Address to be used*/
+}LWIP_IF;
+
+/**
+ * @brief Starts the Lwip stack and initializes low level devices.
+ * 
+ * @param ipConf The desired addresses and/or modes.
+ * @return True if everything went fine, false otherwise.
+ */
+bool startLwip(LWIP_IF* ipConf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __LWIP_BBB_H__
diff --git a/cpsw/src/include/lwiplib.h b/cpsw/src/include/lwiplib.h
new file mode 100755
index 0000000..f400d62
--- /dev/null
+++ b/cpsw/src/include/lwiplib.h
@@ -0,0 +1,255 @@
+/**
+*  \file lwiplib.h
+*
+*  \brief lwip abstraction layer related declarations
+*/
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+*/
+
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * ALL RIGHTS RESERVED
+ */
+#ifndef __LWIPLIB_H__
+#define __LWIPLIB_H__
+
+#include "lwip_bbb.h"
+#include "lwip/opt.h"
+
+/* Ensure that AUTOIP COOP option is configured correctly.*/
+#undef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP   ((LWIP_DHCP) && (LWIP_AUTOIP))
+
+#include "lwip/api.h"
+#include "lwip/netifapi.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+#include "lwip/sockets.h"
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+
+#define CPSW_DUAL_MAC_MODE
+
+/******************************************************************************
+**                            Macro Definitions
+******************************************************************************/
+#define MAX_ALE_ENTRIES                    (1024)
+#define ALE_ENTRY_NUM_WORDS                (3)
+
+#define ERR_PASS                           (0)
+#define ERR_FAIL                           (-1)
+#define ERR_INVAL                          (-2)
+
+#define MIN_SLV_PORT                       (1)
+#define MIN_AUTONEG                        (0)
+#define MIN_PHY_CONFIG                     (1)
+#define MIN_SPEED                          (0)
+#define MIN_DUPLEX                         (0)
+
+#define MAX_SLV_PORT                       (2)
+#define MAX_AUTONEG                        (1)
+#define MAX_PHY_CONFIG                     (0x3F)
+#define MAX_SPEED                          (2)
+#define MAX_DUPLEX                         (1)
+
+#define ERR_SLV_PORT                       (-25)
+#define ERR_AUTONEG                        (-26)
+#define ERR_PHY_CONFIG                     (-27)
+#define ERR_SPEED                          (-28)
+#define ERR_DUPLEX                         (-29)
+
+#ifdef CPSW_SWITCH_CONFIG
+#define MIN_VLANAWARE                      (0)
+#define MIN_ALE_VLANAWARE                  (0)
+#define MIN_ALE_ENTRY_IDX                  (0)
+#define MIN_VLAN_UNTAG                     (0)
+#define MIN_VLAN_MCAST_UNREG               (0)
+#define MIN_VLAN_MCAST_REG                 (0)
+#define MIN_MCAST_FWD_STATE                (0)
+#define MIN_SUPER                          (0)
+#define MIN_PORT_MASK                      (0)
+#define MIN_UCAST_FLAGS                    (0)
+#define MIN_PORT                           (0)
+#define MIN_VLANID                         (0)
+#define MIN_CFI                            (0)
+#define MIN_PRI                            (0)
+#define MIN_UNKNOWN_VLAN_TYPE              (1)
+#define MIN_PORT_STATE                     (0)
+#define MIN_ADDR_TYPE                      (1)
+#define MIN_ENABLE                         (0)
+#define MIN_DIRECTION                      (0)
+#define MIN_LIMIT                          (0)
+#define MIN_UNKNOWN_VLAN                   (1)
+#define MIN_MAC_AUTH                       (0)
+
+#define MAX_VLANAWARE                      (1)
+#define MAX_ALE_VLANAWARE                  (1)
+#define MAX_ALE_ENTRY_IDX                  (1023)
+#define MAX_VLAN_UNTAG                     (7)
+#define MAX_VLAN_MCAST_UNREG               (7)
+#define MAX_VLAN_MCAST_REG                 (7)
+#define MAX_MCAST_FWD_STATE                (3)
+#define MAX_SUPER                          (1)
+#define MAX_PORT_MASK                      (7)
+#define MAX_UCAST_FLAGS                    (3)
+#define MAX_PORT                           (2)
+#define MAX_VLANID                         (4095)
+#define MAX_CFI                            (1)
+#define MAX_PRI                            (7)
+#define MAX_UNKNOWN_VLAN_TYPE              (4)
+#define MAX_PORT_STATE                     (3)
+#define MAX_ADDR_TYPE                      (3)
+#define MAX_ENABLE                         (1)
+#define MAX_DIRECTION                      (1)
+#define MAX_LIMIT                          (255)
+#define MAX_UNKNOWN_VLAN                   (4)
+#define MAX_MAC_AUTH                       (1)
+
+#define ERR_ADDR                           (-3)
+#define ERR_VLANID                         (-4)
+#define ERR_PORT_MASK                      (-5)
+#define ERR_SUPER                          (-6)
+#define ERR_MCAST_FWD_STATE                (-7)
+#define ERR_PORT                           (-8)
+#define ERR_UCAST_FLAGS                    (-9)
+#define ERR_VLAN_MCAST_REG                 (-10)
+#define ERR_VLAN_MCAST_UNREG               (-11)
+#define ERR_VLAN_MCAST_UNTAG               (-12)
+#define ERR_ALE_ENTRY_IDX                  (-13)
+#define ERR_VLANAWARE                      (-14)
+#define ERR_ALE_VLANAWARE                  (-15)
+#define ERR_CFI                            (-16)
+#define ERR_PRI                            (-17)
+#define ERR_ENABLE                         (-18)
+#define ERR_DIRECTION                      (-19)
+#define ERR_LIMIT                          (-20)
+#define ERR_UNKNOWN_VLAN                   (-21)
+#define ERR_MAC_AUTH                       (-22)
+#define ERR_ADDR_TYPE                      (-23)
+#define ERR_PORT_STATE                     (-24)
+#endif
+
+#ifdef CPSW_SWITCH_CONFIG
+enum {
+  ADDR_TYPE_BROADCAST = 1,
+  ADDR_TYPE_MULTICAST,
+  ADDR_TYPE_UNICAST,
+};
+
+enum {
+  ALE_PORT_UNTAGGED_EGRESS = 1,
+  ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
+  ALE_PORT_UNKNOWN_UNREG_MCAST_FLOOD,
+  ALE_PORT_UNKNOWN_VLAN_MEMBER,
+};
+#endif
+
+enum {
+  CONFIG_SWITCH_INVALID = 0,
+#ifdef CPSW_SWITCH_CONFIG
+  CONFIG_SWITCH_ADD_MULTICAST,
+  CONFIG_SWITCH_ADD_UNICAST,
+  CONFIG_SWITCH_ADD_OUI,
+  CONFIG_SWITCH_FIND_ADDR,
+  CONFIG_SWITCH_DEL_MULTICAST,
+  CONFIG_SWITCH_DEL_UNICAST,
+  CONFIG_SWITCH_ADD_VLAN,
+  CONFIG_SWITCH_FIND_VLAN,
+  CONFIG_SWITCH_DEL_VLAN,
+  CONFIG_SWITCH_PORT_VLAN_CONFIG,
+  CONFIG_SWITCH_AGEOUT,
+  CONFIG_SWITCH_DUMP,
+  CONFIG_SWITCH_CONFIG_DUMP,
+  CONFIG_SWITCH_VLANAWARE,
+  CONFIG_SWITCH_RATELIMIT,
+  CONFIG_SWITCH_VID_INGRESS_CHECK,
+  CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO,
+  CONFIG_SWITCH_MACAUTH,
+  CONFIG_SWITCH_PORT_STATE,
+#endif
+  CONFIG_SWITCH_SET_PORT_CONFIG,
+};
+
+#ifdef CPSW_SWITCH_CONFIG
+typedef struct cpsw_switch_param {
+  u32_t  port_num;
+  u32_t  port_mask;
+  u32_t  vid;        /* VLAN identifier */
+  u32_t  prio_port;  /* port priority 0 -7 */
+  u32_t  cfi_port;   /* port CFI  0 /1 */
+  u32_t  unreg_multi;    /* unreg multicast Egress Ports */
+  u32_t  reg_multi;  /* register multicast Egress ports */
+  u32_t  untag_port; /* Untag ports */
+  u8_t  addr[LEN_MAC_ADDRESS]; /* Ethernet Address */
+  u32_t  super;
+  u32_t  fwd_state;
+  u32_t  ucast_flags;
+  u32_t  ucast_type;
+  u32_t  blocked;
+  u32_t  secure;
+  u32_t  ageable;
+  u32_t  ale_tbl_index;    /* if 1 print ale table */
+  u32_t  vlan_aware;
+  u32_t  drop_packet;
+  u32_t  direction;  /* Tx -1 / Rx - 0 */
+  u32_t  addr_type;  /* Address type BroadMulti/Uni cast */
+  u32_t  limit;      /* multicast/broadcast limit */
+  u32_t  vlan_ingress_check;
+  u32_t  port_state;
+  u32_t  drop_untagged;
+  u32_t  enable;     /* 1-enable/0-Disable */
+  u32_t  unknown_vlan;
+  u32_t  mac_auth;
+}CPSW_SW_PARAM_IF;
+#endif
+
+typedef struct cpsw_phy_param {
+  u32_t  slv_port_num;
+  u32_t  autoneg;
+  u32_t  config;
+  u32_t  speed;
+  u32_t  duplex;
+}CPSW_PHY_PARAM_IF;
+
+typedef struct cpsw_config {
+  u32_t cmd;   /* API to be invoked by the kernel driver */
+  u32_t cpsw_inst;
+  struct cpsw_phy_param *phy_param;
+#ifdef CPSW_SWITCH_CONFIG
+  struct cpsw_switch_param *switch_param;
+  u32_t  buf[MAX_ALE_ENTRIES][ALE_ENTRY_NUM_WORDS]; /* Buffer for Ale Dump */
+  u32_t  ale_entry[ALE_ENTRY_NUM_WORDS];
+#endif
+  s32_t ret;   /* Return  Success/Failure */
+}CPSW_CONF_IF;
+
+#endif /* __LWIPLIB_H__ */
diff --git a/cpsw/src/include/mdio.h b/cpsw/src/include/mdio.h
new file mode 100755
index 0000000..7b3c64c
--- /dev/null
+++ b/cpsw/src/include/mdio.h
@@ -0,0 +1,75 @@
+/**
+ *  \file   mdio.h
+ *
+ *  \brief  MDIO APIs and macros.
+ *
+ *   This file contains the driver API prototypes and macro definitions.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __MDIO_H__
+#define __MDIO_H__
+
+#include "hw_mdio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*****************************************************************************/
+/*
+** Structure to save CPSW context
+*/
+typedef struct mdioContext {
+    unsigned int mdioCtrl;
+}MDIOCONTEXT;
+
+/*
+** Prototypes for the APIs
+*/
+extern unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr);
+extern unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr);
+extern void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
+                     unsigned int mdioOutputFreq);
+extern unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
+                                   unsigned int regNum, volatile unsigned short *dataPtr);
+extern void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
+                            unsigned int regNum, unsigned short RegVal);
+extern void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
+extern void MDIOContextRestore(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MDIO_H__ */
diff --git a/cpsw/src/include/mmu.h b/cpsw/src/include/mmu.h
new file mode 100755
index 0000000..a796168
--- /dev/null
+++ b/cpsw/src/include/mmu.h
@@ -0,0 +1,195 @@
+/**
+ *  \file   mmu.h
+ *
+ *  \brief  MMU configuration API prototypes
+ *
+ *  This file contains the API prototypes and structure definitions
+ *  for configuring ARMv7a MMU.
+*/
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef __MMU_H
+#define __MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** Number of entries in a page table. This is only for first level page table
+*/
+#define MMU_PAGETABLE_NUM_ENTRY                  (4096)
+
+/*
+** Alignment for Page Table. The Page Table shall be aligned to 16KB boundary.
+*/
+#define MMU_PAGETABLE_ALIGN_SIZE                 (16 * 1024)
+
+/*****************************************************************************/
+/*
+** Page Type for a region. To be assigned to 'pgType' field of a REGION
+** structure.
+** Eg: region.pgType = MMU_PGTYPE_SECTION
+*/
+/* To configure as a section. Section Size is 1MB */
+#define MMU_PGTYPE_SECTION                       (0xFFF04002)
+
+/* To configure as a super section. Super Section Size is 16MB */
+#define MMU_PGTYPE_SUPERSECTION                  (0xFF040002)
+
+/*****************************************************************************/
+/*
+** Access Control for a section, to be assigned to 'memAttrib' field
+** of a REGION structure.
+** Eg: region1.memAttrib = MMU_MEMTYPE_DEVICE_SHAREABLE;
+**     region2.memAttrib = MMU_MEMTYPE_NORMAL_SHAREABLE(MMU_CACHE_WB_WA,
+**                                                      MMU_CACHE_WT_NOWA)
+*/
+/* Strongly Ordered memory - always shareable */
+#define MMU_MEMTYPE_STRONG_ORD_SHAREABLE         (0x00000000)
+
+/* Shareable Device memory */
+#define MMU_MEMTYPE_DEVICE_SHAREABLE             (0x00000004)
+
+/* Non-Shareable Device memory */
+#define MMU_MEMTYPE_DEVICE_NON_SHAREABLE         (0x00002000)
+
+/*
+** Non-Shareable Normal memory. Cache Policies are given as parameters.
+** Eg : MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WB_WA, MMU_CACHE_WT_NOWA)
+*/
+#define MMU_MEMTYPE_NORMAL_NON_SHAREABLE(innerCachePol, outerCachePol)   \
+                                               (0x00004000               \
+                                                | (outerCachePol << 12)  \
+                                                | (innerCachePol << 2))
+
+/*
+** Shareable Normal memory. Cache Policies are given as parameters.
+** Eg : MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WB_WA, MMU_CACHE_WT_NOWA)
+*/
+#define MMU_MEMTYPE_NORMAL_SHAREABLE(innerCachePol, outerCachePol)       \
+                                               (0x00014000               \
+                                                | (outerCachePol << 12)  \
+                                                | (innerCachePol << 2))
+
+/*
+** Definitions for the parameters 'innerCachePol' & 'outerCachePol' to set
+** cache policies for Normal Memory to MMU_MEMTYPE_NORMAL_* macros
+*/
+/* Non Cacheable Memory */
+#define MMU_NON_CACHEABLE                        (0x00)
+
+/* Write Back, Write Allocate */
+#define MMU_CACHE_WB_WA                          (0x01)
+
+/* Write Through, No Write Allocate */
+#define MMU_CACHE_WT_NOWA                        (0x02)
+
+/* Write Back, No Write Allocate */
+#define MMU_CACHE_WB_NOWA                        (0x03)
+
+/*****************************************************************************/
+/*
+** Access Control for a section, to be assigned to 'secureType' field
+** of a REGION structure
+*/
+/* Secure physical address space is accessed */
+#define MMU_REGION_SECURE                        (0x00000000)
+
+/* Non-secure physical address space is accessed */
+#define MMU_REGION_NON_SECURE                    (0x00080000)
+
+/*****************************************************************************/
+/*
+** Access Control for a section, to be assigned to 'accsCtrl' field
+** of a REGION structure
+** region.accsCtrl = MMU_AP_PRV_RW_USR_RW;
+**
+** If the section is read sensitive, MMU_SECTION_EXEC_NEVER macro can be used
+** OR'ed with Acess Permissions.
+** region.accsCtrl = MMU_AP_PRV_RW_USR_NA | MMU_SECTION_EXEC_NEVER;
+*/
+/*
+** Macros for Access Permissions in both privilege modes
+*/
+/* Both Privileged and User Permission- No Access*/
+#define MMU_AP_PRV_NA_USR_NA                     (0x0000)
+
+/* Privileged Permission - Read/Write, User Permission- No Access*/
+#define MMU_AP_PRV_RW_USR_NA                     (0x0400)
+
+/* Privileged Permission - Read/Write, User Permission- Read Only */
+#define MMU_AP_PRV_RW_USR_RO                     (0x0800)
+
+/* Both Privileged Permission and User  Permission - Read/Write*/
+#define MMU_AP_PRV_RW_USR_RW                     (0x0C00)
+
+/* Privileged Permission - Read Only, User  Permission- No Access*/
+#define MMU_AP_PRV_RO_USR_NA                     (0x8400)
+
+/*
+** Macro to be used if the section is not to be executed and is
+** read sensitive.
+*/
+#define MMU_SECTION_EXEC_NEVER                   (0x00000010)
+
+/*****************************************************************************/
+/*
+** Structure for defining memory regions. 
+** Assumed Virtual Address = Physical Address.
+*/
+typedef struct region {
+    unsigned int pgType; /* Type of the Page (Section/ Super Section)*/
+    unsigned int startAddr; /* Start Address of the page */
+    unsigned int numPages;  /* Number of Pages in the region */
+    unsigned int memAttrib; /* Memory Type and Cache Settings */
+    unsigned int secureType; /* Security Type */
+    unsigned int accsCtrl; /* Access Permissions for the page */
+    unsigned int *masterPtPtr; /* Pointer to the Master Page table */
+} REGION;
+
+/****************************************************************************/
+/*
+** API prototypes for configuring ARMv7a MMU.
+*/
+extern void MMUInit(unsigned int *masterPt);
+extern void MMUMemRegionMap(REGION *region);
+extern void MMUEnable(unsigned int *masterPt);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MMU_H__ */
diff --git a/cpsw/src/include/netif/FILES b/cpsw/src/include/netif/FILES
new file mode 100755
index 0000000..2b75a5c
--- /dev/null
+++ b/cpsw/src/include/netif/FILES
@@ -0,0 +1,2 @@
+cpswif.h   - public prototypes for CPSW ethernet interface driver
+
diff --git a/cpsw/src/include/netif/cpswif.h b/cpsw/src/include/netif/cpswif.h
new file mode 100755
index 0000000..0197d52
--- /dev/null
+++ b/cpsw/src/include/netif/cpswif.h
@@ -0,0 +1,115 @@
+/**
+ * @file - cpswif.h
+ * Prototypes for CPSW Ethernet interface.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/*
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ *
+ */
+#include "lwip/netif.h"
+
+#ifndef __CPSWIF_H__
+#define __CPSWIF_H__
+
+/***************************************************************************/
+/*
+ * Configurations for AM335x
+ */
+#define am335x
+#define beaglebone
+
+#ifdef am335x
+#include "soc_AM335x.h"
+
+#define MAX_CPSW_INST                   1
+#define CPSW0_SS_REGS                   SOC_CPSW_SS_REGS
+#define CPSW0_MDIO_REGS                 SOC_CPSW_MDIO_REGS
+#define CPSW0_WR_REGS                   SOC_CPSW_WR_REGS
+#define CPSW0_CPDMA_REGS                SOC_CPSW_CPDMA_REGS
+#define CPSW0_ALE_REGS                  SOC_CPSW_ALE_REGS
+#define CPSW0_CPPI_RAM_REGS             SOC_CPSW_CPPI_RAM_REGS
+#define CPSW0_PORT_0_REGS               SOC_CPSW_PORT_0_REGS
+#define CPSW0_PORT_1_REGS               SOC_CPSW_PORT_1_REGS
+#define CPSW0_SLIVER_1_REGS             SOC_CPSW_SLIVER_1_REGS
+#define CPSW0_PORT_2_REGS               SOC_CPSW_PORT_2_REGS
+#define CPSW0_SLIVER_2_REGS             SOC_CPSW_SLIVER_2_REGS
+
+#ifdef evmAM335x
+#define CPSW0_PORT_1_PHY_ADDR           0
+#define CPSW0_PORT_1_PHY_GIGABIT        TRUE
+
+#elif defined(beaglebone)
+#define CPSW0_PORT_1_PHY_ADDR           0
+#define CPSW0_PORT_1_PHY_GIGABIT        FALSE
+
+#elif defined(evmskAM335x)
+#define CPSW0_PORT_1_PHY_ADDR           0
+#define CPSW0_PORT_2_PHY_ADDR           1
+#define CPSW0_PORT_1_PHY_GIGABIT        TRUE
+#define CPSW0_PORT_2_PHY_GIGABIT        TRUE
+#endif
+
+//#include "consoleUtils.h"
+#define LWIP_PRINTF                     printk
+
+#else
+#error Unsupported EVM !!!
+#endif
+
+#define MAX_SLAVEPORT_PER_INST          2
+
+/*****************************************************************************/
+/**
+ * Helper struct to hold private data used to operate the ethernet interface.
+ */
+typedef struct cpswportif{
+  /* CPSW instance number */
+  u32_t inst_num;
+
+  /* CPSW port number */
+  u32_t port_num;
+
+  u8_t eth_addr[6];
+}cpswportif;
+
+extern u32_t cpswif_netif_status(struct netif *netif);
+extern u32_t cpswif_link_status(u32_t inst_num, u32_t slv_port_num);
+extern err_t cpswif_init(struct netif *netif);
+extern void cpswif_rx_inthandler(u32_t inst_num);
+extern void cpswif_tx_inthandler(u32_t inst_num);
+
+#endif /* _CPSWIF_H__ */
diff --git a/cpsw/src/include/phy.h b/cpsw/src/include/phy.h
new file mode 100755
index 0000000..26292bb
--- /dev/null
+++ b/cpsw/src/include/phy.h
@@ -0,0 +1,151 @@
+/**
+ * \file  phy.h
+ *
+ * \brief Macros and function definitions for EMAC PHY 
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _PHY_H_
+#define _PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* PHY register offset definitions */
+#define PHY_BCR                           (0u)
+#define PHY_BSR                           (1u)
+#define PHY_ID1                           (2u)
+#define PHY_ID2                           (3u)
+#define PHY_AUTONEG_ADV                   (4u)
+#define PHY_LINK_PARTNER_ABLTY            (5u)
+#define PHY_1000BT_CONTROL                (9u)
+#define PHY_1000BT_STATUS                 (0x0A)
+
+/* PHY status definitions */
+#define PHY_ID_SHIFT                      (16u)
+#define PHY_SOFTRESET                     (0x8000)
+#define PHY_AUTONEG_ENABLE                (0x1000u)
+#define PHY_AUTONEG_RESTART               (0x0200u)
+#define PHY_AUTONEG_COMPLETE              (0x0020u)
+#define PHY_AUTONEG_INCOMPLETE            (0x0000u)
+#define PHY_AUTONEG_STATUS                (0x0020u)
+#define PHY_AUTONEG_ABLE                  (0x0008u)
+#define PHY_LPBK_ENABLE                   (0x4000u)
+#define PHY_LINK_STATUS                   (0x0004u)
+
+/* PHY ID. The LSB nibble will vary between different phy revisions */
+#define PHY_ID_REV_MASK                   (0x0000000Fu)
+
+/* Pause operations */
+#define PHY_PAUSE_NIL                     (0x0000u)
+#define PHY_PAUSE_SYM                     (0x0400u)
+#define PHY_PAUSE_ASYM                    (0x0800u)
+#define PHY_PAUSE_BOTH_SYM_ASYM           (0x0C00u)
+
+/* 1000 Base-T capabilities */
+#define PHY_NO_1000BT                     (0x0000u)
+#define PHY_1000BT_HD                     (0x0100u)
+#define PHY_1000BT_FD                     (0x0200u)
+
+/* 100 Base TX Full Duplex capablity */
+#define PHY_100BTX_HD                     (0x0000u)
+#define PHY_100BTX_FD                     (0x0100u)
+
+/* 100 Base TX capability */
+#define PHY_NO_100BTX                     (0x0000u)
+#define PHY_100BTX                        (0x0080u)
+
+/* 10 BaseT duplex capabilities */
+#define PHY_10BT_HD                       (0x0000u)
+#define PHY_10BT_FD                       (0x0040u)
+
+/* 10 BaseT ability*/
+#define PHY_NO_10BT                       (0x0000u)
+#define PHY_10BT                          (0x0020u)
+
+#define PHY_LINK_PARTNER_1000BT_FD        (0x0800u)
+#define PHY_LINK_PARTNER_1000BT_HD        (0x0400u)
+
+/* Speed settings for BCR register */
+#define PHY_SPEED_MASK                    (0xDFBF)
+#define PHY_SPEED_10MBPS                  (0x0000u)
+#define PHY_SPEED_100MBPS                 (0x2000u)
+#define PHY_SPEED_1000MBPS                (0x0040)
+
+/* Duplex settings for BCR register */
+#define PHY_FULL_DUPLEX                   (0x0100)
+
+/**************************************************************************
+                        API function Prototypes
+**************************************************************************/
+extern unsigned int PhyIDGet(unsigned int mdioBaseAddr,
+                             unsigned int phyAddr);
+extern unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr,
+                                      unsigned int phyAddr);
+extern unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr,
+                                       unsigned int phyAddr);
+extern unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned int phyAddr);
+extern unsigned int PhyConfigure(unsigned int mdioBaseAddr,
+                                 unsigned int phyAddr,
+                                 unsigned short speed,
+                                 unsigned short duplexMode);
+extern unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr, 
+                                     unsigned int phyAddr,
+                                     unsigned short *advPtr,
+                                     unsigned short *gigAdvPtr);
+extern unsigned int PhyRegRead(unsigned int mdioBaseAddr, 
+                               unsigned int phyAddr,
+                               unsigned int regIdx, 
+                               unsigned short *regValAdr);
+extern void PhyRegWrite(unsigned int mdioBaseAddr, 
+                        unsigned int phyAddr,
+                        unsigned int regIdx, 
+                        unsigned short regVal);
+extern unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr,
+                                         unsigned int phyAddr,
+                                         unsigned short *ptnerAblty,
+                                         unsigned short *gbpsPtnerAblty);
+extern unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr,
+                                     unsigned int phyAddr,
+                                     volatile unsigned int retries);
+extern unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr, 
+                                        unsigned int phyAddr);
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/cpsw/src/include/soc_AM335x.h b/cpsw/src/include/soc_AM335x.h
new file mode 100755
index 0000000..ef8b152
--- /dev/null
+++ b/cpsw/src/include/soc_AM335x.h
@@ -0,0 +1,206 @@
+/** ============================================================================
+ *   \file  soc_AM33XX.h
+ *
+ *   \brief This file contains the peripheral information for AM33XX SoC
+ *
+ *  ============================================================================
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _SOC_AM33XX_H_
+#define _SOC_AM33XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Cache Line size in ARM Cortex-A8.                                         */
+#define SOC_CACHELINE_SIZE_MAX               (64)
+
+/** @brief Base address of AINTC memory mapped registers                      */
+#define SOC_AINTC_REGS                       (0x48200000)
+
+/** @brief Base addresses of UART memory mapped registers                     */
+#define SOC_UART_0_REGS                      (0x44E09000)
+#define SOC_UART_1_REGS                      (0x48022000)
+#define SOC_UART_2_REGS                      (0x48024000)
+#define SOC_UART_3_REGS                      (0x481A6000)
+#define SOC_UART_4_REGS                      (0x481A8000)
+#define SOC_UART_5_REGS                      (0x481AA000)
+
+/** @brief Base addresses of USB memory mapped registers                     */
+#define SOC_USB_0_BASE                       (0x47401400)
+#define SOC_USB_1_BASE                       (0x47401C00)
+/** @brief Base addresses of SPI memory mapped registers                      */
+#define SOC_SPI_0_REGS                       (0x48030000)
+#define SOC_SPI_1_REGS                       (0x481A0000)
+
+/** @brief Base addresses of GPIO memory mapped registers                     */
+#define SOC_GPIO_0_REGS                      (0x44E07000)
+#define SOC_GPIO_1_REGS                      (0x4804C000)
+#define SOC_GPIO_2_REGS                      (0x481AC000)
+#define SOC_GPIO_3_REGS                      (0x481AE000)
+
+/** @brief Base addresses of DMTIMER memory mapped registers                  */
+#define SOC_DMTIMER_0_REGS                   (0x44E05000)
+#define SOC_DMTIMER_1_REGS                   (0x44E31000)
+#define SOC_DMTIMER_2_REGS                   (0x48040000)
+#define SOC_DMTIMER_3_REGS                   (0x48042000)
+#define SOC_DMTIMER_4_REGS                   (0x48044000)
+#define SOC_DMTIMER_5_REGS                   (0x48046000)
+#define SOC_DMTIMER_6_REGS                   (0x48048000)
+#define SOC_DMTIMER_7_REGS                   (0x4804A000)
+
+/** @brief Base address of MMC memory mapped registers                        */
+#define SOC_MMCHS_0_REGS                     (0x48060000)
+#define SOC_MMCHS_1_REGS                     (0x481D8000)
+#define SOC_MMCHS_2_REGS                     (0x47810000)
+
+/** @brief Base address of GPMC memory mapped registers                       */
+#define SOC_GPMC_0_REGS                      (0x50000000)
+
+/** @brief Base address of GPMC memory mapped registers                       */
+#define SOC_ELM_0_REGS                       (0x48080000)
+
+/** @brief Base address of I2C memory mapped registers                        */
+#define SOC_I2C_0_REGS                       (0x44E0B000)
+#define SOC_I2C_1_REGS                       (0x4802A000)
+#define SOC_I2C_2_REGS                       (0x4819C000)
+
+/** @brief Base address of WDT memory mapped registers                        */
+#define SOC_WDT_0_REGS                       (0x44E33000)
+#define SOC_WDT_1_REGS                       (0x44E35000)
+
+/** @brief Base address of WDT memory mapped registers                        */
+#define SOC_CPSW_SS_REGS                     (0x4A100000)
+#define SOC_CPSW_MDIO_REGS                   (0x4A101000)
+#define SOC_CPSW_WR_REGS                     (0x4A101200)
+#define SOC_CPSW_CPDMA_REGS                  (0x4A100800)
+#define SOC_CPSW_ALE_REGS                    (0x4A100D00)
+#define SOC_CPSW_STAT_REGS                   (0x4A100900)
+#define SOC_CPSW_PORT_0_REGS                 (0x4A100100)
+#define SOC_CPSW_PORT_1_REGS                 (0x4A100200)
+#define SOC_CPSW_SLIVER_1_REGS               (0x4A100D80)
+#define SOC_CPSW_PORT_2_REGS                 (0x4A100300)
+#define SOC_CPSW_SLIVER_2_REGS               (0x4A100DC0)
+#define SOC_CPSW_CPPI_RAM_REGS               (0x4A102000)
+
+/** @brief Base address of McASP memory mapped registers                      */
+#define SOC_MCASP_0_CTRL_REGS                (0x48038000)
+#define SOC_MCASP_0_FIFO_REGS                (SOC_MCASP_0_CTRL_REGS + 0x1000)
+#define SOC_MCASP_0_DATA_REGS                (0x46000000)
+#define SOC_MCASP_1_CTRL_REGS                (0x4803C000)
+#define SOC_MCASP_1_FIFO_REGS                (SOC_MCASP_1_CTRL_REGS + 0x1000)
+#define SOC_MCASP_1_DATA_REGS                (0x46400000)
+
+/** @brief Base address of EMIF memory mapped registers                       */
+#define SOC_EMIF_0_REGS                      (0x4C000000)
+
+/** @brief Base addresses of RTC memory mapped registers                      */
+#define SOC_RTC_0_REGS                       (0x44E3E000)
+
+/** @brief Base addresses of PRCM memory mapped registers                     */
+#define SOC_PRCM_REGS                        (0x44E00000)
+#define SOC_CM_PER_REGS                      (SOC_PRCM_REGS + 0)
+#define SOC_CM_WKUP_REGS                     (SOC_PRCM_REGS + 0x400)
+#define SOC_CM_DPLL_REGS                     (SOC_PRCM_REGS + 0x500)
+#define SOC_CM_MPU_REGS                      (SOC_PRCM_REGS + 0x600)
+#define SOC_CM_DEVICE_REGS                   (SOC_PRCM_REGS + 0x700)
+#define SOC_CM_RTC_REGS                      (SOC_PRCM_REGS + 0x800)
+#define SOC_CM_GFX_REGS                      (SOC_PRCM_REGS + 0x900)
+#define SOC_CM_CEFUSE_REGS                   (SOC_PRCM_REGS + 0xA00)
+#define SOC_OCP_SOCKET_RAM_REGS              (SOC_PRCM_REGS + 0xB00)
+#define SOC_PRM_PER_REGS                     (SOC_PRCM_REGS + 0xC00)
+#define SOC_PRM_WKUP_REGS                    (SOC_PRCM_REGS + 0xD00)
+#define SOC_PRM_MPU_REGS                     (SOC_PRCM_REGS + 0xE00)
+#define SOC_PRM_DEVICE_REGS                  (SOC_PRCM_REGS + 0xF00)
+#define SOC_PRM_RTC_REGS                     (SOC_PRCM_REGS + 0x1000)
+#define SOC_PRM_GFX_REGS                     (SOC_PRCM_REGS + 0x1100)
+#define SOC_PRM_CEFUSE_REGS                  (SOC_PRCM_REGS + 0x1200)
+
+/** @brief Base address of control module memory mapped registers             */
+#define SOC_CONTROL_REGS                     (0x44E10000)
+
+
+/** @brief Base address of Channel controller  memory mapped registers        */
+#define SOC_EDMA30CC_0_REGS                  (0x49000000)
+
+/** @brief Base address of DCAN module memory mapped registers                */
+#define SOC_DCAN_0_REGS                      (0x481CC000) 
+#define SOC_DCAN_1_REGS                      (0x481D0000) 
+
+/******************************************************************************\
+*  Parameterizable Configuration:- These are fed directly from the RTL
+*  parameters for the given SOC
+\******************************************************************************/
+#define TPCC_MUX(n)                         0xF90 + ((n) * 4)
+
+
+#define SOC_LCDC_0_REGS                     0x4830E000
+
+#define SOC_ADC_TSC_0_REGS                  0x44E0D000
+
+/** @brief Base addresses of PWMSS memory mapped registers.                   */
+
+#define SOC_PWMSS0_REGS                     (0x48300000)
+#define SOC_PWMSS1_REGS                     (0x48302000)
+#define SOC_PWMSS2_REGS                     (0x48304000)
+
+#define SOC_ECAP_REGS                       (0x00000100)
+#define SOC_EQEP_REGS                       (0x00000180)
+#define SOC_EPWM_REGS                       (0x00000200)
+
+#define SOC_ECAP_0_REGS                     (SOC_PWMSS0_REGS + SOC_ECAP_REGS)
+#define SOC_ECAP_1_REGS                     (SOC_PWMSS1_REGS + SOC_ECAP_REGS)
+#define SOC_ECAP_2_REGS                     (SOC_PWMSS2_REGS + SOC_ECAP_REGS)
+
+#define SOC_EQEP_0_REGS                     (SOC_PWMSS0_REGS + SOC_EQEP_REGS)
+#define SOC_EQEP_1_REGS                     (SOC_PWMSS1_REGS + SOC_EQEP_REGS)
+#define SOC_EQEP_2_REGS                     (SOC_PWMSS2_REGS + SOC_EQEP_REGS) 
+
+#define SOC_EPWM_0_REGS                     (SOC_PWMSS0_REGS + SOC_EPWM_REGS)
+#define SOC_EPWM_1_REGS                     (SOC_PWMSS1_REGS + SOC_EPWM_REGS)
+#define SOC_EPWM_2_REGS                     (SOC_PWMSS2_REGS + SOC_EPWM_REGS)
+
+
+#define SOC_EPWM_MODULE_FREQ                 100 
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_AM33XX_H_ */
diff --git a/cpsw/src/locator.c b/cpsw/src/locator.c
new file mode 100755
index 0000000..f8929bb
--- /dev/null
+++ b/cpsw/src/locator.c
@@ -0,0 +1,182 @@
+/*

+ * locator.c

+ *

+ * Device Locator server using UDP

+ *

+*/

+/*

+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without modification,

+ * are permitted provided that the following conditions are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright notice,

+ *    this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright notice,

+ *    this list of conditions and the following disclaimer in the documentation

+ *    and/or other materials provided with the distribution.

+ * 3. The name of the author may not be used to endorse or promote products

+ *    derived from this software without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED

+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT

+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT

+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING

+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY

+ * OF SUCH DAMAGE.

+ *

+ * This file is part of the lwIP TCP/IP stack.

+ *

+ * Author: Adam Dunkels <adam@sics.se>

+ *

+*/

+

+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/

+ * ALL RIGHTS RESERVED

+ */

+

+#include "locator.h"

+#include "lwiplib.h"

+

+/******************************************************************************

+**                      INTERNAL MACRO DEFINITIONS

+*******************************************************************************/

+#define TAG_CMD                      (0xff)

+#define TAG_STATUS                   (0xfe)

+#define CMD_DISCOVER_TARGET          (0x02)

+

+/******************************************************************************

+**                    INTERNAL VARIABLE DEFINITIONS

+*******************************************************************************/

+/*

+** An array that contains the device locator response data.  The format of the

+** data is as follows:

+**

+**     Byte        Description

+**     --------    ------------------------

+**      0          TAG_STATUS

+**      1          packet length

+**      2          CMD_DISCOVER_TARGET

+**      3          board type

+**      4          board ID

+**      5..8       client IP address

+**      9..14      MAC address

+**     15..18      firmware version

+**     19..82      application title

+**     83          checksum

+*/

+static unsigned char locatorData[84];

+

+/******************************************************************************

+**                    INTERNAL FUNCTION PROTOTYPES

+*******************************************************************************/

+static void LocatorReceive(void *arg, struct udp_pcb *pcb, struct pbuf *p,

+                           ip_addr_t *addr, u16_t port);

+

+/******************************************************************************

+**                        FUNCTION DEFINITIONS

+*******************************************************************************/

+/*

+** This function is called by the lwIP TCP/IP stack when it receives a UDP

+** packet from the discovery port.  It produces the response packet, which is

+** sent back to the querying client.

+*/

+static void LocatorReceive(void *arg, struct udp_pcb *pcb, struct pbuf *p,

+                           ip_addr_t *addr, u16_t port)

+{

+    unsigned char *pucData;

+    unsigned long ulIdx;

+

+    /* Validate the contents of the datagram.*/

+    pucData = p->payload;

+    if((p->len != 4) || (pucData[0] != TAG_CMD) || (pucData[1] != 4) ||

+       (pucData[2] != CMD_DISCOVER_TARGET) ||

+       (pucData[3] != ((0 - TAG_CMD - 4 - CMD_DISCOVER_TARGET) & 0xff)))

+    {

+        pbuf_free(p);

+        return;

+    }

+

+    pbuf_free(p);

+

+    p = pbuf_alloc(PBUF_TRANSPORT, sizeof(locatorData), PBUF_RAM);

+    if(p == NULL)

+    {

+        return;

+    }

+

+    /* Calcuate and fill in the checksum on the response packet.*/

+    for(ulIdx = 0, locatorData[sizeof(locatorData) - 1] = 0;

+        ulIdx < (sizeof(locatorData) - 1); ulIdx++)

+    {

+        locatorData[sizeof(locatorData) - 1] -=

+            locatorData[ulIdx];

+    }

+

+    /* Copy the response packet data into the pbuf. */

+    pucData = p->payload;

+    for(ulIdx = 0; ulIdx < sizeof(locatorData); ulIdx++)

+    {

+        pucData[ulIdx] = locatorData[ulIdx];

+    }

+

+    /* Send the response.*/

+    udp_sendto(pcb, p, addr, port);

+

+    pbuf_free(p);

+}

+

+/*

+** Initializes the locator service. Prepares the locator service to

+** handle device discovery requests.  .

+*/

+void LocatorConfig(unsigned char *macArray, const char *appTitle)

+{

+    unsigned int idx;

+    void *pcb;

+

+    /* Clear out the response data.*/

+    for(idx = 0; idx < 84; idx++)

+    {

+        locatorData[idx] = 0;

+    }

+

+    /* Fill in the header for the response data.*/

+    locatorData[0] = TAG_STATUS;

+    locatorData[1] = sizeof(locatorData);

+    locatorData[2] = CMD_DISCOVER_TARGET;

+

+    /* Fill in the MAC address for the response data. */

+    locatorData[9] =  macArray[0];

+    locatorData[10] = macArray[1];

+    locatorData[11] = macArray[2];

+    locatorData[12] = macArray[3];

+    locatorData[13] = macArray[4];

+    locatorData[14] = macArray[5];

+

+    /* Create a new UDP port for listening to device locator requests.*/

+    pcb = udp_new();

+    udp_recv(pcb, (udp_recv_fn) LocatorReceive, NULL);

+    udp_bind(pcb, IP_ADDR_ANY, 23);

+    udp_connect(pcb, IP_ADDR_ANY, 23);

+

+    /* Copy the application title string into the response data. */

+    for(idx = 0; (idx < 64) && *appTitle; idx++)

+    {

+        locatorData[idx + 19] = *appTitle++;

+    }

+

+    /* Zero-fill the remainder of the space in the response data (if any).*/

+    for(; idx < 64; idx++)

+    {

+        locatorData[idx + 19] = 0;

+    }

+

+}

+/***************************** End Of File ***********************************/

+

diff --git a/cpsw/src/lwiplib.c b/cpsw/src/lwiplib.c
new file mode 100755
index 0000000..aeb78e2
--- /dev/null
+++ b/cpsw/src/lwiplib.c
@@ -0,0 +1,389 @@
+/**
+*  \file lwiplib.c
+*
+*  \brief lwip related initializations
+*/
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+*/
+
+/*
+** Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+** ALL RIGHTS RESERVED
+*/
+#include "lwiplib.h"
+#include "beaglebone.h"
+#include "cpsw.h"
+#include "netif/cpswif.h"
+#include "delay.h"
+#include "lwip/netif.h"
+#include "lwip/prot/dhcp.h"
+#include "lwip/dhcp.h"
+#include "lwip/sys.h"
+#include "lwip/autoip.h"
+#include <sched.h>
+
+/* when the link is down, show a message, wait for a while and reboot */
+#define REBOOT_DELAY_SECONDS 5 
+
+#define DEFAULT_INST_NUM 0
+#define DEFAULT_PORT_NUMBER 1
+
+#define LWIP_NOT_INITIALIZED 0
+#define LWIP_INITIALIZED 1
+//#define NUM_DHCP_TRIES 20
+
+#define SECONDS_TO_MILISECONDS 1000
+
+/******************************************************************************
+**                       INTERNAL FUNCTION PROTOTYPES
+******************************************************************************/
+static bool lwIPDHCPComplete(unsigned int ifNum);
+static void CPSWCore0RxIsr(void*);
+static void CPSWCore0TxIsr(void*);
+static void interruptSetup(void);
+
+
+/******************************************************************************
+**                       INTERNAL VARIABLE DEFINITIONS
+******************************************************************************/
+/*
+** The lwIP network interface structure for CPSW ports.
+*/
+#ifdef CPSW_DUAL_MAC_MODE
+static struct netif cpswNetIF[MAX_CPSW_INST * MAX_SLAVEPORT_PER_INST];
+#else
+static struct netif cpswNetIF[MAX_CPSW_INST];
+#endif
+
+/*
+** Helper to identify ports
+*/
+static struct cpswportif cpswPortIf[MAX_CPSW_INST * MAX_SLAVEPORT_PER_INST];
+
+/******************************************************************************
+**                          FUNCTION DEFINITIONS
+******************************************************************************/
+/**
+ * @brief checks if the dhcp has changed its state for 
+ * (LWIP_DHCP_TIMEOUT * 10) ms
+ *  
+ * @param state A pointer to the volatile state to check.
+ */
+static inline void dhcpCheck(volatile unsigned char * const state)
+{
+    unsigned int cnt = LWIP_DHCP_TIMEOUT;
+
+    /* Check for DHCP completion for 'cnt' number of times, each 10ms */
+    while( cnt-- && *state != DHCP_STATE_BOUND)
+    {
+	    if(cnt % 2 == 0)
+               sched_yield();
+        delay(10);
+    }
+}
+
+/**
+ * @brief   This function waits for DHCP completion with a timeout
+ *
+ * @param   ifNum  The netif number for the interface
+ *
+ * @return  True if IP acquired succesfully, false otherwise.
+*/
+static bool lwIPDHCPComplete(const unsigned int ifNum)
+{
+    bool ret = true;
+    unsigned int dhcpTries = 0;
+    volatile unsigned char * state;
+    struct netif* const netif = &cpswNetIF[ifNum];
+
+    do
+    {
+        ++dhcpTries;
+        dhcp_start(netif);
+        state = (volatile unsigned char *) &(netif->state);
+        LWIP_PRINTF("\n\rDHCP Trial %d ", (dhcpTries));
+        dhcpCheck(state);
+    }while((dhcpTries < NUM_DHCP_TRIES) && (*state != DHCP_STATE_BOUND));
+
+    if (*state != DHCP_STATE_BOUND)
+    {
+        LWIP_PRINTF("\n\rUnable to complete DHCP! \n\r");
+        ret = false;
+    }
+    return ret;
+}
+
+/**
+ * @brief Starts the interface in Lwip according to its mode.
+ * 
+ * @param lwipIf The addresses and modes to set.
+ * @param ifNum The interface to set.
+ * 
+ * @return True if mode ok, false otherwise.
+ */
+static bool netifStart(LWIP_IF* const lwipIf, const unsigned int ifNum)
+{
+    bool ret = true;
+    switch(lwipIf->ipMode)
+    {
+        case IPADDR_USE_DHCP:
+            ret = lwIPDHCPComplete(ifNum);
+            break;
+        case IPADDR_USE_AUTOIP:
+            autoip_start(&cpswNetIF[ifNum]);
+            /*This has no break on purpose, since both autoip and static must do netif_set_up*/
+        case IPADDR_USE_STATIC:
+            netif_set_up(&cpswNetIF[ifNum]);
+            break;
+        default:
+            ret = false;
+    }
+    return ret;
+}
+
+/**
+ * @brief Resets Addresses if the mode is not static.
+ * 
+ * @param lwipIf the addresses to configure.
+ */
+static inline void startLwipIf(LWIP_IF* const  lwipIf)
+{
+    if(lwipIf->ipMode != IPADDR_USE_STATIC)
+    {
+        lwipIf->ipAddr.addr = 0;
+        lwipIf->netMask.addr = 0;
+        lwipIf->gwAddr.addr = 0;
+    }
+}
+
+/**
+ * @brief Configures cpswPortIf for de desired interface, setting its
+ * instance number, port number and mac address.
+ * 
+ * @param lwipIf The lwip interface that has the mac address
+ * @param ifNum The interface to configure
+ */
+static inline void setPortIf(LWIP_IF* const lwipIf, const unsigned int ifNum)
+{
+    unsigned int macIndex;
+    cpswPortIf[ifNum].inst_num = ifNum;
+    cpswPortIf[ifNum].port_num = DEFAULT_PORT_NUMBER;
+
+    /* set MAC hardware address */
+    for(macIndex = 0; macIndex < LEN_MAC_ADDRESS; ++macIndex)
+    {
+        cpswPortIf[ifNum].eth_addr[macIndex] =
+                         lwipIf->macArray[(LEN_MAC_ADDRESS - 1) - macIndex];
+    }
+}
+
+/**
+ *
+ * @brief Initializes the lwIP TCP/IP stack.
+ *
+ * @param lwipIf  The interface structure for lwIP
+ *
+ * @return true if everything ok, false otherwise.
+*/
+static bool lwIPInit(LWIP_IF *const lwipIf, const unsigned int ifNum)
+{
+    static unsigned int lwipInitFlag = LWIP_NOT_INITIALIZED;
+    bool ret = true;
+
+    /* do lwip library init only once */
+    if(LWIP_NOT_INITIALIZED == lwipInitFlag)
+    {
+        tcpip_init(NULL, NULL);
+    }
+    setPortIf(lwipIf, ifNum);
+
+    if(netif_add(&cpswNetIF[ifNum], &lwipIf->ipAddr, &lwipIf->netMask, 
+            &lwipIf->gwAddr,&cpswPortIf[ifNum], cpswif_init, tcpip_input) != NULL)
+    {
+        if(LWIP_NOT_INITIALIZED == lwipInitFlag)
+        {
+            netif_set_default(&cpswNetIF[ifNum]);
+            lwipInitFlag = LWIP_INITIALIZED;
+        }
+	//lwipIf->ipMode = IPADDR_USE_DHCP;
+        ret = netifStart(lwipIf, ifNum);
+    }
+    else
+    {
+        LWIP_PRINTF("\n\rUnable to add interface for interface %d", ifNum);
+        ret = false;
+    }
+    return ret;
+}
+
+/**
+ * @brief   Interrupt handler for Receive Interrupt. Directly calls the
+ *          cpsw interface receive interrupt handler.
+ *
+ * @param   instNum  The instance number of CPSW module for which receive
+ *                   interrupt happened
+*/
+static inline void lwIPRxIntHandler(const unsigned int instNum)
+{
+    cpswif_rx_inthandler(instNum);
+}
+
+/**
+ * @brief   Interrupt handler for Transmit Interrupt. Directly calls the
+ *          cpsw interface transmit interrupt handler.
+ *
+ * @param   instNum  The instance number of CPSW module for which transmit
+ *                   interrupt happened
+*/
+static inline void lwIPTxIntHandler(const unsigned int instNum)
+{
+    cpswif_tx_inthandler(instNum);
+}
+
+/**
+ * @brief Initializes low level device.
+ *
+ */
+static inline void cpswInit(void)
+{
+    CPSWPinMuxSetup();
+    CPSWClkEnable();
+}
+
+/**
+ * @brief Initializes Phy and returns MAC Address.
+ * 
+ * @param lwipIfPort The addresses, to return the MAC address.
+ */
+static inline void phyInit(LWIP_IF* const lwipIfPort)
+{
+    /* Chip configuration RGMII selection */
+    EVMPortMIIModeSelect();
+
+    /* Get the MAC address */
+    EVMMACAddrGet(0, lwipIfPort->macArray);
+}
+
+/**
+ * @brief Prints a message wait a delay time and reboot the board(calling exit).
+ */
+static inline void ipFailed(void)
+{
+    printk("\n\r\n\rIP Address Acquisition Failed. Please Verify Your Cable/Link Status...");
+    printk("\n\r\n\rSystem Will Automatically Reboot In %d Seconds.\r\n", REBOOT_DELAY_SECONDS);
+    delay(REBOOT_DELAY_SECONDS * SECONDS_TO_MILISECONDS);
+    exit(1);
+}
+
+/**
+ * @brief Interrupt Handler for Core Receive interrupt
+ * 
+ * @param instNum The device Instance number
+ */
+static void CPSWCore0RxIsr(void* instNum)
+{
+    lwIPRxIntHandler((unsigned int)instNum);
+}
+
+/**
+ * @brief Interrupt Handler for Core Transmit interrupt
+ * 
+ * @param instNum The device Instance number
+ */
+static void CPSWCore0TxIsr(void* instNum)
+{
+    lwIPTxIntHandler((unsigned int)instNum);
+}
+
+/**
+ * @brief Displays the IP address on the Console
+ * 
+ * @param ipAddr The desired IP address to display.
+ */
+static inline void IpAddrDisplay(const ip4_addr_t* const ipAddr)
+{
+    printk("\n\r\n\rIP Address Assigned: %s\r\n", ip4addr_ntoa(ipAddr));
+}
+
+/**
+ * @brief Sets up the ARM Interrupt Controller for generating timer interrupt.
+ */
+static void interruptSetup(void)
+{
+rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  sc = rtems_interrupt_handler_install(
+    AM335X_INT_3PGSWRXINT0,
+    "EthRX",
+    RTEMS_INTERRUPT_UNIQUE,
+    CPSWCore0RxIsr,
+    (void*)DEFAULT_INST_NUM
+  );
+  LWIP_ASSERT("Install interrupt handler rx", sc == RTEMS_SUCCESSFUL);
+
+  sc = rtems_interrupt_handler_install(
+    AM335X_INT_3PGSWTXINT0,
+    "EthTX",
+    RTEMS_INTERRUPT_UNIQUE,
+    CPSWCore0TxIsr,
+    (void*)DEFAULT_INST_NUM
+  );
+    LWIP_ASSERT("Install interrupt handler tx", sc == RTEMS_SUCCESSFUL);
+}
+
+bool startLwip(LWIP_IF* const lwipIfPort)
+{
+    const unsigned int ifNum = DEFAULT_INST_NUM;
+    bool ret;
+
+    /*Initialization of low level device*/
+    cpswInit();
+    /*Initialization of the PHY and getting of MAC Address.*/
+    phyInit(lwipIfPort);
+    /*Set ISR for the device*/
+    interruptSetup();
+    printk("Acquiring IP Address... \n\r" );
+    /*Set up lwipIfPort properly for the desired mode*/
+    startLwipIf(lwipIfPort);
+    /*Start Lwip stack with the desired address*/
+    ret = lwIPInit(lwipIfPort, ifNum);
+
+    if(ret)
+    {       
+        IpAddrDisplay((ip4_addr_t *)&cpswNetIF[ifNum].ip_addr);
+    }
+    else /*Failed lwipinit, Print a message and reset the board*/
+    {
+        ipFailed();
+    }
+    return ret;
+}
diff --git a/cpsw/src/netif/FILES b/cpsw/src/netif/FILES
new file mode 100755
index 0000000..0411124
--- /dev/null
+++ b/cpsw/src/netif/FILES
@@ -0,0 +1 @@
+cpswif.c - lwIP Ethernet interface for CPSW based devices.
diff --git a/cpsw/src/netif/cache.c b/cpsw/src/netif/cache.c
new file mode 100755
index 0000000..699961b
--- /dev/null
+++ b/cpsw/src/netif/cache.c
@@ -0,0 +1,249 @@
+/**
+ *  \file   cache.c
+ *
+ *  \brief  APIs for configuring Cache
+ *
+ *  This file contains the APIs for configuring ARMv7a Cache
+*/
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+#include "cache.h"
+#include "cp15.h"
+
+/*****************************************************************************
+**                      INTERNAL MACRO DEFINITIONS
+******************************************************************************/
+#define CORTEX_A8_L2EN                   (0x02)
+#define PRIMARY_PART_CORTEX_A8           (0xC08) 
+
+/*****************************************************************************
+**                         FUNCTION DEFINITIONS
+******************************************************************************/
+/**
+ * \brief   Disables Cache. The levels/type of Cache to be disabled
+ *          is passed as parameter.
+ *
+ * \param   disFlag   Caches to be disabled.
+ *            'disFlag' can take one of the below values. \n
+ *                CACHE_ICACHE - To disable Instruction Cache \n
+ *                CACHE_DCACHE - To disable Data/Unified Cache \n
+ *                CACHE_ALL - To disable all levels of Cache
+ *
+ * \return  None.
+ *
+ * \Note    Disabling Data Cache disables Unified cache also, if present.
+ **/
+void CacheDisable(unsigned int disFlag)
+{
+    if(disFlag & CACHE_ICACHE)
+    {
+        /*
+        **  Disable I-Cache. The I-Cache invalidation is also done inside
+        **  CP15ICacheDisable().
+        */
+        CP15ICacheDisable();
+    }
+
+    /* Here D Cache Disabling disables Unified cache also */
+    if(disFlag & CACHE_DCACHE)
+    {
+        /*
+        **  Disable D-Cache. The D-Cache Clean and Invalidation is also done
+        **  inside CP15DCacheDisable().
+        */
+        CP15DCacheDisable();
+
+        /* For Cortex A8, L2EN has to be disabled for L2 Cache */
+        if(PRIMARY_PART_CORTEX_A8 == CP15MainIdPrimPartNumGet())
+        {
+            CP15AuxControlFeatureDisable(CORTEX_A8_L2EN);
+        }
+    }
+}
+
+/**
+ * \brief   Enables Cache. The levels/type of Cache to be enabled
+ *          is passed as parameter.
+ *
+ * \param   enFlag   Caches to be enabled.
+ *            'enFlag' can take one of the below values. \n
+ *                CACHE_ICACHE - To enable Instruction Cache \n
+ *                CACHE_DCACHE - To enable Data/Unified Cache \n
+ *                CACHE_ALL - To enable all levels of Cache
+ *
+ * \return  None.
+ *
+ * \Note    Enabling Data Cache enables Unified cache also, if present.
+ **/
+void CacheEnable(unsigned int enFlag)
+{
+    if(enFlag & CACHE_ICACHE)
+    { 
+        CP15ICacheFlush();
+        CP15ICacheEnable();
+    }
+
+    if(enFlag & CACHE_DCACHE)
+    {   
+        /* For Cortex A8, L2EN has to be enabled for L2 Cache */
+        if(PRIMARY_PART_CORTEX_A8 == CP15MainIdPrimPartNumGet())
+        {
+            CP15AuxControlFeatureEnable(CORTEX_A8_L2EN);
+        }
+
+        CP15DCacheFlush();
+        CP15DCacheEnable();
+    }
+}
+
+/**
+ * \brief   This API invalidates the entire I-Cache
+ *
+ * \param   None
+ *
+ * \return  None.
+ *
+ **/
+void CacheInstInvalidateAll(void)
+{
+    CP15ICacheFlush();
+}
+
+/**
+ * \brief   This API invalidates a section of I-Cache. 
+ *
+ * \param   startAddr    Starting address to be invalidated
+ * \param   numBytes     The number of bytes to be invalidated
+ *
+ * \return  None.
+ *
+ **/
+void CacheInstInvalidateBuff(unsigned int startAddr, unsigned int numBytes)
+{
+    CP15ICacheFlushBuff(startAddr, numBytes);
+}
+
+/**
+ * \brief   This API Cleans and Invalidates the entire Data Cache.
+ *
+ * \param   None
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataCleanInvalidateAll(void)
+{
+    CP15DCacheCleanFlush();
+}
+
+/**
+ * \brief   This API Cleans the entire Data Cache.
+ *
+ * \param   None
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataCleanAll(void)
+{
+    CP15DCacheClean();
+}
+
+/**
+ * \brief   This API Invalidates the entire Data Cache.
+ *
+ * \param   None
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataInvalidateAll(void)
+{
+    CP15DCacheFlush();
+}
+
+/**
+ * \brief   This API clean a section of D-Cache, upto PoC. This API
+ *          can be used to make a buffer in D-Cache to be coherent
+ *          with the memory. For example, If DMA engine has to access
+ *          a memory area for transmitting, to make sure that the 
+ *          D-Cache values for the corresponding buffer is written to 
+ *          memory, this API can be used.
+ *
+ * \param   startAddr    Starting address of the buffer to be cleaned
+ * \param   numBytes     The number of bytes to be cleaned.
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataCleanBuff(unsigned int startAddr, unsigned int numBytes)
+{
+    CP15DCacheCleanBuff(startAddr, numBytes);
+}
+
+/**
+ * \brief   This API invalidates a section of D-Cache till PoC. With this
+ *          API, we can make sure that the next read of the buffer happens
+ *          from memory. This is required if any DMA engine has updated
+ *          the memory area with any data, other than from the D-Cache.
+ *
+ * \param   startAddr    Starting address of the buffer to be invalidated
+ * \param   numBytes     The number of bytes to be invalidated
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataInvalidateBuff(unsigned int startAddr, unsigned int numBytes)
+{
+    CP15DCacheFlushBuff(startAddr, numBytes);
+}
+
+/**
+ * \brief   This API cleans and invalidates a section of D-Cache to PoC.
+ *
+ * \param   startAddr    Starting address of the buffer to be cleaned 
+ *                       and invalidated
+ * \param   numBytes     The number of bytes to be cleaned and invalidated
+ *
+ * \return  None.
+ *
+ **/
+void CacheDataCleanInvalidateBuff(unsigned int startAddr, unsigned int numBytes)
+{
+    CP15DCacheCleanFlushBuff(startAddr, numBytes);
+}
+
+/***************************** End Of File ***********************************/
+
diff --git a/cpsw/src/netif/cp15.S b/cpsw/src/netif/cp15.S
new file mode 100755
index 0000000..530288b
--- /dev/null
+++ b/cpsw/src/netif/cp15.S
@@ -0,0 +1,588 @@
+@******************************************************************************
+@
+@ cp15.S - CP15 coprocesser configuration APIs
+@
+@******************************************************************************
+@
+@ Copyright (C) 2010 Texas InSTRuments Incorporated - http://www.ti.com/
+@
+@
+@  RediSTRibution and use in source and binary forms, with or without
+@  modification, are permitted provided that the following conditions
+@  are met:
+@
+@    RediSTRibutions of source code must retain the above copyright
+@    notice, this list of conditions and the following disclaimer.
+@
+@    RediSTRibutions in binary form must reproduce the above copyright
+@    notice, this list of conditions and the following disclaimer in the
+@    documentation and/or other materials provided with the
+@    diSTRibution.
+@
+@    Neither the name of Texas InSTRuments Incorporated nor the names of
+@    its contributors may be used to endorse or promote products derived
+@    from this software without specific prior written permission.
+@
+@  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+@  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+@  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+@  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+@  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+@  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+@  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+@  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+@  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+@******************************************************************************
+
+@****************************** Global Symbols*********************************
+        .global CP15ICacheDisable
+        .global CP15DCacheDisable
+        .global CP15ICacheEnable
+        .global CP15DCacheEnable
+        .global CP15ICacheFlush
+        .global CP15DCacheCleanFlush
+        .global CP15DCacheClean
+        .global CP15DCacheFlush
+        .global CP15DCacheCleanBuff
+        .global CP15DCacheCleanFlushBuff
+        .global CP15DCacheFlushBuff
+        .global CP15ICacheFlushBuff
+        .global CP15Ttb0Set
+        .global CP15TlbInvalidate
+        .global CP15MMUDisable
+        .global CP15MMUEnable
+        .global CP15VectorBaseAddrSet
+        .global CP15BranchPredictorInvalidate
+        .global CP15BranchPredictionEnable
+        .global CP15BranchPredictionDisable
+        .global CP15DomainAccessClientSet
+        .global CP15ControlFeatureDisable
+        .global CP15ControlFeatureEnable
+        .global CP15TtbCtlTtb0Config
+        .global CP15AuxControlFeatureEnable
+        .global CP15AuxControlFeatureDisable
+        .global CP15MainIdPrimPartNumGet
+
+@**************************** Code section ************************************
+        .text
+
+        @ This code is assembled for ARM instructions
+        .code 32
+
+
+@*****************************************************************************
+@ This API disable the InSTRuction cache.
+@*****************************************************************************
+CP15ICacheDisable:
+    PUSH    {lr}
+    MRC     p15, #0, r0, c1, c0, #0
+    BIC     r0,  r0, #0x00001000
+    MCR     p15, #0, r0, c1, c0, #0
+    BL      CP15ICacheFlush
+    POP     {lr}
+    BX      lr
+
+@*****************************************************************************
+@ This API disable the Data cache.
+@*****************************************************************************
+CP15DCacheDisable:
+    PUSH    {r4-r11, lr}
+    MRC     p15, #0, r0, c1, c0, #0
+    BIC     r0,  r0, #0x00000004
+    MCR     p15, #0, r0, c1, c0, #0
+    BL      CP15DCacheCleanFlush
+    POP     {r4-r11, lr}
+    BX      lr
+
+@*****************************************************************************
+@ This API enables I-cache
+@*****************************************************************************
+CP15ICacheEnable:
+    MRC     p15, #0, r0, c1, c0, #0
+    ORR     r0,  r0, #0x00001000
+    MCR     p15, #0, r0, c1, c0, #0 
+    BX      lr
+
+@*****************************************************************************
+@ This API enable the Data cache.
+@*****************************************************************************
+CP15DCacheEnable:
+    MRC     p15, #0, r0, c1, c0, #0 
+    ORR     r0,  r0, #0x00000004
+    MCR     p15, #0, r0, c1, c0, #0
+    BX      lr
+
+@*****************************************************************************
+@ This API Invalidates the entire Data/Unified Cache
+@*****************************************************************************
+CP15DCacheFlush:
+    PUSH    {r4-r11}
+    DMB
+    MRC     p15, #1, r0, c0, c0, #1  @ Read CLID register
+    ANDS    r3, r0, #0x7000000       @ Get Level of Coherency
+    MOV     r3, r3, lsr #23
+    BEQ     ffinished
+    MOV     r10, #0
+floop1:
+    ADD     r2, r10, r10, lsr #1
+    MOV     r1, r0, lsr r2
+    AND     r1, r1, #7
+    CMP     r1, #2
+    BLT     fskip
+    MCR     p15, #2, r10, c0, c0, #0
+    ISB
+    MRC     p15, #1, r1, c0, c0, #0
+    AND     r2, r1, #7
+    ADD     r2, r2, #4
+    LDR     r4, _FLD_MAX_WAY
+    ANDS    r4, r4, r1, lsr #3
+    CLZ     r5, r4
+    LDR     r7, _FLD_MAX_IDX
+    ANDS    r7, r7, r1, lsr #13
+floop2:
+    MOV     r9, r4
+floop3:
+    ORR     r11, r10, r9, lsl r5
+    ORR     r11, r11, r7, lsl r2
+    MCR     p15, #0, r11, c7, c6, #2
+    SUBS    r9, r9, #1
+    BGE     floop3
+    SUBS    r7, r7, #1
+    BGE     floop2
+fskip:
+    ADD     r10, r10, #2
+    CMP     r3, r10
+    BGT     floop1
+
+ffinished:
+    DSB
+    ISB
+    POP     {r4-r11}
+    BX      lr
+
+
+@*****************************************************************************
+@ This API cleans the entire D Cache to PoC
+@*****************************************************************************
+CP15DCacheClean:
+    PUSH    {r4-r11}
+    DMB
+    MRC     p15, #1, r0, c0, c0, #1  @ Read CLID register
+    ANDS    r3, r0, #0x7000000       @ Get Level of Coherency
+    MOV     r3, r3, lsr #23
+    BEQ     cfinished
+    MOV     r10, #0
+cloop1:
+    ADD     r2, r10, r10, lsr #1
+    MOV     r1, r0, lsr r2
+    AND     r1, r1, #7
+    CMP     r1, #2
+    BLT     cskip
+    MCR     p15, #2, r10, c0, c0, #0
+    ISB
+    MRC     p15, #1, r1, c0, c0, #0
+    AND     r2, r1, #7
+    ADD     r2, r2, #4
+    LDR     r4, _FLD_MAX_WAY
+    ANDS    r4, r4, r1, lsr #3
+    CLZ     r5, r4
+    LDR     r7, _FLD_MAX_IDX
+    ANDS    r7, r7, r1, lsr #13
+cloop2:
+    MOV     r9, r4
+cloop3:
+    ORR     r11, r10, r9, lsl r5
+    ORR     r11, r11, r7, lsl r2
+    MCR     p15, #0, r11, c7, c10, #2
+    SUBS    r9, r9, #1
+    BGE     cloop3
+    SUBS    r7, r7, #1
+    BGE     cloop2
+cskip:
+    ADD     r10, r10, #2
+    CMP     r3, r10
+    BGT     cloop1
+
+cfinished:
+    DSB
+    ISB
+    POP     {r4-r11}
+    BX      lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the entire D Cache to PoC
+@*****************************************************************************
+CP15DCacheCleanFlush:
+    PUSH    {r4-r11} 
+    DMB
+    MRC     p15, #1, r0, c0, c0, #1  @ Read CLID register
+    ANDS    r3, r0, #0x7000000       @ Get Level of Coherency
+    MOV     r3, r3, lsr #23  
+    BEQ     finished  
+    MOV     r10, #0 
+loop1:
+    ADD     r2, r10, r10, lsr #1 
+    MOV     r1, r0, lsr r2
+    AND     r1, r1, #7 
+    CMP     r1, #2  
+    BLT     skip 
+    MCR     p15, #2, r10, c0, c0, #0 
+    ISB 
+    MRC     p15, #1, r1, c0, c0, #0 
+    AND     r2, r1, #7 
+    ADD     r2, r2, #4   
+    LDR     r4, _FLD_MAX_WAY 
+    ANDS    r4, r4, r1, lsr #3
+    CLZ     r5, r4
+    LDR     r7, _FLD_MAX_IDX
+    ANDS    r7, r7, r1, lsr #13 
+loop2:
+    MOV     r9, r4   
+loop3:
+    ORR     r11, r10, r9, lsl r5  
+    ORR     r11, r11, r7, lsl r2 
+    MCR     p15, #0, r11, c7, c14, #2 
+    SUBS    r9, r9, #1 
+    BGE     loop3 
+    SUBS    r7, r7, #1 
+    BGE     loop2 
+skip: 
+    ADD     r10, r10, #2 
+    CMP     r3, r10 
+    BGT     loop1 
+
+finished:
+    DSB
+    ISB                        
+    POP     {r4-r11} 
+    BX      lr
+
+@*****************************************************************************
+@ This API invalidates entire I Cache
+@*****************************************************************************
+CP15ICacheFlush:
+    MOV     r0, #0
+    MCR     p15, #0, r0, c7, c5, #0
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API cleans the D-cache/Unified  lines corresponding to the buffer 
+@ pointer upto the specified length to PoC.
+@ r0 - Start Address 
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+CP15DCacheCleanBuff:
+    PUSH    {r14}
+    ADD     r14, r0, r1               @ Calculate the end address
+    DMB
+    MRC     p15, #0, r2, c0, c0, #1   @ Read Cache Type Register
+    UBFX    r2, r2, #16, #4           @ Extract the DMinLine
+    MOV     r3, #2
+    ADD     r3, r3, r2
+    MOV     r2, #1
+    LSL     r2, r2, r3                @ Calculate the line size
+   
+    SUB     r3, r2, #1                @ Calculate the mask
+    BIC     r0, r0, r3                @ Align to cache line boundary   
+    TST     r3, r14
+    BIC     r14, r14, r3
+    MCRNE   p15, #0, r14, c7, c10, #1 @ Clean D/Unified to PoC by MVA
+
+cleanloop:    
+    MCR     p15, #0, r0 , c7, c10, #1 @ Clean D/Unified to PoC by MVA
+    ADDS    r0, r0, r2                @ Go to next line
+    CMP     r0, r14 
+    BLT     cleanloop
+ 
+    POP     {r14}
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API cleans and invalidates the D-cache/Unified  lines corresponding to 
+@ the buffer pointer upto the specified length to PoC.
+@ r0 - Start Address 
+@ r1 - Number of bytes to be cleaned and flushed
+@*****************************************************************************
+CP15DCacheCleanFlushBuff:
+    PUSH    {r14}
+    ADD     r14, r0, r1               @ Calculate the end address
+    DMB
+    MRC     p15, #0, r2, c0, c0, #1   @ Read Cache Type Register
+    UBFX    r2, r2, #16, #4           @ Extract the DMinLine
+    MOV     r3, #2
+    ADD     r3, r3, r2
+    MOV     r2, #1
+    LSL     r2, r2, r3                @ Calculate the line size
+   
+    SUB     r3, r2, #1                @ Calculate the mask
+    BIC     r0, r0, r3                @ Align to cache line boundary   
+    TST     r3, r14
+    BIC     r14, r14, r3
+    MCRNE   p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC
+
+cleanflushloop:    
+    MCR     p15, #0, r0 , c7, c14, #1 @ Clean and Flush D/U line to PoC 
+    ADDS    r0, r0, r2                @ Go to next line
+    CMP     r0, r14 
+    BLT     cleanflushloop
+ 
+    POP     {r14}
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API invalidates the D-cache/Unified  lines corresponding to 
+@ the buffer pointer upto the specified length to PoC.
+@ r0 - Start Address 
+@ r1 - Number of bytes to be flushed
+@*****************************************************************************
+CP15DCacheFlushBuff:
+    PUSH    {r14}
+    ADD     r14, r0, r1               @ Calculate the end address
+    DMB
+    MRC     p15, #0, r2, c0, c0, #1   @ Read Cache Type Register
+    UBFX    r2, r2, #16, #4           @ Extract the DMinLine
+    MOV     r3, #2
+    ADD     r3, r3, r2
+    MOV     r2, #1
+    LSL     r2, r2, r3                @ Calculate the line size
+   
+    SUB     r3, r2, #1                @ Calculate the mask
+    TST     r3, r0 
+    BIC     r0, r0, r3                @ Align to cache line boundary   
+    MCRNE   p15, #0, r0, c7, c14, #1  @ Clean and Flush D/U line to PoC 
+    ADDNE   r0, r0, r2
+    TST     r3, r14 
+    BIC     r14, r14, r3              
+    MCRNE   p15, #0, r14, c7, c14, #1 @ Clean and Flush D/U line to PoC 
+    B       dflushcmp
+
+dflushloop:
+    MCR     p15, #0, r0 , c7, c6, #1  @ Flush D/U line to PoC    
+    ADDS    r0, r0, r2                @ Go to next line
+
+dflushcmp:
+    CMP     r0, r14
+    BLT     dflushloop
+    POP     {r14}
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API invlidates I-cache lines from the star address till the length   
+@ specified to PoU.
+@ r0 - Start Address 
+@ r1 - Number of bytes to be cleaned
+@*****************************************************************************
+CP15ICacheFlushBuff:
+    PUSH    {r14}
+    ADD     r14, r0, r1               @ Calculate the end address
+    DMB
+    MRC     p15, #0, r2, c0, c0, #1   @ Read Cache Type Register
+    UBFX    r2, r2, #0, #4            @ Extract the DMinLine
+    MOV     r3, #2
+    ADD     r3, r3, r2
+    MOV     r2, #1
+    LSL     r2, r2, r3                @ Calculate the line size
+   
+    SUB     r3, r2, #1                @ Calculate the mask
+    BIC     r0, r0, r3                @ Align to cache line boundary   
+    TST     r3, r14
+    BIC     r14, r14, r3
+    MCRNE   p15, #0, r14, c7, c5, #1  @ Invalidate by MVA to PoU
+
+iflushloop:    
+    MCR     p15, #0, r0, c7, c5, #1   @ Invalidate by MVA to PoU
+    ADDS    r0, r0, r2                @ Go to next line
+    CMP     r0, r14 
+    BLT     iflushloop
+ 
+    POP     {r14}
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ Sets TTB0 Register
+@ r0 - Translation Table Base Address
+@*****************************************************************************
+CP15Ttb0Set:
+    MCR     p15, #0, r0, c2, c0, #0
+    DMB
+    BX      lr
+
+@*****************************************************************************
+@ This API Invalidates the TLB
+@*****************************************************************************
+CP15TlbInvalidate:
+    MCR     p15, #0, r0, c8, c7, #0    @ r0 value will be ignored
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API Disables MMU. 
+@*****************************************************************************
+CP15MMUDisable:
+    MCR     p15, #0, r0, c8, c7, #0    @ Invalidate TLB  
+    MRC     p15, #0, r0, c1, c0, #0    
+    BIC     r0, r0, #1      
+    MCR     p15, #0, r0, c1, c0, #0    @ Clear MMU bit
+    DSB  
+    BX      lr
+
+@*****************************************************************************
+@ This API Enables MMU. 
+@*****************************************************************************
+CP15MMUEnable:
+    MRC     p15, #0, r0, c1, c0, #0
+    ORR     r0, r0, #0x001
+    MCR     p15, #0, r0, c1, c0, #0    @ Set MMU Enable bit
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API sets the interrupt vector table base address 
+@ r0 - Interrput Vector Base Address
+@*****************************************************************************
+CP15VectorBaseAddrSet:
+    MCR     p15, #0, r0, c12, c0, #0
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API invalidates the branch predictor 
+@*****************************************************************************
+CP15BranchPredictorInvalidate:
+    MCR     p15, #0, r0, c7, c5, #6
+    ISB
+    BX      lr
+
+@*****************************************************************************
+@ This API enables the branch predictor 
+@*****************************************************************************
+CP15BranchPredictionEnable:
+    MRC     p15, #0, r0, c1, c0, #0
+    ORR     r0, r0, #0x00000800
+    MCR     p15, #0, r0, c1, c0, #0
+    BX      lr
+
+@*****************************************************************************
+@ This API disables the branch predictor 
+@*****************************************************************************
+CP15BranchPredictionDisable:
+    MRC     p15, #0, r0, c1, c0, #0
+    BIC     r0, r0, #0x00000800
+    MCR     p15, #0, r0, c1, c0, #0
+    BX      lr
+
+@*****************************************************************************
+@ This API sets the domain access to 'client' 
+@*****************************************************************************
+CP15DomainAccessClientSet:
+    LDR     r0, _CLIENTD 
+    MCR     p15, #0, r0, c3, c0, #0
+    DSB
+    BX      lr
+
+
+@*****************************************************************************
+@ This API Disables specified features in CP15 control register
+@  r0 -  features   Features to disable in Coprocessor 15 control
+@                       register. 
+@               'features' can take any OR a combination of the
+@               below  values. 
+@                CP15_CONTROL_TEXREMAP - TEX remap flag 
+@                CP15_CONTROL_ACCESSFLAG - Access flag Control 
+@                CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking 
+@                CP15_CONTROL_MMU - To enable MMU 
+@ 
+@ Note: Other fields of the CP15 c1 control register are not given here
+@       as they are not of importance for StarterWare. However, optionally
+@       they can also be ADDed.
+@
+@*****************************************************************************
+CP15ControlFeatureDisable:
+    MRC     p15, #0, r1, c1, c0, #0 
+    BIC     r0, r1, r0  
+    MCR     p15, #0, r0, c1, c0, #0
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API Enables specified features in CP15 control register
+@  r0 -  features   Features to disable in Coprocessor 15 control
+@                       register. 
+@               'features' can take any OR a combination of the
+@               below  values. 
+@                CP15_CONTROL_TEXREMAP - TEX remap flag 
+@                CP15_CONTROL_ACCESSFLAG - Access flag Control 
+@                CP15_CONTROL_ALIGN_CHCK - Alignment Fault Checking 
+@                CP15_CONTROL_MMU - To enable MMU 
+@ 
+@ Note: Other fields of the CP15 c1 control register are not given here
+@       as they are not of importance for StarterWare. However, optionally
+@       they can also be ADDed.
+@
+@*****************************************************************************
+CP15ControlFeatureEnable:
+    MRC     p15, #0, r1, c1, c0, #0 
+    ORR     r0, r1, r0  
+    MCR     p15, #0, r0, c1, c0, #0
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API Configures the TTB control register to use only TTB0
+@*****************************************************************************
+CP15TtbCtlTtb0Config:
+    MOV     r0, #0x0
+    MCR     p15, #0, r0, c2, c0, #2
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API Sets the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be set in Auxiliary Control Register
+@*****************************************************************************
+CP15AuxControlFeatureEnable:
+    MRC     p15, #0, r1, c1, c0, #1 
+    ORR     r0,  r0, r1
+    MCR     p15, #0, r0, c1, c0, #1
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API Clears the specified fields in Auxiliary Control Register
+@ r0 - Bit Mask for the bits to be cleared in Auxiliary Control Register
+@*****************************************************************************
+CP15AuxControlFeatureDisable:
+    MRC     p15, #0, r1, c1, c0, #1 
+    BIC     r0,  r1, r0
+    MCR     p15, #0, r0, c1, c0, #1
+    DSB
+    BX      lr
+
+@*****************************************************************************
+@ This API returns the main ID register in r0
+@*****************************************************************************
+CP15MainIdPrimPartNumGet:
+    MRC     p15, #0, r0, c0, c0, #0
+    UBFX    r0, r0, #4, #12
+    BX      lr
+
+_CLIENTD: 
+   .word  0x55555555
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+@
+@ End of the file
+@
+    .end
+
diff --git a/cpsw/src/netif/cpsw.c b/cpsw/src/netif/cpsw.c
new file mode 100755
index 0000000..e82595b
--- /dev/null
+++ b/cpsw/src/netif/cpsw.c
@@ -0,0 +1,1545 @@
+/**
+ *  \file   cpsw.c
+ *
+ *  \brief  CPSW device abstraction layer APIs.
+ *
+ *   This file contains the device abstraction layer APIs for CPSW RGMII.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#include "hw_types.h"
+#include "cpsw.h"
+
+/*******************************************************************************
+*                       INTERNAL MACRO DEFINITIONS
+*******************************************************************************/
+#define CPSW_CORE_OFFSET                   (0x10u)
+#define CPSW_MAX_HEADER_DESC               (0x08u)
+#define CPDMA_P0_DEF_TX_MAP                (0x76543210u)
+#define ALE_ENTRY_WORDS                    (0x03u)
+#define CPDMA_ERR_CHANNEL_POS              (0xFFu)
+#define CPSW_PORT_DUAL_MAC_MODE            (0x01u <<                        \
+                                            CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_SHIFT)
+#define CPSW_PORT_RATE_LIM_MODE            (0x02u <<                        \
+                                            CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_SHIFT)
+
+/*******************************************************************************
+*                        API FUNCTION DEFINITIONS
+*******************************************************************************/
+/**
+ * \brief   Resets the CPSW Subsystem.
+ *
+ * \param   baseAddr    Base address of the CPSW Subsystem
+ *
+ * \return  None
+ **/
+void CPSWSSReset(unsigned int baseAddr)
+{
+    /* Reset the CPSW */
+    HWREG(baseAddr + CPSW_SS_SOFT_RESET) = CPSW_SS_SOFT_RESET_SOFT_RESET;
+
+    while(HWREG(baseAddr + CPSW_SS_SOFT_RESET)
+          & CPSW_SS_SOFT_RESET_SOFT_RESET);
+}
+
+/**
+ * \brief   Force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has
+ *          been stopped by the PHY
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlGigModeForceEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SL_MACCONTROL) |= CPSW_SL_MACCONTROL_GIG_FORCE;
+}
+
+/**
+ * \brief   Enables the fullduplex and gigabit mode to be selected
+ *          from the FULLDUPLEX_IN and GIG_IN input signals and not from the
+ *          fullduplex and gig bits in this register. The FULLDUPLEX_MODE bit
+ *          reflects the actual fullduplex mode selected
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlControlExtEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SL_MACCONTROL) |= CPSW_SL_MACCONTROL_EXT_EN;
+}
+
+
+/**
+ * \brief   Disables the CPGMAC_SL gigabit mode if the input GMII_MTCLK has
+ *          been stopped by the PHY
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlGigModeForceDisable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SL_MACCONTROL) &= ~CPSW_SL_MACCONTROL_GIG_FORCE;
+}
+
+/**
+ * \brief   Sets the Transfer mode, 10/100 or gigabit mode  and the duplex
+ *          mode  for the sliver.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ * \param   mode        The transfer mode
+ *    'mode' can take one of the below values. \n
+ *         CPSW_SLIVER_NON_GIG_HALF_DUPLEX - 10/100 Mbps mode, half duplex. \n
+ *         CPSW_SLIVER_NON_GIG_FULL_DUPLEX - 10/100 Mbps mode, full duplex. \n
+ *         CPSW_SLIVER_GIG_FULL_DUPLEX - 1000 Mbps mode, full duplex. \n
+ *         Note: for 10Mbps mode, CPSW_SLIVER_INBAND has to be configured. \n
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlTransferModeSet(unsigned int baseAddr, unsigned int mode)
+{
+    HWREG(baseAddr + CPSW_SL_MACCONTROL) &= ~(CPSW_SL_MACCONTROL_GIG
+                                              | CPSW_SL_MACCONTROL_FULLDUPLEX);
+
+    HWREG(baseAddr + CPSW_SL_MACCONTROL) |= mode;
+}
+
+/**
+ * \brief   Returns the MAC Status. The value will be the contents of the MAC
+ *          status register.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ * \param   statFlag    Status flags to be read.
+ *            statFlag can take an OR combination of the below values. \n
+ *              CPSW_SLIVER_STATE - The Sliver state. \n
+ *              CPSW_SLIVER_EXT_GIG_INPUT_BIT - The EXT_GIG input bit mask.\n
+ *              CPSW_SLIVER_EXT_FULL_DUPLEX_BIT - The EXT_FULLDUPLEX input
+ *                                                  bit mask. \n
+ *              CPSW_SLIVER_RX_FLOWCTRL - The receive flow control active. \n
+ *              CPSW_SLIVER_TX_FLOWCTRL - The transmit flow control.
+ *
+ *
+ * \return  MAC Status
+ *            The MAC status register value returned can be compared against
+ *            the below tokens. \n
+ *              CPSW_SLIVER_STATE_IDLE - The Sliver is in idle state. \n
+ *              CPSW_SLIVER_EXT_GIG_INPUT_HIGH - The EXT_GIG input
+ *                                                 bit is in HIGH state.\n
+ *              CPSW_SLIVER_EXT_FULL_DUPLEX_HIGH - The EXT_FULLDUPLEX input
+ *                                                   bit is in HIGH state. \n
+ *              CPSW_SLIVER_RX_FLOWCTRL_ACTIVE - The receive flow control is
+ *                                                 active. \n
+ *              CPSW_SLIVER_TX_FLOWCTRL_ACTIVE - The pause time period is
+ *                                                 observed for a received
+ *                                                 pause frame
+ *
+ **/
+unsigned int CPSWSlMACStatusGet(unsigned int baseAddr, unsigned int statFlag)
+{
+    /* Return the required status only */
+    return (HWREG(baseAddr + CPSW_SL_MACSTATUS) & statFlag);
+}
+
+/**
+ * \brief   Resets the CPSW Sliver Logic.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlReset(unsigned int baseAddr)
+{
+    /* Reset the sliver logic */
+    HWREG(baseAddr + CPSW_SL_SOFT_RESET) = CPSW_SL_SOFT_RESET_SOFT_RESET;
+
+    /* Wait till the reset completes */
+    while(CPSW_SL_SOFT_RESET_SOFT_RESET ==
+          ((HWREG(baseAddr + CPSW_SL_SOFT_RESET))
+           & CPSW_SL_SOFT_RESET_SOFT_RESET));
+}
+
+
+/**
+ * \brief   Sets the maximum length for received frame.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ * \param   rxMaxLen    Maximum length for a received frame
+ *     The default value for 'rxMaxLen' is 1518. The maximum value
+ *     which can be set is 16383.
+ *
+ * \return  None
+ *
+ **/
+void CPSWSlRxMaxLenSet(unsigned int baseAddr, unsigned int rxMaxLen)
+{
+    /* Set the desired maximum length */
+    HWREG(baseAddr + CPSW_SL_RX_MAXLEN) = rxMaxLen;
+}
+
+/**
+ * \brief   Enables GMII for the sliver.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ **/
+void CPSWSlGMIIEnable(unsigned int baseAddr)
+{
+   HWREG(baseAddr + CPSW_SL_MACCONTROL) |= CPSW_SL_MACCONTROL_GMII_EN;
+}
+
+/**
+ * \brief   Enables RGMII for the sliver.
+ *
+ * \param   baseAddr    Base address of the CPSW Sliver Module registers.
+ *
+ * \return  None
+ **/
+void CPSWSlRGMIIEnable(unsigned int baseAddr)
+{
+   HWREG(baseAddr + CPSW_SL_MACCONTROL) |= (CPSW_SL_MACCONTROL_GMII_EN
+                                            | CPSW_SL_MACCONTROL_IFCTL_A
+                                            | CPSW_SL_MACCONTROL_IFCTL_B);
+}
+
+/**
+ * \brief   Resets the CPSW Wrapper module.
+ *
+ * \param   baseAddr    Base address of the CPSW Wrapper Module
+ *
+ * \return  None
+ **/
+void CPSWWrReset(unsigned int baseAddr)
+{
+    /* Reset the CPSW Wrapper */
+    HWREG(baseAddr + CPSW_WR_SOFT_RESET) = CPSW_WR_SOFT_RESET_SOFT_RESET;
+
+    while(HWREG(baseAddr + CPSW_WR_SOFT_RESET)
+          & CPSW_WR_SOFT_RESET_SOFT_RESET);
+}
+
+/**
+ * \brief   Resets the Control Register of CPSW Wrapper module
+ *
+ * \param   baseAddr    Base address of the CPSW Wrapper Module
+ *
+ * \return  None
+ **/
+void CPSWWrControlRegReset(unsigned int baseAddr)
+{
+    /* Reset the CPSW Wrapper control Register */
+    HWREG(baseAddr + CPSW_WR_CONTROL) =  CPSW_WR_CONTROL_MMR_RESET;
+}
+
+/**
+ * \brief   Enables an interrupt for the specified core.
+ *
+ * \param   baseAddr    Base address of the CPSW Wrapper Module
+ * \param   core        Core number
+ * \param   channel     Channel number
+ * \param   intFlag     Interrupt to be enabled
+ *    'intFlag' can take one of the below values. \n
+ *          CPSW_CORE_INT_RX_THRESH - RX threshold interrupt \n
+ *          CPSW_CORE_INT_RX_PULSE - RX pulse interrupt \n
+ *          CPSW_CORE_INT_TX_PULSE - TX pulse interrupt \n
+ *          CPSW_CORE_INT_MISC - Miscellaneous interrupt
+ *
+ * \return  None
+ **/
+void CPSWWrCoreIntEnable(unsigned int baseAddr, unsigned int core,
+                         unsigned int channel, unsigned int intFlag)
+{
+    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) |= (1 << channel);
+}
+
+/**
+ * \brief   Disables an interrupt for the specified core.
+ *
+ * \param   baseAddr    Base address of thei CPSW Wrapper Module
+ * \param   core        Core number
+ * \param   channel     Channel number
+ * \param   intFlag     Interrupt to be disabled
+ *    'intFlag' can take one of the below values. \n
+ *          CPSW_CORE_INT_RX_THRESH - RX threshold interrupt \n
+ *          CPSW_CORE_INT_RX_PULSE - RX pulse interrupt \n
+ *          CPSW_CORE_INT_TX_PULSE - TX pulse interrupt \n
+ *          CPSW_CORE_INT_MISC - Miscellaneous interrupt
+ *
+ * \return  None
+ **/
+void CPSWWrCoreIntDisable(unsigned int baseAddr, unsigned int core,
+                          unsigned int channel, unsigned int intFlag)
+{
+    HWREG(baseAddr + CPSW_WR_C_RX_THRESH_EN(core) + intFlag) &=
+                                                            ~(1 << channel);
+}
+
+/**
+ * \brief   Returns the interrupt status of the core for the specified
+ *          channel
+ *
+ * \param   baseAddr    Base address of thei CPSW Wrapper Module
+ * \param   core        Core number
+ * \param   channel     Channel number
+ * \param   intFlag     Interrupt status to be read
+ *    'intFlag' can take one of the below values. \n
+ *          CPSW_CORE_INT_RX_THRESH - RX threshold interrupt \n
+ *          CPSW_CORE_INT_RX_PULSE - RX pulse interrupt \n
+ *          CPSW_CORE_INT_TX_PULSE - TX pulse interrupt \n
+ *          CPSW_CORE_INT_MISC - Miscellaneous interrupt
+ *
+ * \return  same as intFlag if the status is set
+ *          '0' if the status is cleared
+ **/
+unsigned int CPSWWrCoreIntStatusGet(unsigned int baseAddr, unsigned int core,
+                                    unsigned int channel, unsigned int intFlag)
+{
+    return (HWREG(baseAddr + CPSW_WR_C_RX_THRESH_STAT(core) + intFlag)
+            &  (1 << channel));
+}
+
+/**
+ * \brief   Returns the RGMII status requested.
+ *
+ * \param   baseAddr    Base address of the CPSW Wrapper Module
+ * \param   statFlag    Status to be checked
+ *    'statFlag' can take a combination of the below values. \n
+ *        CPSW_RGMII2_DUPLEX - Duplex of RGMII2 \n
+ *        CPSW_RGMII2_SPEED - Speed of RGMII2 \n
+ *        CPSW_RGMII2_LINK_STAT - Link Status of RGMII2 \n
+ *        CPSW_RGMII1_DUPLEX - Duplex of RGMII1 \n
+ *        CPSW_RGMII1_SPEED - Speed of RGMII1 \n
+ *        CPSW_RGMII1_LINK_STAT - Link Status of RGMII1 \n
+ *
+ *    The returned value can be compared agains the below values \n
+ *        CPSW_RGMII2_DUPLEX_FULL - RGMII2 full duplex \n
+ *        CPSW_RGMII2_DUPLEX_HALF - RGMII2 half duplex \n
+ *        CPSW_RGMII2_SPEED_10M - Speed is 10 Mbps \n
+ *        CPSW_RGMII2_SPEED_100M - Speed is 100 Mbps \n
+ *        CPSW_RGMII2_SPEED_1000M - Speed is 1000 Mbps \n
+ *        CPSW_RGMII2_LINK_UP - RGMII2 link is up\n
+ *        CPSW_RGMII2_LINK_DOWN - RGMII2 link is down \n
+ *        CPSW_RGMII1_DUPLEX_FULL - RGMII1 full duplex \n
+ *        CPSW_RGMII1_DUPLEX_HALF - RGMII1 half duplex \n
+ *        CPSW_RGMII1_SPEED_10M - Speed is 10 Mbps \n
+ *        CPSW_RGMII1_SPEED_100M - Speed is 100 Mbps \n
+ *        CPSW_RGMII1_SPEED_1000M - Speed is 1000 Mbps \n
+ *        CPSW_RGMII1_LINK_UP - RGMII1 link is up\n
+ *        CPSW_RGMII1_LINK_DOWN - RGMII1 link is down \n
+ *
+ * \return  Status of RGMII. Return value can be compared agains the same
+ *          statFlag passed.
+ **/
+unsigned int CPSWWrRGMIIStatusGet(unsigned int baseAddr, unsigned int statFlag)
+{
+    return (HWREG(baseAddr + CPSW_WR_RGMII_CTL) & statFlag);
+}
+
+/**
+ * \brief   Initializes the ALE. The ALE logic is reset and the ALE table
+ *          entries are cleared.
+ *
+ * \param   baseAddr    Base address of the ALE module
+ *
+ * \return  None
+ **/
+void CPSWALEInit(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) = (CPSW_ALE_CONTROL_CLEAR_TABLE
+                                          | CPSW_ALE_CONTROL_ENABLE_ALE);
+}
+
+/**
+ * \brief   Age Out Address Table. The Untouched ageable ALE table
+ *          entries are cleared.
+ *
+ * \param   baseAddr    Base address of the ALE module
+ *
+ * \return  None
+ **/
+void CPSWALEAgeOut(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_AGE_OUT_NOW;
+
+    while(CPSW_ALE_CONTROL_AGE_OUT_NOW & (HWREG(baseAddr + CPSW_ALE_CONTROL)));
+
+}
+
+/**
+ * \brief   Sets the Broadcast Packet Rate Limit
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   bplVal        The Broadcast Packet Rate Limit Value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEBroadcastRateLimitSet(unsigned int baseAddr, unsigned int portNum,
+                                  unsigned int bplVal)
+{
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &=
+                                         ~CPSW_ALE_PORTCTL0_BCAST_LIMIT;
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
+                            (bplVal << CPSW_ALE_PORTCTL0_BCAST_LIMIT_SHIFT);
+}
+
+/**
+ * \brief   Sets the Multicast Packet Rate Limit
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   mplVal        The Multicast Packet Rate Limit Value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEMulticastRateLimitSet(unsigned int baseAddr, unsigned int portNum,
+                                  unsigned int mplVal)
+{
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &=
+                                         ~CPSW_ALE_PORTCTL0_MCAST_LIMIT;
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
+                            (mplVal << CPSW_ALE_PORTCTL0_MCAST_LIMIT_SHIFT);
+}
+
+/**
+ * \brief   VLAN ID Ingress Check
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEVIDIngressCheckSet(unsigned int baseAddr, unsigned int portNum)
+{
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |=
+                                         CPSW_ALE_PORTCTL0_MCAST_LIMIT;
+}
+
+/**
+ * \brief   Sets the port state in the ALE for a given port
+ *
+ * \param   baseAddr    Base address of the ALE module
+ * \param   portNum     The port number
+ * \param   portState   The port state to be set
+ *    'portState' can take one of the below values \n
+ *        CPSW_ALE_PORT_STATE_FWD - ALE state is Forward \n
+ *        CPSW_ALE_PORT_STATE_LEARN - ALE state is Learn \n
+ *        CPSW_ALE_PORT_STATE_BLOCKED - ALE state is Blocked \n
+ *        CPSW_ALE_PORT_STATE_DISABLED - ALE state is Disabled
+ *
+ * \return  None
+ **/
+void CPSWALEPortStateSet(unsigned int baseAddr, unsigned int portNum,
+                         unsigned int portState)
+{
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) &=
+                                        ~CPSW_ALE_PORTCTL0_PORT_STATE;
+
+    HWREG(baseAddr + CPSW_ALE_PORTCTL(portNum)) |= portState;
+}
+
+/**
+ * \brief   Sets VLAN Aware mode for ALE to Flood if VLAN not found
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALEVLANAwareSet(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_ALE_VLAN_AWARE;
+}
+
+/**
+ * \brief   Clears VLAN Aware mode for ALE to drop packets
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALEVLANAwareClear(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) &= ~CPSW_ALE_CONTROL_ALE_VLAN_AWARE;
+}
+
+/**
+ * \brief   Configure Rate Limit to TX Mode
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALERateLimitTXMode(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_RATE_LIMIT_TX;
+}
+
+/**
+ * \brief   Configure Rate Limit to RX Mode
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALERateLimitRXMode(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) &= ~CPSW_ALE_CONTROL_RATE_LIMIT_TX;
+}
+
+/**
+ * \brief   Enable Rate Limit for ALE
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALERateLimitEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_ENABLE_RATE_LIMIT;
+}
+
+/**
+ * \brief   Disable Rate Limit for ALE
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALERateLimitDisable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) &= ~CPSW_ALE_CONTROL_ENABLE_RATE_LIMIT;
+}
+
+/**
+ * \brief   Enable MAC Authorization Mode for ALE
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALEAUTHModeSet(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_ENABLE_AUTH_MODE;
+}
+
+/**
+ * \brief   Disable MAC Authorization Mode for ALE
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ *
+ * \return  None
+ **/
+void CPSWALEAUTHModeClear(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) &= ~CPSW_ALE_CONTROL_ENABLE_AUTH_MODE;
+}
+
+/**
+ * \brief   Sets an ALE table entry
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ * \param   aleTblIdx   The Index of the table entry
+ * \param   aleEntryPtr The address of the entry to be set
+ *
+ * \return  None
+ **/
+void CPSWALETableEntrySet(unsigned int baseAddr, unsigned int aleTblIdx,
+                          unsigned int *aleEntryPtr)
+{
+    unsigned int cnt;
+
+    for (cnt = 0; cnt < ALE_ENTRY_WORDS; cnt++)
+    {
+        HWREG(baseAddr +  CPSW_ALE_TBLW(cnt)) =  *(aleEntryPtr + cnt);
+    }
+
+    HWREG(baseAddr +  CPSW_ALE_TBLCTL) =
+                                aleTblIdx | CPSW_ALE_TBLCTL_WRITE_RDZ;
+}
+
+/**
+ * \brief   Returns an ALE table entry
+ *
+ * \param   baseAddr    Base address of the ALE Module
+ * \param   aleTblIdx   The Index of the table entry
+ * \param   aleEntryPtr The address where the ALE entry to be written
+ *
+ * \return  None
+ **/
+void CPSWALETableEntryGet(unsigned int baseAddr, unsigned int aleTblIdx,
+                          unsigned int *aleEntryPtr)
+{
+    unsigned int cnt;
+
+    HWREG(baseAddr + CPSW_ALE_TBLCTL) = aleTblIdx;
+
+    for (cnt = 0; cnt < ALE_ENTRY_WORDS; cnt++)
+    {
+        *(aleEntryPtr + cnt) = HWREG(baseAddr + CPSW_ALE_TBLW(cnt));
+    }
+}
+
+/**
+ * \brief   Returns the prescale value for ALE. The input clock is divided
+ *          by this value to use in the broadcast/multicast rate limiters.
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ *
+ * \return  Prescale value
+ *
+ **/
+unsigned int CPSWALEPrescaleGet(unsigned int baseAddr)
+{
+    return (HWREG(baseAddr + CPSW_ALE_PRESCALE)
+            & CPSW_ALE_PRESCALE_ALE_PRESCALE);
+}
+
+/**
+ * \brief   Sets the prescale value for ALE. The input clock is divided
+ *          by this value to use in the broadcast/multicast rate limiters.
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   psVal         The prescale value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEPrescaleSet(unsigned int baseAddr, unsigned int psVal)
+{
+    HWREG(baseAddr + CPSW_ALE_PRESCALE) |= psVal
+                                   & CPSW_ALE_PRESCALE_ALE_PRESCALE ;
+}
+
+/**
+ * \brief   Sets the Unknown VLAN Force Untagged Egress
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   ueVal         The Unknown VLAN Fornce Untagged Egress value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEUnknownUntaggedEgressSet(unsigned int baseAddr, unsigned int ueVal)
+{
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) &=
+                      ~CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_FORCE_UNTA;
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) |=
+                      (ueVal << CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_FORCE_UNTA_SHIFT);
+}
+
+/**
+ * \brief   Sets the Unknown VLAN Registered Multicast Flood Mask
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   rfmVal        Unknown VLAN Registered Multicast Flood Mask Value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEUnknownRegFloodMaskSet(unsigned int baseAddr, unsigned int rfmVal)
+{
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) &=
+                      ~CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_MCAST_FLO;
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) |=
+                      (rfmVal << CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_MCAST_FLO_SHIFT);
+}
+
+/**
+ * \brief   Sets the Unknown VLAN UnRegistered Multicast Flood Mask
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   ufmVal        Unknown VLAN UnRegistered Multicast Flood Mask Value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEUnknownUnRegFloodMaskSet(unsigned int baseAddr, unsigned int ufmVal)
+{
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) &=
+                      ~CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_REG_MCAST;
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) |=
+                      (ufmVal << CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_REG_MCAST_SHIFT);
+}
+
+/**
+ * \brief   Sets the Unknown VLAN Member List
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ * \param   mlVal        Unknown VLAN UnRegistered Multicast Flood Mask Value
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEUnknownMemberListSet(unsigned int baseAddr, unsigned int mlVal)
+{
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) &=
+                        ~CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_VLAN_MEM;
+    HWREG(baseAddr + CPSW_ALE_UNKNOWN_VLAN) |=
+                        (mlVal << CPSW_ALE_UNKNOWN_VLAN_UNKNOWN_VLAN_MEM_SHIFT);
+}
+
+/**
+ * \brief   Enables the bypassing of the ALE logic
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEBypassEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) |= CPSW_ALE_CONTROL_ALE_BYPASS;
+}
+
+/**
+ * \brief   Disables the bypassing of the ALE logic
+ *
+ * \param   baseAddr      Base Address of the ALE module
+ *
+ * \return  None
+ *
+ **/
+void CPSWALEBypassDisable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_ALE_CONTROL) &= ~CPSW_ALE_CONTROL_ALE_BYPASS;
+}
+
+/**
+ * \brief   Enables the receive flow control for CPSW for a given port
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ * \param   portNum       The port number
+ *
+ * \return  None
+ *
+ **/
+void CPSWRxFlowControlEnable(unsigned int baseAddr, unsigned int portNum)
+{
+    HWREG(baseAddr + CPSW_SS_FLOW_CONTROL) |= (1 << portNum);
+}
+
+/**
+ * \brief   Disables the receive flow control for CPSW for a given port
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ * \param   portNum       The port number
+ *
+ * \return  None
+ *
+ **/
+void CPSWRxFlowControlDisable(unsigned int baseAddr, unsigned int portNum)
+{
+    HWREG(baseAddr + CPSW_SS_FLOW_CONTROL) &= ~(1 << portNum);
+}
+
+/**
+ * \brief   Enables the software idle mode, causing the switch fabric to stop
+ *          forward packets at the next start of packet.
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ *
+ * \return  None
+ *
+ **/
+void CPSWSoftwareIdleEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SS_SOFT_IDLE) |= CPSW_SS_SOFT_IDLE_SOFT_IDLE;
+}
+
+/**
+ * \brief   Disables the software idle mode, causing the switch fabric to
+ *          forward packets at the next start of packet.
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ *
+ * \return  None
+ *
+ **/
+void CPSWSoftwareIdleDisable(unsigned int baseAddr, unsigned int portNum)
+{
+    (void) portNum;
+    HWREG(baseAddr + CPSW_SS_SOFT_IDLE) &= ~CPSW_SS_SOFT_IDLE_SOFT_IDLE;
+}
+
+/**
+ * \brief   Enables the CPSW statistics for the given port
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ * \param   portNum       The port number
+ *
+ * \return  None
+ *
+ **/
+void CPSWStatisticsEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SS_STAT_PORT_EN) = CPSW_SS_STAT_PORT_EN_P0_STAT_EN
+                                             | CPSW_SS_STAT_PORT_EN_P1_STAT_EN
+                                             | CPSW_SS_STAT_PORT_EN_P2_STAT_EN;
+}
+
+/**
+ * \brief   Enables the VLAN aware mode for CPSW
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ *
+ * \return  None
+ *
+ **/
+void CPSWVLANAwareEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SS_CONTROL) |= CPSW_SS_CONTROL_VLAN_AWARE;
+}
+
+/**
+ * \brief   Disables the VLAN aware mode for CPSW
+ *
+ * \param   baseAddr      Base Address of the CPSW subsystem
+ *
+ * \return  None
+ *
+ **/
+void CPSWVLANAwareDisable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_SS_CONTROL) &= ~CPSW_SS_CONTROL_VLAN_AWARE;
+}
+
+/**
+ * \brief   Sets the ethernet address at the CPSW port
+ *
+ * \param   baseAddr      Base address of the CPSW Port Module registers
+ * \param   ethAddr       Start address of the 6 byte ethernet address
+ *
+ * \return  None
+ *
+ **/
+void CPSWPortSrcAddrSet(unsigned int baseAddr, unsigned char *ethAddr)
+{
+
+    HWREG(baseAddr + CPSW_PORT_SA_HI) =
+                   ethAddr[0]
+                   | (ethAddr[1] << CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_SHIFT)
+                   | (ethAddr[2] << CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_SHIFT)
+                   | (ethAddr[3] << CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_SHIFT);
+    HWREG(baseAddr + CPSW_PORT_SA_LO) =
+                   ethAddr[4]
+                   | (ethAddr[5] << CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_SHIFT);
+}
+
+/**
+ * \brief   Sets Dual Mac Mode for CPSW Port0
+ *
+ * \param   baseAddr      Base address of the CPSW Host Port Module registers
+ *
+ * \return  None
+ *
+ **/
+void CPSWHostPortDualMacModeSet(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_PORT_TX_IN_CTL) &= ~CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL;
+    HWREG(baseAddr + CPSW_PORT_TX_IN_CTL) |=
+                              CPSW_PORT_P0_TX_IN_CTL_TX_IN_DUAL_MAC;
+}
+
+/**
+ * \brief   Configures Port VLAN
+ *
+ * \param   baseAddr      Base address of the CPSW Port Module registers
+ * \param   vlanId        VLAN ID to be set
+ * \param   cfiBit        CFI value to be set
+ * \param   vlanPri       Port VLAN priority
+ *            'vlanId' can take a value from 0 to 0xFFF \n
+ *            'cfiBit' can be either 0 or 1. \n
+ *            'vlanPri' can be any value between and including 0 and 7.
+ *
+ * \return  None
+ *
+ **/
+void CPSWPortVLANConfig(unsigned int baseAddr, unsigned int vlanId,
+                        unsigned int cfiBit, unsigned int vlanPri)
+{
+    HWREG(baseAddr + CPSW_PORT_PORT_VLAN) = vlanId
+                           | (cfiBit << CPSW_PORT_P2_PORT_VLAN_PORT_CFI_SHIFT)
+                           | (vlanPri << CPSW_PORT_P2_PORT_VLAN_PORT_PRI_SHIFT);
+}
+
+/**
+ * \brief   Returns the requested CPSW Statistics
+ *
+ * \param   baseAddr      Base address of the CPSW Status Module registers.
+ * \param   statReg       Statistics Register to be read
+ *
+ * \return  The requested statistics
+ *
+ **/
+unsigned int CPSWStatisticsGet(unsigned int baseAddr, unsigned int statReg)
+{
+    return (HWREG(baseAddr + statReg));
+}
+
+/**
+ * \brief   Resets the CPDMA
+ *
+ * \param   baseAddr      Base address of the CPDMA Module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMAReset(unsigned int baseAddr)
+{
+    unsigned int cnt;
+
+    /* Reset the CPDMA */
+    HWREG(baseAddr + CPSW_CPDMA_CPDMA_SOFT_RESET) =
+                     CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET;
+
+    /* Wait till the reset completes */
+    while(HWREG(baseAddr + CPSW_CPDMA_CPDMA_SOFT_RESET)
+          & CPSW_CPDMA_CPDMA_SOFT_RESET_SOFT_RESET);
+
+    /* Initialize all the header descriptor pointer registers */
+    for(cnt =  0; cnt< CPSW_MAX_HEADER_DESC; cnt++)
+    {
+        HWREG(baseAddr + CPSW_CPDMA_TX_HDP(cnt)) = 0;
+        HWREG(baseAddr + CPSW_CPDMA_RX_HDP(cnt)) = 0;
+        HWREG(baseAddr + CPSW_CPDMA_TX_CP(cnt)) = 0;
+        HWREG(baseAddr + CPSW_CPDMA_RX_CP(cnt)) = 0;
+    }
+}
+
+/**
+ * \brief   Enables the TXPULSE Interrupt Generation.
+ *
+ * \param   baseAddr      Base address of the CPDMA Module registers.
+ * \param   channel       Channel number for which interrupt to be enabled
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMATxIntEnable(unsigned int baseAddr, unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_TX_INTMASK_SET) |= (1 << channel);
+}
+
+/**
+ * \brief   Enables the RXPULSE Interrupt Generation.
+ *
+ * \param   baseAddr      Base address of the CPDMA Module registers.
+ * \param   channel       Channel number for which interrupt to be enabled
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxIntEnable(unsigned int baseAddr, unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_INTMASK_SET) |= (1 << channel);
+}
+
+/**
+ * \brief   Disables the TXPULSE Interrupt Generation.
+ *
+ * \param   baseAddr      Base address of the CPDMA Module registers.
+ * \param   channel       Channel number for which interrupt to be disabled
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMATxIntDisable(unsigned int baseAddr, unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_TX_INTMASK_CLEAR) |= (1 << channel);
+
+}
+
+/**
+ * \brief   Disables the RXPULSE Interrupt Generation.
+ *
+ * \param   baseAddr      Base address of the CPDMA Module registers.
+ * \param   channel       Channel number for which interrupt to be disabled
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxIntDisable(unsigned int baseAddr, unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_INTMASK_CLEAR) |= (1 << channel);
+
+}
+
+/**
+ * \brief   API to enable the transmit in the TX Control Register.
+ *          After the transmit is enabled, any write to TXHDP of
+ *          a channel will start transmission
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMATxEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_TX_CONTROL) = CPSW_CPDMA_TX_CONTROL_TX_EN;
+}
+
+/**
+ * \brief   API to enable the receive in the RX Control Register.
+ *          After the receive is enabled, and write to RXHDP of
+ *          a channel, the data can be received in the destination
+ *          specified by the corresponding RX buffer descriptor.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_CONTROL) = CPSW_CPDMA_RX_CONTROL_RX_EN;
+}
+
+/**
+ * \brief   API to write the TX HDP register. If transmit is enabled,
+ *          write to the TX HDP will immediately start transmission.
+ *          The data will be taken from the buffer pointer of the TX buffer
+ *          descriptor written to the TX HDP
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   descHdr       Address of the TX buffer descriptor
+ * \param   channel       Channel Number
+ *
+ * \return  None
+ *
+ **/
+#include <bsp.h>
+void CPSWCPDMATxHdrDescPtrWrite(unsigned int baseAddr, unsigned int descHdr,
+                                unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_TX_HDP(channel)) = descHdr;
+}
+
+/**
+ * \brief   API to write the RX HDP register. If receive is enabled,
+ *          write to the RX HDP will enable data reception to point to
+ *          the corresponding RX buffer descriptor's buffer pointer.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   descHdr       Address of the RX buffer descriptor
+ * \param   channel       Channel Number
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxHdrDescPtrWrite(unsigned int baseAddr, unsigned int descHdr,
+                                unsigned int channel)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_HDP(channel)) = descHdr;
+}
+
+/**
+ * \brief   Writes the DMA End Of Interrupt Vector.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   eoiFlag       Type of interrupt to acknowledge to the CPDMA
+ *            'eoiFlag' can take the following values \n
+ *                CPSW_EOI_TX_PULSE - TX Pulse Interrupt \n
+ *                CPSW_EOI_RX_PULSE - RX Pulse Interrupt \n
+ *                CPSW_EOI_RX_THRESH_PULSE - RX Pulse Threshold Interrupt \n
+ *                CPSW_EOI_MISC_PULSE - Misc Interrupt \n
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMAEndOfIntVectorWrite(unsigned int baseAddr, unsigned int eoiFlag)
+{
+    /* Acknowledge the CPDMA */
+    HWREG(baseAddr + CPSW_CPDMA_CPDMA_EOI_VECTOR) = eoiFlag;
+}
+
+/**
+ * \brief  Reads the RX Completion Pointer for a specific channel
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   channel       Channel Number.
+ *
+ * \return  RX Completion Pointer value.
+ *
+ **/
+unsigned int CPSWCPDMATxCPRead(unsigned int baseAddr, unsigned int channel)
+{
+    return HWREG(baseAddr + CPSW_CPDMA_TX_CP(channel));
+}
+
+/**
+ * \brief   Writes the the TX Completion Pointer for a specific channel
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   channel       Channel Number.
+ * \param   comPtr        Completion Pointer Value to be written
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMATxCPWrite(unsigned int baseAddr, unsigned int channel,
+                        unsigned int comPtr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_TX_CP(channel)) = comPtr;
+}
+
+/**
+ * \brief  Reads the RX Completion Pointer for a specific channel
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   channel       Channel Number.
+ *
+ * \return  RX Completion Pointer value.
+ *
+ **/
+unsigned int CPSWCPDMARxCPRead(unsigned int baseAddr, unsigned int channel)
+{
+    return HWREG(baseAddr + CPSW_CPDMA_RX_CP(channel));
+}
+
+/**
+ * \brief   Writes the the RX Completion Pointer for a specific channel
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   channel       Channel Number.
+ * \param   comPtr        Completion Pointer Value to be written
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxCPWrite(unsigned int baseAddr, unsigned int channel,
+                        unsigned int comPtr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_CP(channel)) = comPtr;
+}
+
+/**
+ * \brief   Set the free buffers for a specific channel
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   channel       Channel Number.
+ * \param   nBuf          Number of free buffers
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMANumFreeBufSet(unsigned int baseAddr, unsigned int channel,
+                            unsigned int nBuf)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_FREEBUFFER(channel)) = nBuf;
+}
+
+/**
+ * \brief   Returns the CPDMA Status.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers.
+ * \param   statFlag      The status flags to be read
+ *     'statFlag' can take one of the following values \n
+ *            CPDMA_STAT_IDLE - to check if CPDMA is idle. \n
+ *            CPDMA_STAT_TX_HOST_ERR_CODE - TX host error code. \n
+ *            CPDMA_STAT_TX_HOST_ERR_CHAN - TX host error channel. \n
+ *            CPDMA_STAT_RX_HOST_ERR_CODE - RX host error code. \n
+ *            CPDMA_STAT_RX_HOST_ERR_CHAN - RX host error channel. \n
+ *
+ * \return  the DMA status for the status flag passed.
+ *          The return values for CPDMA_STAT_IDLE are, \n
+ *            CPDMA_STAT_IDLE - CPDMA is in idle state \n
+ *            CPDMA_STAT_NOT_IDLE - CPDMA is not in idle state \n
+ *
+ *          The return values for CPDMA_STAT_TX_HOST_ERR_CODE are, \n
+ *            CPDMA_STAT_TX_NO_ERR - No error \n
+ *            CPDMA_STAT_TX_SOP_ERR - SOP error \n
+ *            CPDMA_STAT_TX_OWN_ERR - Ownership bit not
+ *                                                  set in SOP buffer \n
+ *            CPDMA_STAT_TX_ZERO_DESC - Zero Next Buffer
+ *                                       Descriptor Pointer Without EOP \n
+ *            CPDMA_STAT_TX_ZERO_BUF_PTR - Zero Buffer Pointer \n
+ *            CPDMA_STAT_TX_ZERO_BUF_LEN - Zero Buffer Length \n
+ *            CPDMA_STAT_TX_PKT_LEN_ERR - Packet Length Error \n
+ *
+ *          The return values for CPDMA_STAT_RX_HOST_ERR_CODE are, \n
+ *            CPDMA_STAT_RXi_NO_ERR - No error \n
+ *            CPDMA_STAT_RX_OWN_NOT_SET - Ownership bit not set in
+                                          input buffer \n
+ *            CPDMA_STAT_RX_ZERO_BUF_PTR - Zero Buffer Pointer\n
+ *            CPDMA_STAT_RX_ZERO_BUF_LEN - Zero Buffer Length on
+ *                                       non-SOP descriptor \n
+ *            CPDMA_STAT_RX_SOP_BUF_LEN_ERR - SOP buffer length not
+ *                                       greater than offset\n
+ *
+ **/
+unsigned int CPSWCPDMAStatusGet(unsigned int baseAddr, unsigned int statFlag)
+{
+    return (((HWREG(baseAddr + CPSW_CPDMA_DMASTATUS)) & statFlag)
+            >> (statFlag & CPDMA_ERR_CHANNEL_POS));
+}
+
+/**
+ * \brief   Configures the CPDMA module by writing the configuration value
+ *          to the DMA control register.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   cfg           CPDMA configuration written to control register
+ *     'cfg' shall be CPDMA_CFG(tx_rlim, rx_cef, cmd_idle,
+ *                              rx_offlen_blk, rx_own, tx_ptype). \n
+ *        The parameter 'tx_rlim' to CPDMA_CFG can take one of the below
+ *        values, showing which all channels are rate-limited. \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_6 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_5 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_4 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_3 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_2 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_1 \n
+ *            CPDMA_CFG_TX_RATE_LIM_CH_7_TO_0 \n
+ *        The parameter 'rx_cef' to CPDMA_CFG can take one of the below
+ *        values \n
+ *            CPDMA_CFG_COPY_ERR_FRAMES - To copy error frames to memory \n
+ *            CPDMA_CFG_NO_COPY_ERR_FRAMES - Not to copy error frames \n
+ *        The parameter 'cmd_idle' to CPDMA_CFG can take one of the below
+ *        values \n
+ *            CPDMA_CFG_IDLE_COMMAND - Idle commanded \n
+ *            CPDMA_CFG_IDLE_COMMAND_NONE - Idle not commanded \n
+ *        The parameter 'rx_offlen_blk' to CPDMA_CFG can take one of the below
+ *        values \n
+ *            CPDMA_CFG_BLOCK_RX_OFF_LEN_WRITE - Block the DMA writes to the
+ *                                               offset/length field during
+ *                                               packet processing. \n
+ *            CPDMA_CFG_NOT_BLOCK_RX_OFF_LEN_WRITE - Do not Block the DMA writes
+ *                                              to the offset/length field during
+ *                                              packet processing. \n
+ *        The parameter 'rx_own' to CPDMA_CFG can take one of the below
+ *        values \n
+ *            CPDMA_CFG_RX_OWN_1 - The CPDMA writes 1 to the ownership bit at
+ *                                 the end of packet processing. \n
+ *            CPDMA_CFG_RX_OWN_0 - The CPDMA writes 0 to the ownership bit at
+ *                                 the end of packet processing. \n
+ *        The parameter 'tx_ptype' to CPDMA_CFG can take one of the below
+ *        values \n
+ *            CPDMA_CFG_TX_PRI_ROUND_ROBIN - The next channel for transmit is
+ *                                           chosen round-robin. \n
+ *            CPDMA_CFG_TX_PRI_FIXED - The next channel for transmit is
+ *                                     chosen priority based, channel 7 with the
+ *                                     highest priority \n
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMAConfig(unsigned int baseAddr, unsigned int cfg)
+{
+    HWREG(baseAddr + CPSW_CPDMA_DMACONTROL) = cfg;
+}
+
+/**
+ * \brief   Enable the command idle mode for CPDMA. When this API is called, the
+ *          CPSW stops all the reception and transmission. However, if receiving
+ *          the current frame will be received completely before going to the idle
+ *          state. Also, while transmitting, the contents in the fifo will be sent
+ *          fully.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMACmdIdleEnable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_DMACONTROL) |= CPSW_CPDMA_DMACONTROL_CMD_IDLE;
+
+    /* Wait till the state changes to idle */
+    while((HWREG(baseAddr + CPSW_CPDMA_DMASTATUS) & CPSW_CPDMA_DMASTATUS_IDLE)
+          != CPSW_CPDMA_DMASTATUS_IDLE);
+}
+
+/**
+ * \brief   Disable the command idle mode for CPDMA.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMACmdIdleDisable(unsigned int baseAddr)
+{
+    HWREG(baseAddr + CPSW_CPDMA_DMACONTROL) &= ~CPSW_CPDMA_DMACONTROL_CMD_IDLE;
+}
+
+/**
+ * \brief   Sets the RX buffer offset value. The RX buffer offset will be
+ *          written by the port into each frame SOP buffer descriptor
+ *          buffer_offset field. The frame data will begin after the
+ *          rx_buffer_offset value of bytes. This value will be used for
+ *          all the channels .
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   bufOff        Buffer offset value
+ *
+ * \return  None
+ *
+ **/
+void CPSWCPDMARxBufOffsetSet(unsigned int baseAddr, unsigned int bufOff)
+{
+    HWREG(baseAddr + CPSW_CPDMA_RX_BUFFER_OFFSET) = bufOff;
+}
+
+/**
+ * \brief   Returns the raw transmit interrupt pending status.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   chanMask      Channel Mask
+ *    'chanMask' can be given for one or more channels. \n
+ *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
+ *         and 7th channel etc. \n
+ *
+ * \return  Raw receive interrupt status \n
+ *          bits for the 'chanMask' will be set if interrupt is pending \n
+ *          bits for the 'chanMask' will be clear if interrupt is not
+ *                                                              pending \n
+ *
+ **/
+unsigned int CPSWCPDMATxIntStatRawGet(unsigned int baseAddr,
+                                      unsigned int chanMask)
+{
+    return (HWREG(baseAddr + CPSW_CPDMA_TX_INTSTAT_RAW) & chanMask);
+}
+
+/**
+ * \brief   Returns the masked transmit interrupt pending status.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   chanMask      Channel Mask
+ *    'chanMask' can be given for one or more channels. \n
+ *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
+ *         and 7th channel etc. \n
+ *
+ * \return  Masked transmit interrupt status \n
+ *          bits for the 'chanMask' will be set if interrupt is pending \n
+ *          bits for the 'chanMask' will be cleared if interrupt is not
+ *                                                              pending \n
+ *
+ **/
+unsigned int CPSWCPDMATxIntStatMaskedGet(unsigned int baseAddr,
+                                         unsigned int chanMask)
+{
+    return (HWREG(baseAddr + CPSW_CPDMA_TX_INTSTAT_MASKED) & chanMask);
+}
+
+/**
+ * \brief   Returns the raw receive interrupt pending status.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   chanMask      Channel Mask
+ * \param   intType       Interrupt type
+ *    'chanMask' can be given for one or more channels. \n
+ *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
+ *         and 7th channel etc. \n
+ *    'intType' can take one of the following values. \n
+ *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n
+ *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n
+ *
+ * \return  Raw receive interrupt status \n
+ *          bits for the 'chanMask' will be set if interrupt is pending \n
+ *          bits for the 'chanMask' will be cleared if interrupt is not
+ *                                                              pending \n
+ *
+ **/
+unsigned int CPSWCPDMARxIntStatRawGet(unsigned int baseAddr,
+                                      unsigned int chanMask,
+                                      unsigned int intType)
+{
+    return ((HWREG(baseAddr + CPSW_CPDMA_RX_INTSTAT_RAW) >> intType)
+             & chanMask);
+}
+
+/**
+ * \brief   Returns the masked receive interrupt pending status.
+ *
+ * \param   baseAddr      Base Address of the CPDMA module registers
+ * \param   chanMask      Channel Mask
+ * \param   intType       Interrupt type
+ *    'chanMask' can be given for one or more channels. \n
+ *         0x01- for 0th channel, 0x80 for 7th channel, 0x81 for both 0th
+ *         and 7th channel etc. \n
+ *    'intType' can take one of the following values. \n
+ *         CPDMA_RX_INT_THRESH_PEND - RX threshold interrupt pending \n
+ *         CPDMA_RX_INT_PULSE_PEND - RX pulse interrupt pending \n
+ *
+ * \return  Masked receive interrupt status \n
+ *          bits for the 'chanMask' will be set if interrupt is pending \n
+ *          bits for the 'chanMask' will be cleared if interrupt is not
+ *                                                              pending \n
+ *
+ **/
+unsigned int CPSWCPDMARxIntStatMaskedGet(unsigned int baseAddr,
+                                         unsigned int chanMask,
+                                         unsigned int intType)
+{
+    return ((HWREG(baseAddr + CPSW_CPDMA_RX_INTSTAT_MASKED) >> intType)
+             & chanMask);
+}
+
+/**
+ * \brief   Saves the CPSW register context. This can be used while going
+ *          to power down mode where CPSW power will be cut down.
+ *
+ * \param   contextPtr   Pointer to the structure where CPSW register context
+ *                       need to be saved.
+ *
+ * \return  None
+ *
+ **/
+void CPSWContextSave(CPSWCONTEXT *contextPtr)
+{
+    unsigned int idx;
+    unsigned int *cppiDest = (unsigned int*)contextPtr->cppiRamBase;
+
+    CPSWCPDMACmdIdleEnable(contextPtr->cpdmaBase);
+
+    /* Restore the CPPI RAM contents */
+    for(idx = 0; idx < (CPSW_SIZE_CPPI_RAM / 4); idx++, cppiDest++)
+    {
+        contextPtr->cppiRam[idx] = *cppiDest;
+    }
+
+    contextPtr->aleCtrl = HWREG(contextPtr->aleBase + CPSW_ALE_CONTROL);
+    contextPtr->alePortCtl[0] = HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(0));
+    contextPtr->alePortCtl[1] = HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(1));
+    contextPtr->alePortCtl[2] = HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(2));
+
+    for(idx = 0; idx < CPSW_MAX_NUM_ALE_ENTRY; idx++)
+    {
+        CPSWALETableEntryGet(contextPtr->aleBase, idx,
+                             &(contextPtr->aleEntry[idx * 3]));
+    }
+
+    contextPtr->ssStatPortEn = HWREG(contextPtr->ssBase + CPSW_SS_STAT_PORT_EN);
+    contextPtr->port1SaHi = HWREG(contextPtr->port1Base + CPSW_PORT_SA_HI);
+    contextPtr->port1SaLo = HWREG(contextPtr->port1Base + CPSW_PORT_SA_LO);
+    contextPtr->port2SaHi = HWREG(contextPtr->port2Base + CPSW_PORT_SA_HI);
+    contextPtr->port2SaLo = HWREG(contextPtr->port2Base + CPSW_PORT_SA_LO);
+    contextPtr->port1TxInCtl = HWREG(contextPtr->port1Base + CPSW_PORT_TX_IN_CTL);
+    contextPtr->port2TxInCtl = HWREG(contextPtr->port2Base + CPSW_PORT_TX_IN_CTL);
+    contextPtr->port1Vlan = HWREG(contextPtr->port1Base + CPSW_PORT_PORT_VLAN);
+    contextPtr->port2Vlan = HWREG(contextPtr->port2Base + CPSW_PORT_PORT_VLAN);
+    contextPtr->cpdmaRxFB = HWREG(contextPtr->cpdmaBase
+                                  + CPSW_CPDMA_RX_FREEBUFFER(0));
+    contextPtr->cpdmaTxCtl = HWREG(contextPtr->cpdmaBase
+                                   + CPSW_CPDMA_TX_CONTROL);
+    contextPtr->cpdmaRxCtl = HWREG(contextPtr->cpdmaBase
+                                   + CPSW_CPDMA_RX_CONTROL);
+    contextPtr->cpdmaRxHdp = HWREG(contextPtr->cpdmaBase
+                                   + CPSW_CPDMA_RX_HDP(0));
+    contextPtr->txIntMaskSet = HWREG(contextPtr->cpdmaBase
+                                     + CPSW_CPDMA_TX_INTMASK_SET);
+    contextPtr->wrCoreIntTxPulse = HWREG(contextPtr->wrBase
+                                         + CPSW_WR_C_RX_THRESH_EN(0) + 0x04);
+    contextPtr->rxIntMaskSet = HWREG(contextPtr->cpdmaBase
+                                     + CPSW_CPDMA_RX_INTMASK_SET);
+    contextPtr->wrCoreIntRxPulse = HWREG(contextPtr->wrBase
+                                         + CPSW_WR_C_RX_THRESH_EN(0) + 0x08);
+    contextPtr->sl1MacCtl = HWREG(contextPtr->sl1Base + CPSW_SL_MACCONTROL);
+    contextPtr->sl2MacCtl = HWREG(contextPtr->sl2Base + CPSW_SL_MACCONTROL);
+}
+
+/**
+ * \brief   Restores the CPSW register context. This can be used while coming
+ *          back from power down mode where CPSW power will be cut down.
+ *
+ * \param   contextPtr   Pointer to the structure where CPSW register context
+ *                       need to be restored from.
+ *
+ * \return  None
+ *
+ **/
+void CPSWContextRestore(CPSWCONTEXT *contextPtr)
+{
+    unsigned int idx;
+    unsigned int *cppiDest = (unsigned int*)contextPtr->cppiRamBase;
+
+    /* Restore the CPPI RAM contents */
+    for(idx = 0; idx < (CPSW_SIZE_CPPI_RAM / 4); idx++, cppiDest++)
+    {
+        *cppiDest = contextPtr->cppiRam[idx] ;
+    }
+
+    HWREG(contextPtr->aleBase + CPSW_ALE_CONTROL) = contextPtr->aleCtrl;
+    HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(0)) = contextPtr->alePortCtl[0];
+    HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(1)) = contextPtr->alePortCtl[1];
+    HWREG(contextPtr->aleBase + CPSW_ALE_PORTCTL(2)) = contextPtr->alePortCtl[2];
+
+    for(idx = 0; idx < CPSW_MAX_NUM_ALE_ENTRY; idx++)
+    {
+        CPSWALETableEntrySet(contextPtr->aleBase, idx,
+                             &(contextPtr->aleEntry[idx * 3]));
+    }
+
+    HWREG(contextPtr->ssBase + CPSW_SS_STAT_PORT_EN) = contextPtr->ssStatPortEn;
+    HWREG(contextPtr->port1Base + CPSW_PORT_SA_HI) = contextPtr->port1SaHi;
+    HWREG(contextPtr->port1Base + CPSW_PORT_SA_LO) = contextPtr->port1SaLo;
+    HWREG(contextPtr->port2Base + CPSW_PORT_SA_HI) = contextPtr->port2SaHi;
+    HWREG(contextPtr->port2Base + CPSW_PORT_SA_LO) = contextPtr->port2SaLo;
+    HWREG(contextPtr->port1Base + CPSW_PORT_TX_IN_CTL) = contextPtr->port1TxInCtl;
+    HWREG(contextPtr->port2Base + CPSW_PORT_TX_IN_CTL) = contextPtr->port2TxInCtl;
+    HWREG(contextPtr->port1Base + CPSW_PORT_PORT_VLAN) = contextPtr->port1Vlan;
+    HWREG(contextPtr->port2Base + CPSW_PORT_PORT_VLAN) = contextPtr->port2Vlan;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_FREEBUFFER(0)) =
+                                contextPtr->cpdmaRxFB;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_CONTROL)
+                                 = contextPtr->cpdmaTxCtl;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_CONTROL)
+                                 = contextPtr->cpdmaRxCtl;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_HDP(0))
+                                 = contextPtr->cpdmaRxHdp;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_TX_INTMASK_SET)
+                                 = contextPtr->txIntMaskSet;
+    HWREG(contextPtr->wrBase + CPSW_WR_C_RX_THRESH_EN(0) + 0x04)
+                                 = contextPtr->wrCoreIntTxPulse;
+    HWREG(contextPtr->cpdmaBase + CPSW_CPDMA_RX_INTMASK_SET)
+                                 = contextPtr->rxIntMaskSet;
+    HWREG(contextPtr->wrBase + CPSW_WR_C_RX_THRESH_EN(0) + 0x08)
+                                 =  contextPtr->wrCoreIntRxPulse;
+    HWREG(contextPtr->sl1Base + CPSW_SL_MACCONTROL) = contextPtr->sl1MacCtl;
+    HWREG(contextPtr->sl2Base + CPSW_SL_MACCONTROL) = contextPtr->sl2MacCtl;
+}
+
+
diff --git a/cpsw/src/netif/cpsw_bb.c b/cpsw/src/netif/cpsw_bb.c
new file mode 100755
index 0000000..a35a6f0
--- /dev/null
+++ b/cpsw/src/netif/cpsw_bb.c
@@ -0,0 +1,161 @@
+/**
+ * \file   cpsw.c
+ *
+ * \brief  This file contains functions which configure CPSW instance
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#include "soc_AM335x.h"
+#include "hw_control_AM335x.h"
+#include "hw_types.h"
+#include "beaglebone.h"
+#include "hw_cm_per.h"
+
+/******************************************************************************
+**                       INTERNAL MACRO DEFINITIONS
+******************************************************************************/
+#define CPSW_MII_SEL_MODE                     (0x00u)
+#define CPSW_MDIO_SEL_MODE                    (0x00u)
+#define LEN_MAC_ADDR                          (0x06u)
+#define OFFSET_MAC_ADDR                       (0x30u)
+
+/******************************************************************************
+**                          FUNCTION DEFINITIONS
+******************************************************************************/
+/**
+ * \brief   This function selects the CPSW pins for use in MII mode.
+ *          
+ * \param   None
+ *
+ * \return  None.
+ *
+ */
+void CPSWPinMuxSetup(void)
+{
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
+        CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =  CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =  
+         CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =  CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) =  CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) =  CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) =  CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) = 
+          CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) = 
+         CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) = 
+         CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) = 
+         CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =  
+         CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =  
+         CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
+               CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
+               CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE | CPSW_MII_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
+         CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE 
+         | CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
+         | CPSW_MDIO_SEL_MODE;
+    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
+         CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL | CPSW_MDIO_SEL_MODE;
+}
+
+/**
+ * \brief   Enables CPSW clocks
+ *
+ * \param   None
+ *
+ * \return  None.
+ */
+void CPSWClkEnable(void)
+{
+    HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL) =
+                      CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE;
+
+    while(0 != (HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
+                & CM_PER_CPGMAC0_CLKCTRL_IDLEST));
+ 
+    HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL) =
+                      CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
+
+    while(0 == (HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)
+                & CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK));
+} 
+
+/**
+ * \brief   This function sets the MII mode for both ports
+ *
+ * \param   None 
+ *
+ * \return  None.
+ */
+void EVMPortMIIModeSelect(void)
+{
+    /* Select MII, Internal Delay mode */
+    HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0x00;   
+}
+
+/**
+ * \brief   This function returns the MAC address for the EVM
+ *
+ * \param   addrIdx    the MAC address index. 
+ * \param   macAddr    the Pointer where the MAC address shall be stored
+ *     'addrIdx' can be either 0 or 1
+ *
+ * \return  None.
+ */
+void EVMMACAddrGet(unsigned int addrIdx, unsigned char *macAddr)
+{
+    macAddr[0] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(addrIdx)) 
+                   >> 8) & 0xFF;
+    macAddr[1] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(addrIdx)))
+                  & 0xFF;
+    macAddr[2] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(addrIdx))
+                   >> 24) & 0xFF;
+    macAddr[3] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(addrIdx))
+                   >> 16) & 0xFF;
+    macAddr[4] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(addrIdx))
+                   >> 8) & 0xFF;
+    macAddr[5] =  (HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(addrIdx)))
+                  & 0xFF;
+}
+
+/****************************** End Of File *********************************/
diff --git a/cpsw/src/netif/cpswif.c b/cpsw/src/netif/cpswif.c
new file mode 100755
index 0000000..9ff45b0
--- /dev/null
+++ b/cpsw/src/netif/cpswif.c
@@ -0,0 +1,2999 @@
+/**
+ * @file - cpswif.c
+ * lwIP Ethernet interface for CPSW port
+ *
+ */
+
+/**
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ *
+ * This file is dervied from the "ethernetif.c" skeleton Ethernet network
+ * interface driver for lwIP.
+ */
+#include <semaphore.h>
+#include <bsp.h>
+#include <sched.h>
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "netif/etharp.h"
+#include "netif/ppp/pppoe.h"
+#include "lwip/err.h"
+#include "netif/cpswif.h"
+#include "arch/cc.h"
+
+/* DriverLib Header Files required for this interface driver. */
+#include "cpsw.h"
+#include "mdio.h"
+#include "delay.h"
+#include "phy.h"
+#include "cache.h"
+
+#include "lwiplib.h"
+
+/* CPPI RAM size in bytes */
+#ifndef SIZE_CPPI_RAM
+#define SIZE_CPPI_RAM                            0x2000
+#endif
+
+#define SIZEOF_STRUCT_PBUF        LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))
+
+#define PORT_1                                   0x0
+#define PORT_2                                   0x1
+#define PORT_0_MASK                              0x1
+#define PORT_1_MASK                              0x2
+#define PORT_2_MASK                              0x4
+#define HOST_PORT_MASK                           PORT_0_MASK
+#define SLAVE_PORT_MASK(slv_port_num)            (1 << slv_port_num)
+#define PORT_MASK                                (0x7)
+#define INDV_PORT_MASK(slv_port_num)             (1 << slv_port_num)
+
+#define ENTRY_TYPE                               0x30
+#define ENTRY_TYPE_IDX                           7
+#define ENTRY_FREE                               0
+
+/* MDIO input and output frequencies in Hz */
+#define MDIO_FREQ_INPUT                          125000000
+#define MDIO_FREQ_OUTPUT                         1000000
+
+#define CPDMA_BUF_DESC_OWNER                     0x20000000
+#define CPDMA_BUF_DESC_SOP                       0x80000000
+#define CPDMA_BUF_DESC_EOP                       0x40000000
+#define CPDMA_BUF_DESC_EOQ                       0x10000000
+#define CPDMA_BUF_DESC_FROM_PORT                 0x70000
+#define CPDMA_BUF_DESC_FROM_PORT_SHIFT           16
+#define CPDMA_BUF_DESC_TO_PORT(port)             ((port << 16) | 0x100000)
+#define CPDMA_BD_LEN_MASK                        0xFFFF
+#define CPDMA_BD_PKTLEN_MASK                     0xFFFF
+
+#define MAX_TRANSFER_UNIT                        1500
+#define PBUF_LEN_MAX                             1520
+
+#define MIN_PKT_LEN                              60
+
+/* Define those to better describe the network interface. */
+#define IFNAME0                                  'e'
+#define IFNAME1                                  'n'
+
+#define MASK_LOWER_4BITS_BYTE                    (0x0F)
+#define MASK UPPER_4BITS_BYTE                    (0xF0)
+
+#define MASK_BROADCAST_ADDR                      (0xFF)
+#define MASK_MULTICAST_ADDR                      (0x01)
+
+#define ALE_ENTRY_VLAN                           0x20
+#define ALE_ENTRY_VLANUCAST                      0x30
+#define ALE_ENTRY_UCAST                          0x10
+#define ALE_ENTRY_MCAST                          0xD0
+#define ALE_ENTRY_OUI                            (0x80)
+#define ALE_ENTRY_ADDR                           (0x10)
+#define ALE_ENTRY_VLAN_ADDR                      (0x30)
+#define ALE_VLAN_ENTRY_MEMBER_LIST               0
+#define ALE_VLAN_ENTRY_FRC_UNTAG_EGR             3
+#define ALE_VLAN_ENTRY_MCAST_UNREG               (1)
+#define ALE_VLAN_ENTRY_MCAST_REG                 (2)
+#define ALE_VLAN_ENTRY_ID                        (3)
+#define ALE_VLAN_ID_MASK                         (0x0FFF)
+#define ALE_VLAN_ENTRY_ID_BIT0_BIT7              6
+#define ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11        7
+#define ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11_ALIGN  (0x08)
+#define ALE_VLANUCAST_ENTRY_ID_BIT0_BIT7         6
+#define ALE_VLANUCAST_ENTRY_TYPE_ID_BIT8_BIT11   7
+#define ALE_UCAST_ENTRY_TYPE                     7
+#define ALE_UCAST_TYPE_MASK                      (0xC0)
+#define ALE_UCAST_TYPE_SHIFT                     (6)
+#define ALE_UCAST_TYPE_PERSISTANT                (0x00)
+#define ALE_UCAST_TYPE_UNTOUCHED                 (0x40)
+#define ALE_UCAST_TYPE_OUI                       (0x80)
+#define ALE_UCAST_TYPE_TOUCHED                   (0xC0)
+#define ALE_UCAST_ENTRY_DLR_PORT_BLK_SEC         8
+#define ALE_UCAST_ENTRY_DLR_BLK_SEC_MASK         (0x03)
+#define ALE_UCAST_ENTRY_PORT_SHIFT               2
+#define ALE_MCAST_ENTRY_TYPE_FWD_STATE           7
+#define ALE_MCAST_ENTRY_TYPE_FWD_STATE_SHIFT     (6)
+#define ALE_MCAST_ENTRY_PORTMASK_SUP             8
+#define ALE_MCAST_ENTRY_SUPER_MASK               (0x02)
+#define ALE_MCAST_ENTRY_SUPER_SHIFT              (1)
+#define ALE_MCAST_ENTRY_PORT_MASK                (0x1C)
+#define ALE_MCAST_ENTRY_PORTMASK_SHIFT           2
+
+#define SELECT_10_HALF                          (1 << 0)
+#define SELECT_10_FULL                          (1 << 1)
+#define SELECT_100_HALF                         (1 << 2)
+#define SELECT_100_FULL                         (1 << 3)
+#define SELECT_1000_HALF                        (1 << 4)
+#define SELECT_1000_FULL                        (1 << 5)
+
+#define SELECT_SPEED_10                         (0)
+#define SELECT_SPEED_100                        (1)
+#define SELECT_SPEED_1000                       (2)
+
+#define SELECT_FORCED                           (0)
+#define SELECT_AUTONEG                          (1)
+#define SELECT_BOTH                             (2)
+
+#define SELECT_HALF_DUPLEX                      (0)
+#define SELECT_FULL_DUPLEX                      (1)
+
+
+#define SEM_DEFAULT_PSHARED (0)
+#define SEM_INITIAL_VALUE (0)
+#define RX_PRIORITY   (0)
+#define TX_PRIORITY   (0)
+
+/**
+ * RX thread stack size.
+ */
+#define RX_THREAD_STACKSIZE 2048
+
+ /**
+ * RX thread stack size.
+ */
+#define TX_THREAD_STACKSIZE 2048
+
+static void rx_thread_function(void* arg);
+static void tx_thread_function(void* arg);
+
+/* TX Buffer descriptor data structure */
+struct cpdma_tx_bd {
+  volatile struct cpdma_tx_bd *next;
+  volatile u32_t bufptr;
+  volatile u32_t bufoff_len;
+  volatile u32_t flags_pktlen;
+
+  /* helper to know which pbuf this tx bd corresponds to */
+  volatile struct pbuf *pbuf;
+}cpdma_tx_bd;
+
+/* RX Buffer descriptor data structure */
+struct cpdma_rx_bd {
+  volatile struct cpdma_rx_bd *next;
+  volatile u32_t bufptr;
+  volatile u32_t bufoff_len;
+  volatile u32_t flags_pktlen;
+
+  /* helper to know which pbuf this rx bd corresponds to */
+  volatile struct pbuf *pbuf;
+}cpdma_rx_bd;
+
+/**
+ * Helper struct to hold the data used to operate on the receive
+ * buffer descriptor ring
+ */
+struct rxch {
+  /* The head of the bd chain which can be allocated for reception*/
+  volatile struct cpdma_rx_bd *free_head;
+
+  /* The head of the bd chain which is receiving data */
+  volatile struct cpdma_rx_bd *recv_head;
+
+  /* The tail of the bd chain which is receiving data */
+  volatile struct cpdma_rx_bd *recv_tail;
+
+  /* The number of free bd's, which can be allocated for reception */
+  volatile u32_t free_num;
+}rxch;
+
+/**
+ * Helper struct to hold the data used to operate on the transmit
+ * buffer descriptor ring
+ */
+struct txch {
+  /* The bd which is free to send */
+  volatile struct cpdma_tx_bd *free_head;
+
+  /* The head of the bd chain, being sent */
+  volatile struct cpdma_tx_bd *send_head;
+
+  /* The tail of the bd chain, being sent */
+  volatile struct cpdma_tx_bd *send_tail;
+
+  /* The number of free bd's, which can be sent */
+  volatile u32_t free_num;
+}txch;
+
+volatile struct cpdma_tx_bd *free_head;
+
+/**
+ * Slave port information
+ */
+struct cpswport{
+  u32_t port_base;
+  u32_t sliver_base;
+  u32_t phy_addr;
+
+  /* The PHY is capable of GitaBit or Not */
+  u32_t phy_gbps;
+}cpswport;
+
+/**
+ * CPSW instance information
+ */
+struct cpswinst{
+  /* Base addresses */
+  u32_t ss_base;
+  u32_t mdio_base;
+  u32_t wrpr_base;
+  u32_t ale_base;
+  u32_t cpdma_base;
+  u32_t cppi_ram_base;
+  u32_t host_port_base;
+
+  /* Slave port information */
+  struct cpswport port[MAX_SLAVEPORT_PER_INST];
+
+  /* The tx/rx channels for the interface */
+  struct txch txch;
+  struct rxch rxch;
+  sys_thread_t RxThread; /**< RX receive thread data object pointer */
+  sem_t rxsem;
+  sys_thread_t TxThread; /**< RX receive thread data object pointer */
+  sem_t txsem;
+  sys_mutex_t txmtx;
+}cpswinst;
+
+/* Defining set of CPSW base addresses for all the instances */
+static struct cpswinst cpsw_inst_data[MAX_CPSW_INST];
+
+/**
+* Function to setup the instance parameters inside the interface
+* @param  cpswif  The interface structure pointer
+* @return None.
+*/
+static void
+cpswif_inst_config(struct cpswportif *cpswif) {
+  u32_t inst_num = cpswif->inst_num;
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+
+  /**
+   * Code is added for only instance 0. If more instances
+   * are there, assign base addresses and phy info here
+   */
+  if(0 == inst_num) {
+    cpswinst->ss_base = CPSW0_SS_REGS;
+    cpswinst->mdio_base = CPSW0_MDIO_REGS;
+    cpswinst->wrpr_base = CPSW0_WR_REGS;
+    cpswinst->cpdma_base = CPSW0_CPDMA_REGS;
+    cpswinst->ale_base = CPSW0_ALE_REGS;
+    cpswinst->cppi_ram_base = CPSW0_CPPI_RAM_REGS;
+    cpswinst->host_port_base = CPSW0_PORT_0_REGS;
+    cpswinst->port[PORT_1].port_base = CPSW0_PORT_1_REGS;
+    cpswinst->port[PORT_1].sliver_base = CPSW0_SLIVER_1_REGS;
+#ifdef CPSW0_PORT_1_PHY_ADDR
+    cpswinst->port[PORT_1].phy_addr = CPSW0_PORT_1_PHY_ADDR;
+    cpswinst->port[PORT_1].phy_gbps = CPSW0_PORT_1_PHY_GIGABIT;
+#endif
+    cpswinst->port[PORT_2].port_base = CPSW0_PORT_2_REGS;
+    cpswinst->port[PORT_2].sliver_base = CPSW0_SLIVER_2_REGS;
+#ifdef CPSW0_PORT_2_PHY_ADDR
+    cpswinst->port[PORT_2].phy_addr = CPSW0_PORT_2_PHY_ADDR;
+    cpswinst->port[PORT_2].phy_gbps = CPSW0_PORT_2_PHY_GIGABIT;
+#endif
+  }
+}
+
+/**
+ * Gives the index of the ALE entry which is free
+ * @param  cpswinst  The CPSW instance structure pointer
+ *
+ * @return index of the ALE entry which is free
+ *         ERR_VAL if entry not found
+ */
+static err_t
+cpswif_ale_entry_match_free(struct cpswinst *cpswinst) {
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS];
+  s32_t idx;
+
+  /* Check which ALE entry is free starting from 0th entry */
+  for (idx = 0; idx < MAX_ALE_ENTRIES; idx++) {
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+
+    /* Break if the table entry is free */
+    if (((*(((u8_t *)ale_entry) + ENTRY_TYPE_IDX))
+         & ENTRY_TYPE) == ENTRY_FREE) {
+       return idx;
+    }
+  }
+
+  return ERR_VAL;
+}
+
+#ifdef CPSW_DUAL_MAC_MODE
+/**
+ * Sets the VLAN and VLAN/UCAST entries in ALE table for Dual Mac mode
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ *
+ * @return None
+ */
+static void
+cpswif_port_to_host_vlan_cfg(struct cpswinst *cpswinst, u32_t port_num,
+                             u8_t *eth_addr)
+{
+  s32_t idx;
+  u32_t cnt;
+  u32_t ale_v_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+  u32_t ale_vu_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if(MAX_ALE_ENTRIES == idx) {
+    return;
+  }
+
+  /* Set up the VLAN Entry */
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MEMBER_LIST) =
+                                   HOST_PORT_MASK | SLAVE_PORT_MASK(port_num);
+
+  /**
+   * Set the bit fields for entry type and VLAN ID. Set the port
+   * number as VLAN ID. So only lsb 2 bits of VLAN_ID field will be used.
+   */
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_ID_BIT0_BIT7) = port_num;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11) = ALE_ENTRY_VLAN;
+
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_FRC_UNTAG_EGR) =
+                                   HOST_PORT_MASK | SLAVE_PORT_MASK(port_num);
+
+  /* Set the VLAN entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_v_entry);
+
+  idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if(MAX_ALE_ENTRIES == idx) {
+    return;
+  }
+
+  /* Set up the VLAN/Unicast Entry */
+  for(cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_vu_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  *(((u8_t *)ale_vu_entry) + ALE_VLANUCAST_ENTRY_TYPE_ID_BIT8_BIT11) =
+                                                           ALE_ENTRY_VLANUCAST;
+  *(((u8_t *)ale_vu_entry) + ALE_VLANUCAST_ENTRY_ID_BIT0_BIT7) = port_num;
+
+  /* Set the VLAN/Unicast entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_vu_entry);
+}
+
+#else /* CPSW_DUAL_MAC_MODE */
+
+/**
+ * Sets a unicast entry in the ALE table.
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ *
+ * @return None
+ */
+static void
+cpswif_ale_unicastentry_set(struct cpswinst *cpswinst, u32_t port_num,
+                            u8_t *eth_addr) {
+  volatile u32_t cnt;
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  for(cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_TYPE) = ALE_ENTRY_UCAST;
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_DLR_PORT_BLK_SEC) =
+                                   (port_num << ALE_UCAST_ENTRY_PORT_SHIFT);
+
+  idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if (idx < MAX_ALE_ENTRIES ) {
+    CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+  }
+}
+
+/**
+ * Sets a multicast entry in the ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param portmask   The port mask for the port number
+ * @param eth_addr   Ethernet Address
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static void
+cpswif_ale_multicastentry_set(struct cpswinst *cpswinst, u32_t portmask,
+                              u8_t *eth_addr)
+{
+  volatile u32_t cnt;
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_free(cpswinst);
+  if (idx < MAX_ALE_ENTRIES ) {
+    for (cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+      *(((u8_t *)ale_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+    }
+
+    *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) = ALE_ENTRY_MCAST;
+    *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) |=
+                                (portmask << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+
+    CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+  }
+}
+#endif /* CPSW_DUAL_MAC_MODE */
+
+#ifdef CPSW_SWITCH_CONFIG
+/**
+ * Checks the address is value for given type
+ *
+ * @param   eth_addr   Ethernet Address
+ * @param   addr_type  Type of address (Unicast, Multicast, Broadcast)
+ *
+ * @return  the status
+ */
+static u32_t
+check_valid_addr(u8_t *eth_addr, u32_t addr_type) {
+  u32_t cnt = 0;
+
+  if (!addr_type)
+    return TRUE;
+
+  for (cnt = 0; cnt < LEN_MAC_ADDRESS; cnt++)
+    if ((eth_addr[cnt] & MASK_BROADCAST_ADDR) != MASK_BROADCAST_ADDR)
+      break;
+
+  if ((cnt == LEN_MAC_ADDRESS) && (addr_type == ADDR_TYPE_BROADCAST))
+    return TRUE;
+  else if (cnt == LEN_MAC_ADDRESS)
+    return FALSE;
+  else if (addr_type == ADDR_TYPE_BROADCAST)
+    return FALSE;
+
+  if (addr_type == ADDR_TYPE_MULTICAST) {
+    if ((eth_addr[0] & MASK_MULTICAST_ADDR) == MASK_MULTICAST_ADDR)
+      return TRUE;
+  } else if (addr_type == ADDR_TYPE_UNICAST) {
+    if ((eth_addr[0] & MASK_MULTICAST_ADDR) != MASK_MULTICAST_ADDR)
+      return TRUE;
+  }
+
+  return FALSE;
+}
+
+/**
+ * Gives the index of the ALE entry which is untouched ageable
+ * @param  cpswinst  The CPSW instance structure pointer
+ *
+ * @return index of the ALE entry which is free
+ *         ERR_VAL if entry not found
+ */
+static err_t
+cpswif_ale_entry_match_ageable(struct cpswinst *cpswinst) {
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS];
+  u32_t type;
+  s32_t idx;
+
+  /* Check which ALE entry is free starting from 0th entry */
+  for (idx = 0; idx < MAX_ALE_ENTRIES; idx++) {
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+
+    type = *(((u8_t *)ale_entry) + ENTRY_TYPE_IDX) & ENTRY_TYPE;
+
+    /* Goto next entry if the ale entry is not valid address */
+    if ((type != ALE_ENTRY_ADDR) && (type != ALE_ENTRY_VLAN_ADDR))
+      continue;
+
+    if (check_valid_addr((u8_t *)ale_entry, ADDR_TYPE_MULTICAST))
+      continue;
+
+    type = *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_TYPE) & ALE_UCAST_TYPE_MASK;
+
+    if ((type != ALE_UCAST_TYPE_PERSISTANT) && (type != ALE_UCAST_TYPE_OUI))
+       return idx;
+    }
+
+  return ERR_VAL;
+}
+
+/**
+ * Configure the rate limit for packets transmit of ports
+ * @param  cpswinst    The CPSW instance
+ * @param  enable      Enable Rate Limit
+ * @param  direction   Select TX or RX mode
+ * @param  port_num    Port Number
+ * @param  addr_type   Type of Address (Broadcast or Multicast)
+ * @param  limit       Vale of rate limit to be set
+ *
+ * @return  None
+ *
+ **/
+static void
+cpswif_rate_limit(struct cpswinst *cpswinst, u32_t enable, u32_t direction,
+                  u32_t port_num, u32_t addr_type, u32_t limit) {
+  if (!enable) {
+    CPSWALERateLimitDisable(cpswinst->ale_base);
+  }
+
+  if (addr_type == ADDR_TYPE_BROADCAST) {
+    CPSWALEBroadcastRateLimitSet(cpswinst->ale_base, port_num, limit);
+  } else if (addr_type == ADDR_TYPE_MULTICAST) {
+    CPSWALEMulticastRateLimitSet(cpswinst->ale_base, port_num, limit);
+  }
+
+  if (port_num == 0) {
+    if (direction) {
+      CPSWALERateLimitTXMode(cpswinst->ale_base);
+    } else {
+      CPSWALERateLimitRXMode(cpswinst->ale_base);
+    }
+  } else {
+    if (direction) {
+      CPSWALERateLimitRXMode(cpswinst->ale_base);
+    } else {
+      CPSWALERateLimitTXMode(cpswinst->ale_base);
+    }
+  }
+
+  CPSWALERateLimitEnable(cpswinst->ale_base);
+}
+
+/**
+ * Gives the index of the ALE entry which match address of VLAN
+ * @param  cpswinst  The CPSW instance structure pointer
+ * @param  eth_addr  Ethernet address
+ * @param  vid       VLAN ID
+ *
+ * @return index of the ALE entry which match address of VLAN
+ *         ERR_VAL if entry not found
+ */
+static err_t
+cpswif_ale_entry_match_addr(struct cpswinst *cpswinst, u8_t *eth_addr,
+                            u32_t vid) {
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS];
+  u32_t type, cnt;
+  s32_t idx;
+
+  /* Check which ALE entry is free starting from 0th entry */
+  for (idx = 0; idx < MAX_ALE_ENTRIES; idx++) {
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+
+    type = *(((u8_t *)ale_entry) + ENTRY_TYPE_IDX) & ENTRY_TYPE;
+
+    /* Goto next entry if the ale entry is not valid address */
+    if ((type != ALE_ENTRY_ADDR) && (type != ALE_ENTRY_VLAN_ADDR))
+      continue;
+
+    if ((*(((u16_t *)ale_entry) + ALE_VLAN_ENTRY_ID) & ALE_VLAN_ID_MASK) != vid)
+      continue;
+
+    for (cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+      if (*(((u8_t *)ale_entry) + cnt) != eth_addr[ETHARP_HWADDR_LEN - cnt -1])
+        break;
+
+      if (ETHARP_HWADDR_LEN == (cnt + 1))
+        return idx;
+    }
+  }
+
+  return ERR_VAL;
+}
+
+/**
+ * Gives the index of the ALE entry which match vlan
+ * @param  cpswinst  The CPSW instance structure pointer
+ * @param  vid  VLAN ID
+ *
+ * @return index of the ALE entry which match vlan
+ *         ERR_VAL if entry not found
+ */
+static err_t
+cpswif_ale_entry_match_vlan(struct cpswinst *cpswinst, u32_t vid) {
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS];
+  u32_t type;
+  s32_t idx;
+
+  /* Check which ALE entry is free starting from 0th entry */
+  for (idx = 0; idx < MAX_ALE_ENTRIES; idx++) {
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+
+    type = *(((u8_t *)ale_entry) + ENTRY_TYPE_IDX) & ENTRY_TYPE;
+
+    /* Goto next entry if the ale entry is not valid vlan */
+    if (type != ALE_ENTRY_VLAN)
+      continue;
+
+    if ((*(((u16_t *)ale_entry) + ALE_VLAN_ENTRY_ID) & ALE_VLAN_ID_MASK) == vid)
+      return idx;
+  }
+
+  return ERR_VAL;
+}
+
+/**
+ * Adds an unicast entry in the ALE table.
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ * @param flags      Flags Settings
+ *                   0x1 - Secure
+ *                   0x2 - Block
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_unicastentry_add(struct cpswinst *cpswinst, u32_t port_num,
+                            u8_t *eth_addr, u32_t flags, u32_t ucast_type) {
+  volatile u32_t cnt;
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, 0);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  for(cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_TYPE) = ALE_ENTRY_ADDR |
+                                           (ucast_type << ALE_UCAST_TYPE_SHIFT);
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_DLR_PORT_BLK_SEC) =
+                                  (port_num << ALE_UCAST_ENTRY_PORT_SHIFT) |
+                                   (flags & ALE_UCAST_ENTRY_DLR_BLK_SEC_MASK);
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+
+  return idx;
+}
+
+/**
+ * Adds an OUI entry in the ALE table.
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param eth_addr   Ethernet address
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_OUI_add(struct cpswinst *cpswinst, u8_t *eth_addr) {
+  volatile u32_t cnt;
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, 0);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  for(cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_TYPE) = ALE_ENTRY_ADDR | ALE_ENTRY_OUI;
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+
+  return idx;
+}
+
+/**
+ * Deletes an unicast entry in the ALE table.
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ *
+ * @return index of the ALE entry deleted
+ *         ERR_VAL if table entry is not present
+ */
+static err_t
+cpswif_ale_unicastentry_del(struct cpswinst *cpswinst, u32_t port_num,
+                            u8_t *eth_addr) {
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  *(((u8_t *)ale_entry) + ALE_UCAST_ENTRY_TYPE) = ENTRY_FREE;
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, 0);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+
+  return idx;
+}
+
+/**
+ * Adds a multicast entry in the ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param portmask   The port mask for the port number
+ * @param eth_addr   Ethernet Address
+ * @param super      Supervisory Packet
+ * @param mcast_st   Multicast Forward State
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_multicastentry_add(struct cpswinst *cpswinst, u32_t portmask,
+                              u8_t *eth_addr, u32_t super, u32_t mcast_st) {
+  volatile s32_t idx;
+  volatile u32_t cnt;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, 0);
+
+  if (ERR_VAL == idx) {
+    idx = cpswif_ale_entry_match_free(cpswinst);
+  } else {
+    /* Get the entry in the ALE table */
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+  }
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  for (cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  portmask |= (*(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &
+                                        ALE_MCAST_ENTRY_PORT_MASK);
+
+  *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) =
+                          (ALE_ENTRY_ADDR |
+                           (mcast_st << ALE_MCAST_ENTRY_TYPE_FWD_STATE_SHIFT));
+  *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &=
+                           ~(PORT_MASK << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+  *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) |=
+                           (portmask << ALE_MCAST_ENTRY_PORTMASK_SHIFT) |
+                            ((super << ALE_MCAST_ENTRY_SUPER_SHIFT) &
+                             ALE_MCAST_ENTRY_SUPER_MASK);
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+
+  return idx;
+}
+
+/**
+ * Deletes a multicast entry in the ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param portmask   The port mask for the port number
+ * @param eth_addr   Ethernet Address
+ *
+ * @return index of the ALE entry deleted
+ *         ERR_VAL if table entry is not present
+ */
+static err_t
+cpswif_ale_multicastentry_del(struct cpswinst *cpswinst, u32_t portmask,
+                              u8_t *eth_addr) {
+  volatile s32_t idx;
+  u32_t ale_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, 0);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_entry);
+
+  if (portmask) {
+    *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &=
+                             ~(PORT_MASK << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+    *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) =
+                             (portmask << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+  } else {
+    *(((u8_t *)ale_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) = ENTRY_FREE;
+  }
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_entry);
+
+  return idx;
+}
+
+/**
+ * Adds the VLAN entry in ALE table
+ * @param cpswinst    The CPSW instance structure pointer
+ * @param vid         VLAN ID
+ * @param port_num    The slave port number
+ * @param untag       The force untagged egress
+ * @param reg_mcast   The registered MCAST Flood Mask
+ * @param unreg_mcast The unregistered MCAST Flood Mask
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_vlan_add(struct cpswinst *cpswinst, u32_t vid, u32_t port_num,
+                             u32_t untag, u32_t reg_mcast, u32_t unreg_mcast) {
+  s32_t idx;
+  u32_t ale_v_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_vlan(cpswinst, vid);
+
+  if (ERR_VAL == idx) {
+    idx = cpswif_ale_entry_match_free(cpswinst);
+  } else {
+    /* Get the entry in the ALE table */
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_v_entry);
+  }
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  /**
+   * Set the bit fields for entry type and VLAN ID.
+   */
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_ID_BIT0_BIT7) = vid;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11) =
+                            ((vid >> ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11_ALIGN) &
+                              MASK_LOWER_4BITS_BYTE) | ALE_ENTRY_VLAN;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_FRC_UNTAG_EGR) = untag;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MCAST_UNREG) = unreg_mcast;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MCAST_REG) = reg_mcast;
+  *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MEMBER_LIST) |=
+                                   PORT_MASK & INDV_PORT_MASK(port_num);
+
+  /* Set the VLAN entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_v_entry);
+
+  return idx;
+}
+
+/**
+ * Dlelete the VLAN entry in ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param vid        VLAN ID
+ * @param port_num   The slave port number
+ *
+ * @return index of the ALE entry deleted
+ *         ERR_VAL if table entry is not present
+ */
+static err_t
+cpswif_ale_vlan_del(struct cpswinst *cpswinst, u32_t vid, u32_t port_num) {
+  s32_t idx;
+  u32_t mask;
+  u32_t ale_v_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_vlan(cpswinst, vid);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_v_entry);
+
+  /* Set up the VLAN Entry */
+  mask = *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MEMBER_LIST) | PORT_MASK;
+  mask &= INDV_PORT_MASK(port_num);
+
+  if (0 == mask)
+    return ERR_VAL;
+
+  if (1 == mask) {
+      *(((u8_t *)ale_v_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) = ENTRY_FREE;
+  } else {
+    /* Set up the VLAN Entry */
+    *(((u8_t *)ale_v_entry) + ALE_VLAN_ENTRY_MEMBER_LIST) &=
+                              ~INDV_PORT_MASK(port_num);
+  }
+
+  /* Set the VLAN/Unicast entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_v_entry);
+
+  return idx;
+}
+
+/**
+ * Add the VLAN/UCAST entries in ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param vid        VLAN ID
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ * @param flags      Flags Settings
+ *                   0x1 - Secure
+ *                   0x2 - Block
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_vlan_add_ucast(struct cpswinst *cpswinst, u32_t vid, u32_t port_num,
+                             u8_t *eth_addr, u32_t flags, u32_t ucast_type) {
+  s32_t idx;
+  u32_t cnt;
+  u32_t ale_vu_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, vid);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_free(cpswinst);
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  /**
+   * Set the bit fields for entry type and VLAN ID.
+   */
+  *(((u8_t *)ale_vu_entry) + ALE_VLAN_ENTRY_ID_BIT0_BIT7) = vid;
+  *(((u8_t *)ale_vu_entry) + ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11) =
+                            ((vid >> ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11_ALIGN) &
+                              MASK_LOWER_4BITS_BYTE) | ALE_ENTRY_VLAN_ADDR |
+                              (ucast_type << ALE_UCAST_TYPE_SHIFT);
+
+  for (cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_vu_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  *(((u8_t *)ale_vu_entry) + ALE_UCAST_ENTRY_DLR_PORT_BLK_SEC) =
+                                  (port_num << ALE_UCAST_ENTRY_PORT_SHIFT) |
+                                   (flags & ALE_UCAST_ENTRY_DLR_BLK_SEC_MASK);
+
+  /* Set the VLAN entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_vu_entry);
+
+  return idx;
+}
+
+/**
+ * Dlelete the VLAN/UCAST entry in ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param vid        VLAN ID
+ * @param port_num   The slave port number
+ *
+ * @return index of the ALE entry deleted
+ *         ERR_VAL if table entry is not present
+ */
+static err_t
+cpswif_ale_vlan_del_ucast(struct cpswinst *cpswinst, u32_t vid, u32_t port_num,
+                             u8_t *eth_addr) {
+  volatile s32_t idx;
+  u32_t ale_vu_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  *(((u8_t *)ale_vu_entry) + ALE_UCAST_ENTRY_TYPE) = ENTRY_FREE;
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, vid);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_vu_entry);
+
+  return idx;
+}
+
+/**
+ * Add the VLAN/MCAST entries in ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param vid        VLAN ID
+ * @param port_num   The slave port number
+ * @param eth_addr   Ethernet address
+ * @param super      Supervisory Packet
+ * @param mcast_st   Multicast Forward State
+ *
+ * @return index of the ALE entry added
+ *         ERR_VAL if table entry is not free
+ */
+static err_t
+cpswif_ale_vlan_add_mcast(struct cpswinst *cpswinst, u32_t vid, u32_t portmask,
+                             u8_t *eth_addr, u32_t super, u32_t mcast_st) {
+  s32_t idx;
+  u32_t cnt;
+  u32_t ale_vm_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, vid);
+
+  if (ERR_VAL == idx) {
+    idx = cpswif_ale_entry_match_free(cpswinst);
+  } else {
+    /* Get the entry in the ALE table */
+    CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_vm_entry);
+  }
+
+  if (ERR_VAL == idx)
+    idx = cpswif_ale_entry_match_ageable(cpswinst);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  /**
+   * Set the bit fields for entry type and VLAN ID.
+   */
+  *(((u8_t *)ale_vm_entry) + ALE_VLAN_ENTRY_ID_BIT0_BIT7) = vid;
+  *(((u8_t *)ale_vm_entry) + ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11) =
+                            ((vid >> ALE_VLAN_ENTRY_TYPE_ID_BIT8_BIT11_ALIGN) &
+                              MASK_LOWER_4BITS_BYTE);
+
+  for (cnt = 0; cnt < ETHARP_HWADDR_LEN; cnt++) {
+    *(((u8_t *)ale_vm_entry) + cnt) = eth_addr[ETHARP_HWADDR_LEN - cnt -1];
+  }
+
+  portmask |= (*(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &
+                                           ALE_MCAST_ENTRY_PORT_MASK);
+
+  *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) |=
+                          (ALE_ENTRY_VLAN_ADDR |
+                           (mcast_st << ALE_MCAST_ENTRY_TYPE_FWD_STATE_SHIFT));
+  *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &=
+                              ~(PORT_MASK << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+  *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) |=
+                             (portmask << ALE_MCAST_ENTRY_PORTMASK_SHIFT) |
+                              ((super << ALE_MCAST_ENTRY_SUPER_SHIFT) &
+                               ALE_MCAST_ENTRY_SUPER_MASK);
+
+  /* Set the VLAN entry in the ALE table */
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_vm_entry);
+
+  return idx;
+}
+
+/**
+ * Deletes a vlan multicast entry in the ALE table
+ * @param cpswinst   The CPSW instance structure pointer
+ * @param vid        VLAN ID
+ * @param portmask   The port mask for the port number
+ * @param eth_addr   Ethernet Address
+ *
+ * @return index of the ALE entry deleted
+ *         ERR_VAL if table entry is not present
+ */
+static err_t
+cpswif_ale_vlan_del_mcast(struct cpswinst *cpswinst, u32_t vid, u32_t portmask,
+                              u8_t *eth_addr) {
+  volatile s32_t idx;
+  u32_t ale_vm_entry[ALE_ENTRY_NUM_WORDS] = {0, 0, 0};
+
+  idx = cpswif_ale_entry_match_addr(cpswinst, eth_addr, vid);
+
+  if (ERR_VAL == idx)
+    return ERR_VAL;
+
+  CPSWALETableEntryGet(cpswinst->ale_base, idx, ale_vm_entry);
+
+  if (portmask) {
+    *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) &=
+                                ~(PORT_MASK << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+    *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_PORTMASK_SUP) =
+                                (portmask << ALE_MCAST_ENTRY_PORTMASK_SHIFT);
+  } else {
+    *(((u8_t *)ale_vm_entry) + ALE_MCAST_ENTRY_TYPE_FWD_STATE) = ENTRY_FREE;
+  }
+
+  CPSWALETableEntrySet(cpswinst->ale_base, idx, ale_vm_entry);
+
+  return idx;
+}
+
+#endif  /* CPSW_SWITCH_CONFIG */
+
+/**
+ * AutoNegotiates with phy for link, set it in silver and check for link status.
+ * @param  cpswinst   The CPSW instance structure pointer
+ * @param  port_num    The slave port number
+ * @param  adv         Configuration for advertisement
+ *                     SELECT_10_HALF - 10Base Half Duplex
+ *                     SELECT_10_FULL - 10Base Full Duplex
+ *                     SELECT_100_HALF - 100Base Half Duplex
+ *                     SELECT_100_FULL - 100Base Full Duplex
+ *                     SELECT_1000_HALF - 1000Base Half Duplex
+ *                     SELECT_1000_FULL - 1000Base Full Duplex
+ * @return ERR_OK      If link set up is successful
+ *                     others if not successful
+ */
+static err_t
+cpswif_phy_autoneg(struct cpswinst *cpswinst, u32_t port_num, u32_t adv) {
+  err_t linkstat = ERR_CONN;
+  u16_t adv_val = 0, partnr_ablty = 0, gbps_partnr_ablty = 0, gig_adv_val = 0;
+  u32_t aut_neg_cnt = 200, auto_stat, transfer_mode = 0;
+
+  /* Check if ethernet PHY is present or not */
+  if (0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+            & (1 << cpswinst->port[port_num - 1].phy_addr))) {
+    LWIP_PRINTF("\n\rNo PHY found at addr %d for Port %d of Instance %d.",
+                cpswinst->port[port_num - 1].phy_addr,
+                port_num, 0);
+    return linkstat;
+  }
+
+  LWIP_PRINTF("\n\rPHY found at address %d for  Port %d of Instance %d.",
+              cpswinst->port[port_num - 1].phy_addr,
+              port_num, 0);
+
+  if (SELECT_1000_HALF == adv) {
+    LWIP_PRINTF("\n\rCPSW doesnot support Half Duplex for Gigabyte...");
+    return linkstat;
+  }
+
+  /* We advertise for 10/100 Mbps both half and full duplex */
+  if (adv & SELECT_10_HALF)
+    adv_val |= PHY_10BT;
+  if (adv & SELECT_10_FULL)
+    adv_val |= PHY_10BT_FD;
+  if (adv & SELECT_100_HALF)
+    adv_val |= PHY_100BTX;
+  if (adv & SELECT_100_FULL)
+    adv_val |= PHY_100BTX_FD;
+
+  gig_adv_val = 0;
+  partnr_ablty = TRUE;
+  gbps_partnr_ablty = FALSE;
+
+  /**
+   * Not all the PHYs can operate at 1000 Mbps. So advertise only
+   * if the PHY is capable
+   */
+  if (cpswinst->port[port_num -1].phy_gbps) {
+    LWIP_PRINTF("\n\rPhy supports Gigabyte...");
+    if (adv & SELECT_1000_FULL) {
+      gig_adv_val = PHY_1000BT_FD;
+      partnr_ablty = TRUE;
+      gbps_partnr_ablty = TRUE;
+    }
+    if (adv & SELECT_1000_HALF) {
+      LWIP_PRINTF("\n\rCPSW doesnot support Half Duplex for Gigabyte...");
+    }
+  } else {
+    LWIP_PRINTF("\n\rPhy doesnot support Gigabyte...");
+  }
+
+  LWIP_PRINTF("\n\rPerforming Auto-Negotiation...");
+
+  /**
+   * Now start Autonegotiation. PHY will talk to its partner
+   * and give us what the partner can handle
+   */
+  if (PhyAutoNegotiate(cpswinst->mdio_base,
+                       cpswinst->port[port_num -1].phy_addr,
+                       &adv_val, &gig_adv_val) == TRUE) {
+    while (aut_neg_cnt) {
+      delay(50);
+      auto_stat = PhyAutoNegStatusGet(cpswinst->mdio_base,
+                                      cpswinst->port[port_num -1].phy_addr);
+      if (TRUE == auto_stat) {
+        break;
+      }
+      aut_neg_cnt--;
+    }
+
+    if (0 != aut_neg_cnt) {
+      linkstat = ERR_OK;
+      LWIP_PRINTF("\n\rAuto-Negotiation Successful.");
+    } else {
+      LWIP_PRINTF("\n\rAuto-Negotiation Not Successful.");
+      return ERR_CONN;
+    }
+
+    /* Get what the partner supports */
+    PhyPartnerAbilityGet(cpswinst->mdio_base,
+                         cpswinst->port[port_num -1].phy_addr,
+                         &partnr_ablty, &gbps_partnr_ablty);
+    if (gbps_partnr_ablty & PHY_LINK_PARTNER_1000BT_FD) {
+      LWIP_PRINTF("\n\rTransfer Mode : 1000 Mbps.");
+      transfer_mode = CPSW_SLIVER_GIG_FULL_DUPLEX;
+    } else {
+      if ((adv_val & partnr_ablty) & PHY_100BTX_FD) {
+        LWIP_PRINTF("\n\rTransfer Mode : 100 Mbps Full Duplex.");
+        transfer_mode = CPSW_SLIVER_NON_GIG_FULL_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_100BTX) {
+        LWIP_PRINTF("\n\rTransfer Mode : 100 Mbps Half Duplex.");
+        transfer_mode = CPSW_SLIVER_NON_GIG_HALF_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_10BT_FD) {
+        LWIP_PRINTF("\n\rTransfer Mode : 10 Mbps Full Duplex.");
+        transfer_mode = CPSW_SLIVER_INBAND | CPSW_SLIVER_NON_GIG_FULL_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_10BT) {
+        LWIP_PRINTF("\n\rTransfer Mode : 10 Mbps Half Duplex.");
+        transfer_mode = CPSW_SLIVER_INBAND | CPSW_SLIVER_NON_GIG_HALF_DUPLEX;
+      } else {
+        LWIP_PRINTF("\n\rNo Valid Transfer Mode is detected.");
+      }
+    }
+  } else {
+    LWIP_PRINTF("\n\rAuto-Negotiation Not Successful.");
+    linkstat = ERR_CONN;
+  }
+
+  /**
+   * Set the Sliver with the negotiation results if autonegotiation
+   * is successful
+   */
+  if (linkstat == ERR_OK) {
+    CPSWSlTransferModeSet(cpswinst->port[port_num - 1].sliver_base,
+                          transfer_mode);
+  }
+
+  /* Check if PHY link is there or not */
+  if (FALSE == ((PhyLinkStatusGet(cpswinst->mdio_base,
+                cpswinst->port[port_num - 1].phy_addr, 1000)))) {
+    LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Inst %d.",
+                port_num, 0);
+    return linkstat;
+  }
+
+  LWIP_PRINTF("\n\rPHY link verified for Port %d of Instance %d.",
+              port_num, 0);
+
+  CPSWSlRGMIIEnable(
+                  cpswinst->port[port_num - 1].sliver_base);
+
+  return linkstat;
+}
+
+/**
+ * Manually configure phy, set it in silver and check for link status.
+ * @param  cpswinst   The CPSW instance structure pointer
+ * @param  port_num    The slave port number
+ * @param  speed       Configuration for speed
+ *                     SELECT_SPEED_1000 - 1000 Mbps
+ *                     SELECT_SPEED_100 - 100 Mbps
+ *                     SELECT_SPEED_10 - 10 Mbps
+ * @param  duplex      Configuration for duplex
+ *                     SELECT_HALF_DUPLEX - Half Duplex
+ *                     SELECT_FULL_DUPLEX - Full Duplex
+ * @return ERR_OK      If link set up is successful
+ *                     others if not successful
+ */
+static err_t
+cpswif_phy_forced(struct cpswinst *cpswinst, u32_t port_num, u32_t speed,
+                  u32_t duplex) {
+  err_t linkstat = ERR_CONN;
+  u16_t speed_val = 0, duplex_val = 0;
+  u32_t frc_stat_cnt = 200, frc_stat = FALSE, transfer_mode = 0;
+
+  /* Check if ethernet PHY is present or not */
+  if (0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+            & (1 << cpswinst->port[port_num - 1].phy_addr))){
+    LWIP_PRINTF("\n\rNo PHY found at addr %d for Port %d of Instance %d.",
+                cpswinst->port[port_num - 1].phy_addr,
+                port_num, 0);
+    return linkstat;
+  }
+
+  LWIP_PRINTF("\n\rPHY found at address %d for  Port %d of Instance %d.",
+              cpswinst->port[port_num - 1].phy_addr,
+              port_num, 0);
+
+  /* configure control for speed and duples */
+  if (SELECT_SPEED_1000 == speed)
+    speed_val = PHY_SPEED_1000MBPS;
+  else if (SELECT_SPEED_100 == speed)
+    speed_val = PHY_SPEED_100MBPS;
+
+  if (TRUE == duplex)
+    duplex_val = PHY_FULL_DUPLEX;
+
+  if (SELECT_SPEED_1000 == speed) {
+    LWIP_PRINTF("\n\rManual Configuration not allowed for Gigabyte...");
+    return linkstat;
+  }
+
+  if (FALSE == PhyReset(cpswinst->mdio_base,
+                        cpswinst->port[port_num - 1].phy_addr)) {
+    LWIP_PRINTF("\n\rPHY Reset Failed...");
+    return linkstat;
+  }
+
+  if (TRUE == (PhyLinkStatusGet(cpswinst->mdio_base,
+               cpswinst->port[port_num - 1].phy_addr, 1000))) {
+   while (frc_stat_cnt) {
+      delay(50);
+      /* Check if PHY link is there or not */
+      frc_stat = (PhyLinkStatusGet(cpswinst->mdio_base,
+                  cpswinst->port[port_num - 1].phy_addr, 1000));
+
+      if (TRUE == frc_stat) {
+        LWIP_PRINTF("\n\rPHY Link is Down.");
+        break;
+      }
+      frc_stat_cnt--;
+    }
+  }
+
+  LWIP_PRINTF("\n\rPerforming Manual Configuration...");
+
+  frc_stat_cnt = 200;
+  frc_stat = FALSE;
+
+  if (PhyConfigure(cpswinst->mdio_base, cpswinst->port[port_num -1].phy_addr,
+                   speed_val, duplex_val)) {
+    while (frc_stat_cnt) {
+      delay(50);
+      frc_stat = PhyLinkStatusGet(cpswinst->mdio_base,
+                           cpswinst->port[port_num - 1].phy_addr, 1000);
+
+      if (1 == frc_stat) {
+        break;
+      }
+      frc_stat_cnt--;
+    }
+
+    if (0 != frc_stat_cnt) {
+      linkstat = ERR_OK;
+      LWIP_PRINTF("\n\rPhy Configuration Successful.");
+      LWIP_PRINTF("\n\rPHY link verified for Port %d of Instance %d.",
+                  port_num, 0);
+    } else {
+      LWIP_PRINTF("\n\rPhy Configuration Successful.");
+      LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Inst %d.",
+                  port_num, 0);
+      return ERR_CONN;
+    }
+
+    if (SELECT_SPEED_1000 == speed) {
+      LWIP_PRINTF("\n\rTransfer Mode : 1000 Mbps.");
+      transfer_mode = CPSW_SLIVER_GIG_FULL_DUPLEX;
+    } else {
+      if (SELECT_SPEED_10 == speed) {
+        LWIP_PRINTF("\n\rTransfer Mode : 10 Mbps ");
+        transfer_mode = CPSW_SLIVER_INBAND;
+      } else {
+        LWIP_PRINTF("\n\rTransfer Mode : 100 Mbps ");
+      }
+      if (TRUE == duplex) {
+        LWIP_PRINTF("Full Duplex.");
+        transfer_mode |= CPSW_SLIVER_NON_GIG_FULL_DUPLEX;
+      } else {
+        LWIP_PRINTF("Half Duplex.");
+        transfer_mode |= CPSW_SLIVER_NON_GIG_HALF_DUPLEX;
+      }
+    }
+  } else {
+    LWIP_PRINTF("\n\rPhy Configuration Not Successful.");
+    LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Inst %d.",
+                port_num, 0);
+    linkstat = ERR_CONN;
+  }
+
+  /**
+   * Set the Sliver with the forced phy configuration
+   */
+  CPSWSlTransferModeSet(cpswinst->port[port_num - 1].sliver_base,
+                        transfer_mode);
+
+  CPSWSlRGMIIEnable(cpswinst->port[port_num - 1].sliver_base);
+
+  return linkstat;
+}
+
+/**
+* Function to setup the link. AutoNegotiates with the phy for link
+* setup and set the CPSW with the result of autonegotiation.
+* @param  cpswportif  The cpsw port interface structure pointer
+* @return ERR_OK      If link set up is successful
+*                     others if not successful
+*/
+static err_t
+cpswif_autoneg_config(u32_t inst_num, u32_t port_num) {
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+  err_t linkstat = ERR_CONN;
+  u16_t adv_val, partnr_ablty, gbps_partnr_ablty, gig_adv_val;
+  u32_t aut_neg_cnt = 200, auto_stat, transfer_mode = 0;
+
+  /* We advertise for 10/100 Mbps both half and full duplex */
+  adv_val = (PHY_100BTX | PHY_100BTX_FD | PHY_10BT | PHY_10BT_FD);
+
+  /**
+   * Not all the PHYs can operate at 1000 Mbps. So advertise only
+   * if the PHY is capable
+   */
+  if(TRUE == cpswinst->port[port_num -1].phy_gbps) {
+    gig_adv_val = PHY_1000BT_FD;
+    partnr_ablty = TRUE;
+    gbps_partnr_ablty = TRUE;
+  } else {
+    gig_adv_val = 0;
+    partnr_ablty = TRUE;
+    gbps_partnr_ablty = FALSE;
+  }
+
+  LWIP_PRINTF("\n\rPerforming Auto-Negotiation...");
+
+  /**
+   * Now start Autonegotiation. PHY will talk to its partner
+   * and give us what the partner can handle
+   */
+  if(PhyAutoNegotiate(cpswinst->mdio_base,
+                      cpswinst->port[port_num -1].phy_addr,
+                      &adv_val, &gig_adv_val) == TRUE) {
+    while(aut_neg_cnt) {
+      delay(50);
+      auto_stat = PhyAutoNegStatusGet(cpswinst->mdio_base,
+                                      cpswinst->port[port_num -1].phy_addr);
+      if(TRUE == auto_stat) {
+        break;
+      }
+      aut_neg_cnt--;
+    }
+
+    if(0 != aut_neg_cnt) {
+      linkstat = ERR_OK;
+      LWIP_PRINTF("\n\rAuto-Negotiation Successful.");
+    } else {
+      LWIP_PRINTF("\n\rAuto-Negotiation Not Successful.");
+      return ERR_CONN;
+    }
+
+    /* Get what the partner supports */
+    PhyPartnerAbilityGet(cpswinst->mdio_base,
+                         cpswinst->port[port_num -1].phy_addr,
+                         &partnr_ablty, &gbps_partnr_ablty);
+    if(gbps_partnr_ablty & PHY_LINK_PARTNER_1000BT_FD) {
+      LWIP_PRINTF("\n\rTransfer Mode : 1000 Mbps.");
+      transfer_mode = CPSW_SLIVER_GIG_FULL_DUPLEX;
+    } else {
+      if ((adv_val & partnr_ablty) & PHY_100BTX_FD) {
+        LWIP_PRINTF("\n\rTransfer Mode : 100 Mbps Full Duplex.");
+        transfer_mode = CPSW_SLIVER_NON_GIG_FULL_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_100BTX) {
+        LWIP_PRINTF("\n\rTransfer Mode : 100 Mbps Half Duplex.");
+        transfer_mode = CPSW_SLIVER_NON_GIG_HALF_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_10BT_FD) {
+        LWIP_PRINTF("\n\rTransfer Mode : 10 Mbps Full Duplex.");
+        transfer_mode = CPSW_SLIVER_INBAND | CPSW_SLIVER_NON_GIG_FULL_DUPLEX;
+      } else if ((adv_val & partnr_ablty) & PHY_10BT) {
+        LWIP_PRINTF("\n\rTransfer Mode : 10 Mbps Half Duplex.");
+        transfer_mode = CPSW_SLIVER_INBAND | CPSW_SLIVER_NON_GIG_HALF_DUPLEX;
+      } else {
+        LWIP_PRINTF("\n\rNo Valid Transfer Mode is detected.");
+      }
+    }
+  } else {
+    LWIP_PRINTF("\n\rAuto-Negotiation Not Successful.");
+    linkstat = ERR_CONN;
+  }
+
+  /**
+   * Set the Sliver with the negotiation results if autonegotiation
+   * is successful
+   */
+  if(linkstat == ERR_OK) {
+    CPSWSlTransferModeSet(cpswinst->port[port_num - 1].sliver_base,
+                          transfer_mode);
+  }
+
+  return linkstat;
+}
+
+/**
+ * This function allocates the rx buffer descriptors ring. The function
+ * internally calls pbuf_alloc() and allocates the pbufs to the rx buffer
+ * descriptors.
+ *
+ * @param   cpswinst   The CPSW instance structure pointer
+ * @return  None
+ */
+static void
+cpswif_rxbd_alloc(struct cpswinst *cpswinst) {
+  struct rxch *rxch = &(cpswinst->rxch);
+  struct pbuf *p;
+  volatile struct cpdma_rx_bd *curr_bd, *last_bd, *recv_tail, *recv_head;
+  u32_t saved_free_num;
+
+  /* Start from the free head of the chain */
+  curr_bd = rxch->free_head;
+
+  /* Note down the current positions */
+  recv_head = rxch->free_head;
+  recv_tail = rxch->recv_tail;
+  saved_free_num = rxch->free_num;
+  last_bd = rxch->recv_tail;
+
+  while(rxch->free_num) {
+    /**
+     * Try to get a pbuf of max. length. This shall be cache line aligned if
+     * cache is enabled.
+     */
+    p = pbuf_alloc(PBUF_RAW, PBUF_LEN_MAX, PBUF_POOL);
+
+    /**
+     * Allocate bd's if p is not NULL. This allocation doesnt support
+     * pbuf chaining.
+     */
+    if(p != NULL) {
+#ifdef LWIP_CACHE_ENABLED
+      /**
+       * Clean the pbuf structure info. This is needed to prevent losing
+       * pbuf structure info when we invalidate the pbuf on rx interrupt
+       */
+      CacheDataCleanBuff((u32_t)(p), (u32_t)(SIZEOF_STRUCT_PBUF));
+#endif
+      curr_bd->bufptr = (u32_t)(p->payload);
+      curr_bd->bufoff_len = p->len;
+      curr_bd->flags_pktlen = CPDMA_BUF_DESC_OWNER;
+
+      /* Save the pbuf */
+      curr_bd->pbuf = p;
+      last_bd = curr_bd;
+      curr_bd = curr_bd->next;
+      rxch->free_num--;
+    } else {
+      break;
+    }
+  }
+
+  if(saved_free_num == rxch->free_num) {
+    /* No bd's were allocated. Go back. */
+    return;
+  }
+
+  rxch->recv_tail = last_bd;
+
+  /**
+   * If the entire ring is traversed, curr_bd will be NULL. In that case,
+   * write the Rx HDP in order to continue reception
+   */
+  if(NULL != curr_bd) {
+    rxch->free_head = curr_bd;
+  } else {
+    CPSWCPDMARxHdrDescPtrWrite(cpswinst->cpdma_base, (u32_t)(recv_head), 0);
+  }
+
+  recv_tail->next = recv_head;
+
+  /* Close the ring to prevent overwriting of pbuf data */
+  last_bd->next = NULL;
+
+  /**
+   * Check if the reception has ended. If the EOQ flag is set, the NULL
+   * Pointer is  already taken by the DMA engine. So we need to write the
+   * RX HDP with the next descriptor.
+   */
+  if(recv_tail->flags_pktlen & CPDMA_BUF_DESC_EOQ) {
+    CPSWCPDMARxHdrDescPtrWrite(cpswinst->cpdma_base, (u32_t)(recv_head), 0);
+  }
+}
+
+/**
+ * This function does the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf might be
+ * chained. That is, one pbuf can span more than one tx buffer descriptors
+ *
+ * @param netif    the network interface state for this ethernetif
+ * @param pbuf     the pbuf which is to be sent over EMAC
+ * @return status  ERR_OK, if transmit was successful
+ *                 ERR_MEM, if no memory available
+ */
+static err_t
+cpswif_transmit(struct netif *netif, struct pbuf *pbuf) {
+  struct pbuf *q;
+  struct txch *txch;
+  volatile struct cpdma_tx_bd *curr_bd, *bd_to_send, *bd_end;
+  struct cpswportif *cpswif = netif->state;
+  u32_t inst_num = cpswif->inst_num;
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+
+#ifdef CPSW_DUAL_MAC_MODE
+  u32_t port_num = cpswif->port_num;
+#endif
+
+  txch = &(cpswinst->txch);
+
+  /* Do not send if there are no enough free bd's */
+  if(pbuf_clen(pbuf) > txch->free_num) {
+    return ERR_MEM;
+  }
+
+  /* Get the buffer descriptor which is free to transmit */
+  curr_bd = txch->free_head;
+
+  bd_to_send = txch->free_head;
+
+  /* Update the total packet length */
+  curr_bd->flags_pktlen = pbuf->tot_len;
+
+  /* Indicate the start of the packet */
+  curr_bd->flags_pktlen |= (CPDMA_BUF_DESC_SOP | CPDMA_BUF_DESC_OWNER);
+
+#ifdef CPSW_DUAL_MAC_MODE
+  /* Indicate to which port the packet has to be sent */
+  curr_bd->flags_pktlen |= CPDMA_BUF_DESC_TO_PORT(port_num);
+#endif
+
+  /* Copy pbuf information into TX buffer descriptors */
+  for(q = pbuf; q != NULL; q = q->next) {
+#ifdef LWIP_CACHE_ENABLED
+    /**
+     * Make sure that the payload is written to memory. Clean
+     * the portion of cache to make it coherent with the memory.
+     */
+    CacheDataCleanBuff((u32_t)(q->payload), (u32_t)(q->len));
+#endif
+    /* Intialize the buffer pointer and length */
+    curr_bd->bufptr = (u32_t)(q->payload);
+    curr_bd->bufoff_len = (q->len) & CPDMA_BD_LEN_MASK;
+    bd_end = curr_bd;
+    curr_bd->pbuf = pbuf;
+    curr_bd = curr_bd->next;
+
+    /* Decrement free bds, since one is consumed */
+    txch->free_num--;
+  }
+  /* Indicate the end of the packet */
+  bd_end->next = NULL;
+  bd_end->flags_pktlen |= CPDMA_BUF_DESC_EOP;
+  bd_end->flags_pktlen &= ~CPDMA_BUF_DESC_EOQ;
+
+  txch->free_head = curr_bd;
+
+  /* For the first time, write the HDP with the filled bd */
+  if(txch->send_tail == NULL) {
+    CPSWCPDMATxHdrDescPtrWrite(cpswinst->cpdma_base,
+                               (u32_t)(bd_to_send), 0);
+  } else {
+    /**
+     * Chain the bd's. If the DMA engine, already reached the end of the chain,
+     * the EOQ will be set. In that case, the HDP shall be written again.
+     */
+    curr_bd = txch->send_tail;
+    curr_bd->next = bd_to_send;
+
+    if(curr_bd->flags_pktlen & CPDMA_BUF_DESC_EOQ) {
+      /* Write the Header Descriptor Pointer and start DMA */
+      CPSWCPDMATxHdrDescPtrWrite(cpswinst->cpdma_base,
+                                 (u32_t)(bd_to_send), 0);
+    }
+  }
+
+  txch->send_tail = bd_end;
+
+  return ERR_OK;
+}
+
+/**
+ * This function will send a packet through the emac if the channel is
+ * available. Otherwise, the packet will be queued in a pbuf queue.
+ *
+ * @param netif   The lwip network interface structure for this ethernetif
+ * @param p       The MAC packet to send (e.g. IP packet including
+ *                MAC addresses and type)
+ * @return        ERR_OK if the packet could be sent
+ *                an err_t value if the packet couldn't be sent
+ *
+ */
+static err_t
+cpswif_output(struct netif *netif, struct pbuf *p) {
+  err_t stat;
+  struct pbuf *q;
+  struct cpswportif *cpswif = netif->state;
+  u32_t inst_num = cpswif->inst_num;
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  /**
+   * This entire function must run within a "critical section" to preserve
+   * the integrity of the transmit pbuf queue.
+   */
+
+  sys_mutex_lock(&cpswinst->txmtx);
+  SYS_ARCH_PROTECT(lev);
+
+  /**
+   * Adjust the packet length if less than minimum required.
+   */
+  if(p->tot_len < MIN_PKT_LEN) {
+      p->tot_len = MIN_PKT_LEN;
+
+      for(q = p; q->next != NULL; q = q->next) {
+        q->next->tot_len = q->tot_len - q->len;
+      }
+
+    /* Adjust the length of the last pbuf. (contents - don't care) */
+    q->len = q->tot_len;
+  }
+
+  /**
+   * Bump the reference count on the pbuf to prevent it from being
+   * freed till we are done with it.
+   */
+  pbuf_ref(p);
+
+  /* call the actual transmit function */
+  stat = cpswif_transmit(netif, p);
+
+  /* Return to prior interrupt state and return. */
+  SYS_ARCH_UNPROTECT(lev);
+  sys_mutex_unlock(&cpswinst->txmtx);
+
+  return stat;
+}
+
+/**
+ * Configures PHY link for a port
+ * @param cpswif  The CPSW interface structure pointer
+ * @param slv_port_num  The slave port number
+ *
+ * @return ERR_OK    if link configurations are successful
+ *                   an error status if failed
+ */
+static err_t
+cpswif_phylink_config(struct cpswportif * cpswif, u32_t slv_port_num) {
+  struct cpswinst *cpswinst = &cpsw_inst_data[cpswif->inst_num];
+  err_t err;
+
+  /* Check if ethernet PHY is present or not */
+  if(0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+        & (1 << cpswinst->port[slv_port_num - 1].phy_addr))){
+    LWIP_PRINTF("\n\rNo PHY found at address %d for  Port %d of Instance %d.",
+                cpswinst->port[slv_port_num - 1].phy_addr, slv_port_num,
+                cpswif->inst_num);
+    return ERR_CONN;
+  }
+
+  LWIP_PRINTF("\n\rPHY found at address %d for  Port %d of Instance %d.",
+              cpswinst->port[slv_port_num - 1].phy_addr, slv_port_num,
+              cpswif->inst_num);
+
+  /**
+   * PHY is alive. So autonegotiate and get the speed and duplex
+   * parameters, set it in the sliver
+   */
+  err = (err_t)(cpswif_autoneg_config(cpswif->inst_num, slv_port_num));
+
+  /* Check if PHY link is there or not */
+  if(FALSE == ((PhyLinkStatusGet(cpswinst->mdio_base,
+                           cpswinst->port[slv_port_num - 1].phy_addr, 1000)))) {
+    LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Instance %d.",
+                slv_port_num, cpswif->inst_num);
+    return ERR_CONN;
+  }
+
+  LWIP_PRINTF("\n\rPHY link verified for Port %d of Instance %d.",
+              slv_port_num, cpswif->inst_num);
+
+  CPSWSlRGMIIEnable(cpswinst->port[slv_port_num - 1].sliver_base);
+
+  return err;
+}
+
+/**
+ * Initializes the CPSW port
+ * @param netif   The cpsw interface
+ *
+ * @return ERR_OK    if port initialization is successful
+ *                   an error status if failed
+ */
+static err_t
+cpswif_port_init(struct netif *netif) {
+  struct cpswportif *cpswif = (struct cpswportif*)(netif->state);
+  u32_t temp;
+  err_t err;
+
+#ifdef CPSW_DUAL_MAC_MODE
+  struct cpswinst *cpswinst = &cpsw_inst_data[cpswif->inst_num];
+  u32_t curr_port = cpswif->port_num;
+#endif
+  sem_init(&cpswinst->rxsem, SEM_DEFAULT_PSHARED, SEM_INITIAL_VALUE);
+  
+  cpswinst->RxThread = sys_thread_new("receive_thread", rx_thread_function, netif, RX_THREAD_STACKSIZE, RX_PRIORITY);
+  LWIP_ASSERT("RxThread creation error", (cpswinst->RxThread));
+
+  sem_init(&cpswinst->txsem, SEM_DEFAULT_PSHARED, SEM_INITIAL_VALUE);
+
+  cpswinst->TxThread = sys_thread_new("transmit_thread", tx_thread_function, netif, TX_THREAD_STACKSIZE, TX_PRIORITY);
+  LWIP_ASSERT("TxThread creation error", (cpswinst->TxThread));
+
+  err = sys_mutex_new(&cpswinst->txmtx);
+  LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
+
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  for(temp = 0; temp < ETHARP_HWADDR_LEN; temp++) {
+    netif->hwaddr[temp] = cpswif->eth_addr[temp];
+  }
+
+  /* maximum transfer unit */
+  netif->mtu = MAX_TRANSFER_UNIT;
+
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+#ifdef CPSW_DUAL_MAC_MODE
+  /* Set the ethernet address for the port */
+  CPSWPortSrcAddrSet(cpswinst->port[curr_port - 1].port_base,
+                    (u8_t *)(&(cpswif->eth_addr)));
+
+  /**
+   * For Dual Mac mode, configure port0 and port1 for one VLAN ID;
+   * port0 and port2 for a different VLAN ID. Here we choose the
+   * port number as VLAN ID.
+   */
+  CPSWPortVLANConfig(cpswinst->port[curr_port - 1].port_base, curr_port, 0, 0);
+
+  cpswif_port_to_host_vlan_cfg(cpswinst, curr_port,
+                               (u8_t *)(&(cpswif->eth_addr)));
+
+  err = cpswif_phylink_config(cpswif, curr_port);
+
+#else
+  err = cpswif_phylink_config(cpswif, 1);
+  err = err & (cpswif_phylink_config(cpswif, 2));
+
+#endif
+
+  return err;
+}
+
+/**
+ * This function intializes the CPDMA.
+ * The CPPI RAM will be initialized for transmit and receive
+ * buffer descriptor rings.
+ *
+ * @param cpswinst   The CPSW instance structure pointer
+ * @return None
+ */
+static void
+cpswif_cpdma_init(struct cpswinst *cpswinst) {
+  u32_t num_bd;
+  volatile struct cpdma_tx_bd *curr_txbd, *last_txbd;
+  volatile struct cpdma_rx_bd *curr_rxbd, *last_rxbd;
+  struct txch *txch;
+  struct rxch *rxch;
+
+  txch = &(cpswinst->txch);
+
+  /* Initialize the CPDMA memory. Only Channel 0 is supported */
+  txch->free_head = (volatile struct cpdma_tx_bd*)(cpswinst->cppi_ram_base);
+  txch->send_head = txch->free_head;
+  txch->send_tail = NULL;
+
+  /* Allocate half of the CPPI RAM for TX buffer descriptors */
+  num_bd = (SIZE_CPPI_RAM >> 1) / sizeof(cpdma_tx_bd);
+
+  /* All buffer descriptors are free to send */
+  txch->free_num = num_bd;
+
+  curr_txbd = txch->free_head;
+
+  /* Initialize all the TX buffer descriptors ring */
+  while(num_bd) {
+    curr_txbd->next = curr_txbd + 1;
+    curr_txbd->flags_pktlen = 0;
+    last_txbd = curr_txbd;
+    curr_txbd = curr_txbd->next;
+    num_bd--;
+  }
+  last_txbd->next = txch->free_head;
+
+  /* Initialize the descriptors for the RX channel */
+  rxch = &(cpswinst->rxch);
+  rxch->free_head = (volatile struct cpdma_rx_bd*)(cpswinst->cppi_ram_base +
+                                                   (SIZE_CPPI_RAM >> 1));
+
+  /* Allocate half of the CPPI RAM available for RX buffer dscriptors */
+  num_bd = (SIZE_CPPI_RAM >> 1) / sizeof(cpdma_rx_bd);
+  rxch->free_num = num_bd;
+
+  curr_rxbd = rxch->free_head;
+
+  /* Create the rx ring of buffer descriptors */
+  while(num_bd) {
+    curr_rxbd->next = curr_rxbd + 1;
+    curr_rxbd->flags_pktlen = CPDMA_BUF_DESC_OWNER;
+    last_rxbd = curr_rxbd;
+    curr_rxbd = curr_rxbd->next;
+    num_bd--;
+  }
+
+  last_rxbd->next = rxch->free_head;
+
+  /* We are going to receive starting from the free head */
+  rxch->recv_head = rxch->free_head;
+  rxch->recv_tail = last_rxbd;
+  cpswif_rxbd_alloc(cpswinst);
+
+  /* close the ring */
+  last_rxbd->next = NULL;
+
+  CPSWCPDMARxHdrDescPtrWrite(cpswinst->cpdma_base, (u32_t)(rxch->recv_head), 0);
+}
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from cpswif_init().
+ *
+ * @param cpswportif  The CPSW port interface structure pointer
+ * @return None
+ */
+static void
+cpswif_inst_init(struct cpswportif *cpswif){
+  u32_t inst_num = cpswif->inst_num;
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+
+  /* Reset the different modules */
+  CPSWSSReset(cpswinst->ss_base);
+  CPSWWrReset(cpswinst->wrpr_base);
+  CPSWSlReset(cpswinst->port[PORT_1].sliver_base);
+  CPSWSlReset(cpswinst->port[PORT_2].sliver_base);
+  CPSWCPDMAReset(cpswinst->cpdma_base);
+
+  /* Initialize MDIO */
+  MDIOInit(cpswinst->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);
+  delay(1);
+
+  CPSWALEInit(cpswinst->ale_base);
+
+  /* Set the port 0, 1 and 2 states to FORWARD */
+  CPSWALEPortStateSet(cpswinst->ale_base, 0, CPSW_ALE_PORT_STATE_FWD);
+  CPSWALEPortStateSet(cpswinst->ale_base, 1, CPSW_ALE_PORT_STATE_FWD);
+  CPSWALEPortStateSet(cpswinst->ale_base, 2, CPSW_ALE_PORT_STATE_FWD);
+
+#ifdef CPSW_DUAL_MAC_MODE
+  /* For Dual Mac Mode, Configure for VLAN Aware Mode */
+  CPSWALEVLANAwareSet(cpswinst->ale_base);
+  CPSWHostPortDualMacModeSet(cpswinst->host_port_base);
+
+#else  /*CPSW_DUAL_MAC_MODE */
+  /* For normal CPSW switch mode, set multicast entry. */
+  u8_t bcast_addr[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+  cpswif_ale_multicastentry_set(cpswinst,
+                                PORT_0_MASK | PORT_1_MASK | PORT_2_MASK,
+                                bcast_addr);
+  cpswif_ale_unicastentry_set(cpswinst, 0,
+                              (u8_t *)(&(cpswif->eth_addr)));
+
+  /* Set the ethernet address for both the ports */
+  CPSWPortSrcAddrSet(cpswinst->port[0].port_base,
+                    (u8_t *)(&(cpswif->eth_addr)));
+  CPSWPortSrcAddrSet(cpswinst->port[1].port_base,
+                    (u8_t *)(&(cpswif->eth_addr)));
+
+#endif /*CPSW_DUAL_MAC_MODE */
+
+  /* Enable the statistics. Lets see in case we come across any issues */
+  CPSWStatisticsEnable(cpswinst->ss_base);
+
+  /* Initialize the buffer descriptors for CPDMA */
+  cpswif_cpdma_init(cpswinst);
+
+  /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/
+  CPSWCPDMAEndOfIntVectorWrite(cpswinst->cpdma_base, CPSW_EOI_TX_PULSE);
+  CPSWCPDMAEndOfIntVectorWrite(cpswinst->cpdma_base, CPSW_EOI_RX_PULSE);
+
+  /* Enable the transmission and reception */
+  CPSWCPDMATxEnable(cpswinst->cpdma_base);
+  CPSWCPDMARxEnable(cpswinst->cpdma_base);
+
+  /* Enable the interrupts for channel 0 and for control core 0 */
+  CPSWCPDMATxIntEnable(cpswinst->cpdma_base, 0);
+  CPSWWrCoreIntEnable(cpswinst->wrpr_base, 0, 0, CPSW_CORE_INT_TX_PULSE);
+
+  CPSWCPDMARxIntEnable(cpswinst->cpdma_base, 0);
+  CPSWWrCoreIntEnable(cpswinst->wrpr_base, 0, 0, CPSW_CORE_INT_RX_PULSE);
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the functions cpswif_inst_init() and
+ * cpswif_port_init() to do low level initializations
+ *
+ * @param netif     The lwip network interface structure for this ethernetif
+ * @return ERR_OK   If the interface is initialized
+ *                  any other err_t on error
+ */
+err_t
+cpswif_init(struct netif *netif)
+{
+  struct cpswportif *cpswif = (struct cpswportif*)(netif->state);
+  static u32_t inst_init_flag = 0;
+  u32_t inst_num = cpswif->inst_num;
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /**
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
+
+  /* let us use the interface number to identify netif */
+#ifdef CPSW_DUAL_MAC_MODE
+  netif->num = (u8_t)(((cpswif->inst_num * MAX_SLAVEPORT_PER_INST)
+                      + cpswif->port_num - 1) & 0xFF);
+#else
+  netif->num = (u8_t)(cpswif->inst_num);
+#endif
+
+  /**
+   * We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...)
+   */
+  netif->output = etharp_output;
+  netif->linkoutput = cpswif_output;
+
+  /**
+   * Initialize an instance only once. Port initialization will be
+   * done separately.
+   */
+  if(((inst_init_flag >> inst_num) & 0x01) == 0) {
+    cpswif_inst_config(cpswif);
+    cpswif_inst_init(cpswif);
+    inst_init_flag |= (1 << inst_num);
+  }
+
+  if(cpswif_port_init(netif) != ERR_OK) {
+    return ERR_CONN;
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Handler for Receive interrupt. Packet processing is done in this
+ * interrupt handler itself.
+ *
+ * @param inst_num   the instance for which interrupt was generated
+ * @param netif_arr  the address of the array of netifs
+ * @return none
+ */
+void
+cpswif_rx_inthandler(const u32_t inst_num) {
+  struct cpswinst *const cpswinst = &cpsw_inst_data[inst_num];
+  sem_t* const rxsem = &cpswinst->rxsem;
+  const u32_t cpdma_base = cpswinst->cpdma_base;
+  unsigned int curr_bd;
+
+  sem_post(rxsem);
+
+  /* Get the bd which contains the earliest filled data */
+  curr_bd = CPSWCPDMARxCPRead(cpdma_base, 0);
+  /* Acknowledge that this packet is processed */
+  CPSWCPDMARxCPWrite(cpdma_base, 0, (unsigned int)curr_bd);
+  CPSWCPDMAEndOfIntVectorWrite(cpdma_base, CPSW_EOI_RX_PULSE);
+}
+
+static void
+process_input(const u32_t inst_num, struct netif *const netif_arr) {
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+  struct rxch *rxch;
+  volatile struct cpdma_rx_bd *curr_bd;
+  volatile struct pbuf *pbuf;
+  u32_t tot_len, if_num;
+
+#ifdef CPSW_DUAL_MAC_MODE
+  u32_t from_port;
+#endif
+
+  /* Get the rx channel pointer */
+  rxch = &(cpswinst->rxch);
+
+  /* Get the bd which contains the earliest filled data */
+  curr_bd = rxch->recv_head;
+
+  /**
+   * Process the receive buffer descriptors. When the DMA completes
+   * reception, OWNERSHIP flag will be cleared.
+   */
+  while((curr_bd->flags_pktlen & CPDMA_BUF_DESC_OWNER)
+           != CPDMA_BUF_DESC_OWNER) {
+
+#ifdef CPSW_DUAL_MAC_MODE
+    /**
+     * From which slave port the packet came from ?
+     * We will use this to decide to which netif the packet
+     * is to be forwarded to.
+     */
+    from_port = ((curr_bd->flags_pktlen) & CPDMA_BUF_DESC_FROM_PORT)
+                 >> CPDMA_BUF_DESC_FROM_PORT_SHIFT;
+#endif
+
+    /* Get the total length of the packet */
+    tot_len = (curr_bd->flags_pktlen) & CPDMA_BD_PKTLEN_MASK;
+
+    /* Get the pbuf which is associated with the current bd */
+    pbuf = curr_bd->pbuf;
+#ifdef LWIP_CACHE_ENABLED
+    /**
+     * Invalidate the cache lines of the pbuf including payload. Because
+     * the memory contents got changed by DMA.
+     */
+    CacheDataInvalidateBuff((u32_t)pbuf, (PBUF_LEN_MAX + SIZEOF_STRUCT_PBUF));
+#endif
+
+    /* Update the len and tot_len fields for the pbuf in the chain */
+    pbuf->len = (u16_t)(tot_len);
+    pbuf->tot_len = (u16_t)(tot_len);
+
+    curr_bd->flags_pktlen = CPDMA_BUF_DESC_OWNER;
+
+    /* Adjust the link statistics */
+    LINK_STATS_INC(link.recv);
+
+#ifdef CPSW_DUAL_MAC_MODE
+    if_num = (inst_num * MAX_SLAVEPORT_PER_INST) + from_port - 1;
+#else
+    if_num = inst_num;
+#endif
+    struct netif * netif = netif_arr + if_num;
+    /* Process the packet */
+    if(netif->input((struct pbuf *)pbuf, netif) != ERR_OK) {
+      /* Adjust the link statistics */
+      LINK_STATS_INC(link.memerr);
+      LINK_STATS_INC(link.drop);
+    }
+
+    curr_bd = curr_bd->next;
+
+    /* One more buffer descriptor is free now */
+    rxch->free_num++;
+
+    /**
+     * If the DMA engine took the NULL pointer, we dont have any bd to
+     * process until new bd's are allocated.
+     */
+    if(curr_bd == NULL) {
+      rxch->recv_head = rxch->free_head;
+      break;
+    }
+    rxch->recv_head = curr_bd;
+  }
+
+  /* We got some bd's freed; Allocate them */
+  cpswif_rxbd_alloc(cpswinst);
+}
+
+static void
+rx_thread_function(void* arg) {
+struct netif *const netif = arg;
+struct cpswportif * const cpswif = netif->state;
+const u32_t inst_num = cpswif->inst_num;
+struct cpswinst *const cpswinst = &cpsw_inst_data[inst_num];
+sem_t *const rxsem = &cpswinst->rxsem;
+while (1) {
+        sem_wait(rxsem);
+        process_input(inst_num, netif);
+	sched_yield();
+    }
+}
+
+/**
+ * Handler for CPSW Transmit interrupt
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return none
+ */
+void
+cpswif_tx_inthandler(const u32_t inst_num) {
+  struct cpswinst *const cpswinst = &cpsw_inst_data[inst_num];
+  sem_t* const txsem = &cpswinst->txsem;
+  const u32_t cpdma_base = cpswinst->cpdma_base;
+  unsigned int curr_bd;
+
+  sem_post(txsem);
+
+  /* Get the bd which contains the earliest filled data */
+  curr_bd = CPSWCPDMATxCPRead(cpdma_base, 0);
+  /* Acknowledge that this packet is processed */
+  CPSWCPDMATxCPWrite(cpdma_base, 0, (unsigned int)curr_bd);
+  CPSWCPDMAEndOfIntVectorWrite(cpdma_base, CPSW_EOI_TX_PULSE);
+}
+
+static void process_tx_end(const u32_t inst_num)
+{
+  struct txch *txch;
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+  volatile struct cpdma_tx_bd *curr_bd, *send_head;
+  volatile u32_t cnt = 0xFFFF;
+
+  txch = &(cpswinst->txch);
+
+  send_head = txch->send_head;
+
+  curr_bd = send_head;
+
+  /* Check for correct start of packet */
+  while((curr_bd->flags_pktlen) & CPDMA_BUF_DESC_SOP) {
+
+    /* Make sure that the transmission is over */
+    while(((curr_bd->flags_pktlen & CPDMA_BUF_DESC_OWNER)
+          == CPDMA_BUF_DESC_OWNER) && ((--cnt) != 0));
+
+    /* If CPDMA failed to transmit, give it a chance once more */
+    if(0 == cnt) {
+      CPSWCPDMATxHdrDescPtrWrite(cpswinst->cpdma_base,
+                                 (u32_t)(curr_bd), 0);
+      return;
+    }
+
+    /* One buffer descriptor is free now */
+    txch->free_num++;
+
+    /* Traverse till the end of packet is reached */
+    while(((curr_bd->flags_pktlen) & CPDMA_BUF_DESC_EOP) != CPDMA_BUF_DESC_EOP) {
+      curr_bd = curr_bd->next;
+
+      /* As this bd is not the end, its free now */
+      txch->free_num++;
+
+      if(txch->free_num == (SIZE_CPPI_RAM >> 1) / sizeof(cpdma_tx_bd)) {
+        break;
+      }
+    }
+
+    send_head->flags_pktlen &= ~(CPDMA_BUF_DESC_SOP);
+    curr_bd->flags_pktlen &= ~(CPDMA_BUF_DESC_EOP);
+
+    /**
+     * If there are no more data transmitted, the next interrupt
+     * shall happen with the pbuf associated with the free_head
+     */
+    if(curr_bd->next == NULL) {
+      txch->send_head = txch->free_head;
+    } else {
+      txch->send_head = curr_bd->next;
+    }
+
+    pbuf_free((struct pbuf *)curr_bd->pbuf);
+
+    LINK_STATS_INC(link.xmit);
+
+    send_head = txch->send_head;
+    curr_bd = send_head;
+  }
+}
+
+static void
+tx_thread_function(void* arg) {
+struct netif * const netif = arg;
+struct cpswportif * const cpswif = netif->state;
+const u32_t inst_num = cpswif->inst_num;
+struct cpswinst *const cpswinst = &cpsw_inst_data[inst_num];
+sem_t* const txsem = &cpswinst->txsem;
+sys_mutex_t* const txmtx = &cpswinst->txmtx;
+while (1) {
+        /* Wait for receive task to wakeup */
+        sem_wait(txsem);
+        sys_mutex_lock(txmtx);
+        process_tx_end(inst_num);
+        sys_mutex_unlock(txmtx);
+	sched_yield();
+    }
+}
+
+/**
+ * Gets the netif status
+ *
+ * @param   netif   The netif whoes status to be checked
+ * @return  The netif status
+ */
+u32_t
+cpswif_netif_status(struct netif *netif) {
+  return ((u32_t)(netif_is_up(netif)));
+}
+
+/**
+ * Returns the link status
+ *
+ * @param   inst_num      The instance number of the module
+ * @param   slv_port_num  The slave port number for the module
+ *
+ * @return  the link status
+ */
+u32_t
+cpswif_link_status(u32_t inst_num, u32_t slv_port_num) {
+
+  struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
+
+  return (PhyLinkStatusGet(cpswinst->mdio_base,
+                           cpswinst->port[slv_port_num - 1].phy_addr, 3));
+}
+
+/**
+ * Checks the value is in the range of min and max
+ *
+ * @param   vlaue      Value
+ * @param   min        Minimum Value
+ * @param   max        Maximum Value
+ *
+ * @return  the status
+ */
+static u32_t
+check_valid(u32_t value, u32_t min, u32_t max) {
+  if ((min <= value) && (value <= max))
+    return TRUE;
+  else
+    return FALSE;
+}
+
+/*
+ * Executes following CPSW Configutarions
+ * Switch Configuration (CPSW_SWITCH_CONFIG has to be defined)
+ *  1 - Add a multicast entry
+ *  2 - Add a unicast entry
+ *  3 - Add a OUI entry
+ *  4 - Search address in entry list
+ *  5 - Delete a multicast entry
+ *  6 - Delete a unicast entry
+ *  7 - Adds a vlan entry
+ *  8 - Search vlan in entry list
+ *  9 - Delete vlan
+ * 10 - Configure Port Vlan (ID, CFI, PRI)
+ * 11 - Age Out the Untouched entries of ALE Table
+ * 12 - Print Dump of Switch
+ * 13 - Print Dump of Switch Config
+ * 14 - ALE VLAN Aware Config
+ * 15 - Configure Rate Limit for TX or RX
+ * 16 - Enable Engress Check
+ * 17 - Set port unknown VLAN info
+ * 18 - Enable MAC Auth
+ * 19 - Configure Port State
+ * Phy Configuration
+ *  1 - Configure PHY of a port
+ *
+ * @param   cpsw_switch_config  parameters required for configuration
+ *
+ * @return  None
+*/
+void
+cpsw_switch_configuration(struct cpsw_config *cpsw_config) {
+  struct cpswinst *cpswinst = &cpsw_inst_data[cpsw_config->cpsw_inst];
+  struct cpsw_phy_param *cpsw_phy_param = cpsw_config->phy_param;
+#ifdef CPSW_SWITCH_CONFIG
+  struct cpsw_switch_param *cpsw_switch_param = cpsw_config->switch_param;
+  s32_t ret;
+#endif /* CPSW_SWITCH_CONFIG */
+
+  switch (cpsw_config->cmd) {
+#ifdef CPSW_SWITCH_CONFIG
+    case CONFIG_SWITCH_ADD_MULTICAST:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, ADDR_TYPE_MULTICAST)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_mask, MIN_PORT_MASK,
+                      MAX_PORT_MASK)) {
+        cpsw_config->ret = ERR_PORT_MASK;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->super, MIN_SUPER, MAX_SUPER)) {
+        cpsw_config->ret = ERR_SUPER;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->fwd_state, MIN_MCAST_FWD_STATE,
+                      MAX_MCAST_FWD_STATE)) {
+        cpsw_config->ret = ERR_MCAST_FWD_STATE;
+        break;
+      }
+
+      if (cpsw_switch_param->vid == 0)
+        ret = cpswif_ale_multicastentry_add(cpswinst,
+                                            cpsw_switch_param->port_mask,
+                                            cpsw_switch_param->addr,
+                                            cpsw_switch_param->super,
+                                            cpsw_switch_param->fwd_state);
+      else
+        ret = cpswif_ale_vlan_add_mcast(cpswinst, cpsw_switch_param->vid,
+                                        cpsw_switch_param->port_mask,
+                                        cpsw_switch_param->addr,
+                                        cpsw_switch_param->super,
+                                        cpsw_switch_param->fwd_state);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_ADD_UNICAST:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, ADDR_TYPE_UNICAST)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->ucast_flags, MIN_UCAST_FLAGS,
+                      MAX_UCAST_FLAGS)) {
+        cpsw_config->ret = ERR_UCAST_FLAGS;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->ucast_type, MIN_UCAST_FLAGS,
+                      MAX_UCAST_FLAGS)) {
+        cpsw_config->ret = ERR_UCAST_FLAGS;
+        break;
+      }
+
+      if (cpsw_switch_param->vid == 0)
+        ret = cpswif_ale_unicastentry_add(cpswinst, cpsw_switch_param->port_num,
+                                          cpsw_switch_param->addr,
+                                          cpsw_switch_param->ucast_flags,
+                                          cpsw_switch_param->ucast_type);
+      else
+        ret = cpswif_ale_vlan_add_ucast(cpswinst, cpsw_switch_param->vid,
+                                        cpsw_switch_param->port_num,
+                                        cpsw_switch_param->addr,
+                                        cpsw_switch_param->ucast_flags,
+                                        cpsw_switch_param->ucast_type);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_ADD_OUI:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, ADDR_TYPE_UNICAST)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      ret = cpswif_ale_OUI_add(cpswinst, cpsw_switch_param->addr);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_FIND_ADDR:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, 0)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      ret = cpswif_ale_entry_match_addr(cpswinst, cpsw_switch_param->addr,
+                                        cpsw_switch_param->vid);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_DEL_MULTICAST:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, ADDR_TYPE_MULTICAST)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_mask, MIN_PORT_MASK,
+                      MAX_PORT_MASK)) {
+        cpsw_config->ret = ERR_PORT_MASK;
+        break;
+      }
+
+      if (cpsw_switch_param->vid == 0)
+        ret = cpswif_ale_multicastentry_del(cpswinst, cpsw_switch_param->port_mask,
+                                            cpsw_switch_param->addr);
+      else
+        ret = cpswif_ale_vlan_del_mcast(cpswinst, cpsw_switch_param->vid,
+                                        cpsw_switch_param->port_mask,
+                                        cpsw_switch_param->addr);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_DEL_UNICAST:
+    {
+      if (!check_valid_addr(cpsw_switch_param->addr, ADDR_TYPE_UNICAST)) {
+        cpsw_config->ret = ERR_ADDR;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (cpsw_switch_param->vid == 0)
+        ret = cpswif_ale_unicastentry_del(cpswinst, cpsw_switch_param->port_num,
+                                          cpsw_switch_param->addr);
+      else
+        ret = cpswif_ale_vlan_del_ucast(cpswinst, cpsw_switch_param->vid,
+                                        cpsw_switch_param->port_num,
+                                        cpsw_switch_param->addr);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_ADD_VLAN:
+    {
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->reg_multi, MIN_VLAN_MCAST_REG,
+                      MAX_VLAN_MCAST_REG)) {
+        cpsw_config->ret = ERR_VLAN_MCAST_REG;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->unreg_multi, MIN_VLAN_MCAST_UNREG,
+                      MAX_VLAN_MCAST_UNREG)) {
+        cpsw_config->ret = ERR_VLAN_MCAST_UNREG;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->untag_port, MIN_VLAN_UNTAG,
+                      MAX_VLAN_UNTAG)) {
+        cpsw_config->ret = ERR_VLAN_MCAST_UNTAG;
+        break;
+      }
+
+      ret = cpswif_ale_vlan_add(cpswinst, cpsw_switch_param->vid,
+                                cpsw_switch_param->port_num,
+                                cpsw_switch_param->untag_port,
+                                cpsw_switch_param->reg_multi,
+                                cpsw_switch_param->unreg_multi);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_FIND_VLAN:
+    {
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      ret = cpswif_ale_entry_match_vlan(cpswinst, cpsw_switch_param->vid);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_DEL_VLAN:
+    {
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      ret = cpswif_ale_vlan_del(cpswinst, cpsw_switch_param->vid,
+                                cpsw_switch_param->port_num);
+
+      if (ret == ERR_VAL)
+        cpsw_config->ret = ERR_FAIL;
+      else
+        cpsw_config->ret = ret;
+
+      break;
+    }
+
+    case CONFIG_SWITCH_PORT_VLAN_CONFIG:
+    {
+      if (!check_valid(cpsw_switch_param->vid, MIN_VLANID, MAX_VLANID)) {
+        cpsw_config->ret = ERR_VLANID;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->cfi_port, MIN_CFI, MAX_CFI)) {
+        cpsw_config->ret = ERR_CFI;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->prio_port, MIN_PRI, MAX_PRI)) {
+        cpsw_config->ret = ERR_PRI;
+        break;
+      }
+
+      if (cpsw_switch_param->port_num == 0)
+          CPSWPortVLANConfig(cpswinst->host_port_base, cpsw_switch_param->vid,
+                             cpsw_switch_param->cfi_port,
+                             cpsw_switch_param->prio_port);
+      else if (cpsw_switch_param->port_num <= 2)
+          CPSWPortVLANConfig(
+                        cpswinst->port[cpsw_switch_param->port_num - 1].port_base,
+                        cpsw_switch_param->vid,
+                        cpsw_switch_param->cfi_port,
+                        cpsw_switch_param->prio_port);
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_AGEOUT:
+    {
+      CPSWALEAgeOut(cpswinst->ale_base);
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_DUMP:
+    {
+      u32_t cnt = 0;
+
+      for(cnt = 0; cnt <= MAX_ALE_ENTRIES; cnt++)
+      {
+        CPSWALETableEntryGet(cpswinst->ale_base, cnt,
+                             cpsw_config->buf[cnt]);
+      }
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_CONFIG_DUMP:
+    {
+
+      if (!check_valid(cpsw_switch_param->ale_tbl_index, MIN_ALE_ENTRY_IDX,
+                      MAX_ALE_ENTRY_IDX)) {
+        cpsw_config->ret = ERR_ALE_ENTRY_IDX;
+        break;
+      }
+
+      CPSWALETableEntryGet(cpswinst->ale_base, cpsw_switch_param->ale_tbl_index,
+                           cpsw_config->ale_entry);
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_VLANAWARE:
+    {
+      if (!check_valid(cpsw_switch_param->vlan_aware, MIN_VLANAWARE,
+                      MAX_VLANAWARE)) {
+        cpsw_config->ret = ERR_VLANAWARE;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->drop_packet, MIN_ALE_VLANAWARE,
+                      MAX_ALE_VLANAWARE)) {
+        cpsw_config->ret = ERR_ALE_VLANAWARE;
+        break;
+      }
+
+      if (!cpsw_switch_param->vlan_aware)
+        CPSWVLANAwareDisable(cpswinst->ale_base);
+      else
+        CPSWVLANAwareEnable(cpswinst->ale_base);
+
+      if (!cpsw_switch_param->drop_packet)
+        CPSWALEVLANAwareClear(cpswinst->ale_base);
+      else
+        CPSWALEVLANAwareSet(cpswinst->ale_base);
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_RATELIMIT:
+    {
+      if (!check_valid(cpsw_switch_param->enable, MIN_ENABLE, MAX_ENABLE)) {
+        cpsw_config->ret = ERR_ENABLE;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->direction, MIN_DIRECTION,
+                       MAX_DIRECTION)) {
+        cpsw_config->ret = ERR_DIRECTION;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->addr_type, MIN_ADDR_TYPE, MAX_ADDR_TYPE)) {
+        cpsw_config->ret = ERR_ADDR_TYPE;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->limit, MIN_LIMIT, MAX_LIMIT)) {
+        cpsw_config->ret = ERR_LIMIT;
+        break;
+      }
+
+      cpswif_rate_limit(cpswinst, cpsw_switch_param->enable,
+                        cpsw_switch_param->direction,
+                        cpsw_switch_param->port_num, cpsw_switch_param->addr_type,
+                        cpsw_switch_param->limit);
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_VID_INGRESS_CHECK:
+    {
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      CPSWALEVIDIngressCheckSet(cpswinst->ale_base, cpsw_switch_param->port_num);
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_ADD_UNKNOWN_VLAN_INFO:
+    {
+      if (!check_valid(cpsw_switch_param->unknown_vlan, MIN_UNKNOWN_VLAN,
+                      MAX_UNKNOWN_VLAN)) {
+        cpsw_config->ret = ERR_UNKNOWN_VLAN;
+        break;
+      }
+
+      if (cpsw_switch_param->unknown_vlan == ALE_PORT_UNTAGGED_EGRESS) {
+        if (!check_valid(cpsw_switch_param->untag_port, MIN_VLAN_UNTAG,
+                        MAX_VLAN_UNTAG)) {
+          cpsw_config->ret = ERR_VLAN_MCAST_UNTAG;
+          break;
+        }
+
+        CPSWALEUnknownUntaggedEgressSet(cpswinst->ale_base,
+                                        cpsw_switch_param->untag_port);
+      } else if (cpsw_switch_param->unknown_vlan ==
+                 ALE_PORT_UNKNOWN_REG_MCAST_FLOOD) {
+        if (!check_valid(cpsw_switch_param->reg_multi, MIN_VLAN_MCAST_REG,
+                        MAX_VLAN_MCAST_REG)) {
+          cpsw_config->ret = ERR_VLAN_MCAST_REG;
+          break;
+        }
+
+        CPSWALEUnknownRegFloodMaskSet(cpswinst->ale_base,
+                                      cpsw_switch_param->reg_multi);
+      } else if (cpsw_switch_param->unknown_vlan ==
+                 ALE_PORT_UNKNOWN_UNREG_MCAST_FLOOD) {
+        if (!check_valid(cpsw_switch_param->unreg_multi, MIN_VLAN_MCAST_UNREG,
+                        MAX_VLAN_MCAST_UNREG)) {
+          cpsw_config->ret = ERR_VLAN_MCAST_UNREG;
+          break;
+        }
+
+        CPSWALEUnknownUnRegFloodMaskSet(cpswinst->ale_base,
+                                        cpsw_switch_param->unreg_multi);
+      } else if (cpsw_switch_param->unknown_vlan ==
+                 ALE_PORT_UNKNOWN_VLAN_MEMBER) {
+        if (!check_valid(cpsw_switch_param->port_mask, MIN_PORT_MASK,
+                        MIN_PORT_MASK)) {
+          cpsw_config->ret = ERR_VLAN_MCAST_UNREG;
+          break;
+        }
+
+        CPSWALEUnknownMemberListSet(cpswinst->ale_base,
+                                    cpsw_switch_param->port_mask);
+      }
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_MACAUTH:
+    {
+      if (!check_valid(cpsw_switch_param->mac_auth, MIN_MAC_AUTH, MAX_MAC_AUTH)) {
+        cpsw_config->ret = ERR_MAC_AUTH;
+        break;
+      }
+
+      if (!cpsw_switch_param->mac_auth)
+        CPSWALEAUTHModeClear(cpswinst->ale_base);
+      else
+        CPSWALEAUTHModeSet(cpswinst->ale_base);
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    case CONFIG_SWITCH_PORT_STATE:
+    {
+      if (!check_valid(cpsw_switch_param->port_num, MIN_PORT, MAX_PORT)) {
+        cpsw_config->ret = ERR_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_switch_param->port_state, MIN_PORT_STATE,
+                      MAX_PORT_STATE)) {
+        cpsw_config->ret = ERR_PORT_STATE;
+        break;
+      }
+
+      CPSWALEPortStateSet(cpswinst->ale_base, cpsw_switch_param->port_num,
+                          cpsw_switch_param->port_state);
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+#endif /* CPSW_SWITCH_CONFIG */
+
+    case CONFIG_SWITCH_SET_PORT_CONFIG:
+    {
+      if (!check_valid(cpsw_phy_param->slv_port_num, MIN_SLV_PORT,
+                       MAX_SLV_PORT)) {
+        cpsw_config->ret = ERR_SLV_PORT;
+        break;
+      }
+
+      if (!check_valid(cpsw_phy_param->autoneg, MIN_AUTONEG, MAX_AUTONEG)) {
+        cpsw_config->ret = ERR_AUTONEG;
+        break;
+      }
+
+      if (TRUE == cpsw_phy_param->autoneg) {
+        if (!check_valid(cpsw_phy_param->config, MIN_PHY_CONFIG,
+                         MAX_PHY_CONFIG)) {
+          cpsw_config->ret = ERR_PHY_CONFIG;
+          break;
+        }
+      } else {
+        if (!check_valid(cpsw_phy_param->speed, MIN_SPEED, MAX_SPEED)) {
+          cpsw_config->ret = ERR_SPEED;
+          break;
+        }
+
+        if (!check_valid(cpsw_phy_param->duplex, MIN_DUPLEX, MAX_DUPLEX)) {
+          cpsw_config->ret = ERR_DUPLEX;
+          break;
+        }
+      }
+
+      if (cpsw_phy_param->autoneg)
+        cpswif_phy_autoneg(cpswinst, cpsw_phy_param->slv_port_num,
+                                         cpsw_phy_param->config);
+      else
+        cpswif_phy_forced(cpswinst, cpsw_phy_param->slv_port_num,
+                                        cpsw_phy_param->speed,
+                                        cpsw_phy_param->duplex);
+
+      cpsw_config->ret = ERR_PASS;
+      break;
+    }
+
+    default:
+      cpsw_config->ret = ERR_INVAL;
+      break;
+  }
+}
diff --git a/cpsw/src/netif/delay.c b/cpsw/src/netif/delay.c
new file mode 100644
index 0000000..0f1b2a7
--- /dev/null
+++ b/cpsw/src/netif/delay.c
@@ -0,0 +1,6 @@
+#include <unistd.h>
+
+void delay(unsigned int ms)
+{
+	usleep(ms*1000);
+}
\ No newline at end of file
diff --git a/cpsw/src/netif/mdio.c b/cpsw/src/netif/mdio.c
new file mode 100755
index 0000000..9c6c18e
--- /dev/null
+++ b/cpsw/src/netif/mdio.c
@@ -0,0 +1,209 @@
+/**
+ *  \file   mdio.c
+ *
+ *  \brief  MDIO APIs.
+ *
+ *   This file contains the device abstraction layer APIs for MDIO.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/* HW Macros and Peripheral Defines */
+#include "hw_types.h"
+#include "hw_mdio.h"
+
+/* Driver APIs */
+#include "mdio.h"
+
+/*******************************************************************************
+*                       INTERNAL MACRO DEFINITIONS
+*******************************************************************************/
+#define PHY_REG_MASK                             (0x1Fu)
+#define PHY_ADDR_MASK                            (0x1Fu)
+#define PHY_DATA_MASK                            (0xFFFFu)
+#define PHY_REG_SHIFT                            (21u)
+#define PHY_ADDR_SHIFT                           (16u)
+
+/*******************************************************************************
+*                        API FUNCTION DEFINITIONS
+*******************************************************************************/
+
+/**
+ * \brief   Reads a PHY register using MDIO.
+ *
+ * \param   baseAddr      Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   regNum        Register Number to be read.
+ * \param   dataPtr       Pointer where the read value shall be written.
+ *
+ * \return  status of the read \n
+ *          TRUE - read is successful.\n
+ *          FALSE - read is not acknowledged properly.
+ *
+ **/
+unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
+                            unsigned int regNum, volatile unsigned short *dataPtr)
+{
+    /* Wait till transaction completion if any */
+    while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+    HWREG(baseAddr + MDIO_USERACCESS0)
+                           = (MDIO_USERACCESS0_READ | MDIO_USERACCESS0_GO
+                              |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
+                              |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT));
+
+    /* wait for command completion */
+    while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+    /* Store the data if the read is acknowledged */
+    if((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK)
+    {
+        *dataPtr = (unsigned short)((HWREG(baseAddr + MDIO_USERACCESS0))
+                                    & PHY_DATA_MASK);
+        return TRUE;
+    }
+
+    return FALSE;
+}
+
+/**
+ * \brief   Writes a PHY register using MDIO.
+ *
+ * \param   baseAddr      Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   regNum        Register Number to be read.
+ * \param   RegVal        Value to be written.
+ *
+ * \return  None
+ *
+ **/
+void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
+                     unsigned int regNum, unsigned short RegVal)
+{
+    /* Wait till transaction completion if any */
+    while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+
+    HWREG(baseAddr + MDIO_USERACCESS0)
+                               = (MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO
+                                  |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT)
+                                  |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)
+                                  | RegVal);
+
+    /* wait for command completion*/
+    while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+}
+/**
+ * \brief   Reads the alive status of all PHY connected to this MDIO.
+ *          The bit correponding to the PHY address will be set if the PHY
+ *          is alive.
+ *
+ * \param   baseAddr      Base Address of the MDIO Module Registers.
+ *
+ * \return  MDIO alive register state
+ *
+ **/
+unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)
+{
+    return (HWREG(baseAddr + MDIO_ALIVE));
+}
+
+/**
+ * \brief   Reads the link status of all PHY connected to this MDIO.
+ *          The bit correponding to the PHY address will be set if the PHY
+ *          link is active.
+ *
+ * \param   baseAddr      Base Address of the MDIO Module Registers.
+ *
+ * \return  MDIO link register state
+ *
+ **/
+unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)
+{
+    return (HWREG(baseAddr + MDIO_LINK));
+}
+
+/**
+ * \brief   Initializes the MDIO peripheral. This enables the MDIO state
+ *          machine, uses standard pre-amble and set the clock divider value.
+ *
+ * \param   baseAddr       Base Address of the MDIO Module Registers.
+ * \param   mdioInputFreq  The clock input to the MDIO module
+ * \param   mdioOutputFreq The clock output required on the MDIO bus
+ * \return  None
+ *
+ **/
+void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
+              unsigned int mdioOutputFreq)
+{
+   unsigned int clkDiv = (mdioInputFreq/mdioOutputFreq) - 1;
+
+   HWREG(baseAddr + MDIO_CONTROL) = ((clkDiv & MDIO_CONTROL_CLKDIV)
+                                     | MDIO_CONTROL_ENABLE 
+                                     | MDIO_CONTROL_PREAMBLE
+                                     | MDIO_CONTROL_FAULTENB);
+}
+
+/**
+ * \brief   Saves the MDIO register context. Note that only MDIO control 
+ *          register context is saved here.
+ *
+ * \param   baseAddr       Base Address of the MDIO Module Registers.
+ * \param   contextPtr     Pointer to the structure where MDIO context 
+ *                         needs to be saved.
+ * \return  None
+ *
+ **/
+void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr)
+{
+    contextPtr->mdioCtrl = HWREG(baseAddr + MDIO_CONTROL);
+}
+
+/**
+ * \brief   Restores the MDIO register context. Note that only MDIO control 
+ *          register context is restored here. Hence enough delay shall be
+ *          given after this API
+ *
+ * \param   baseAddr       Base Address of the MDIO Module Registers.
+ * \param   contextPtr     Pointer to the structure where MDIO context 
+ *                         needs to be restored from
+ * \return  None
+ *
+ **/
+void MDIOContextRestore(unsigned int baseAddr, MDIOCONTEXT *contextPtr)
+{
+    HWREG(baseAddr + MDIO_CONTROL) = contextPtr->mdioCtrl;
+}
+
+/***************************** End Of File ***********************************/
diff --git a/cpsw/src/netif/mmu.c b/cpsw/src/netif/mmu.c
new file mode 100755
index 0000000..8015541
--- /dev/null
+++ b/cpsw/src/netif/mmu.c
@@ -0,0 +1,184 @@
+/**
+ *  \file   mmu.c
+ *
+ *  \brief  APIs for configuring MMU
+ *
+ *  This file contains the APIs for configuring ARMv7a MMU.
+*/
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#include "mmu.h"
+#include "cp15.h"
+
+/*****************************************************************************
+**                      INTERNAL MACRO DEFINITIONS
+******************************************************************************/
+#define MMU_PAGETABLE_ENTRY_FAULT                (0x00)
+#define MMU_PAGEBOUND_SHIFT                      (20)
+#define MMU_PG_SUPSECT_SIZE_SHIFT                (14)
+#define MMU_PGADDR_MASK                          (0xFFF00000)
+#define MMU_PGTYPE_MASK                          (0x00040002)
+
+/*****************************************************************************
+**                         FUNCTION DEFINITIONS
+******************************************************************************/
+/**
+ * \brief   Initializes the Page Table with fault entries and configures CP15
+ *          registers required for MMU. The Page Table passed is the master
+ *          page table containing 4096 words, which will be defined by the
+ *          application.
+ *
+ * \param   masterPt      Master Page Table Base Address
+ *
+ * \return  None.
+ *
+ * \Note    The StarterWare support for MMU needs only master page table
+ *          configuration. Only a single level paging is supported. Also, only
+ *          TTB0 will be used for page table walking.
+ **/
+void MMUInit(unsigned int *masterPt)
+{
+    unsigned int idx;
+
+   /* Invalidate the TLB entries */
+    CP15TlbInvalidate();
+
+    /* Set domain access rights */
+    CP15DomainAccessClientSet();
+
+    /* Disable TEX remapping, Access Flag usage and alignment check */
+    CP15ControlFeatureDisable( CP15_CONTROL_TEXREMAP
+                               | CP15_CONTROL_ACCESSFLAG
+                               | CP15_CONTROL_ALIGN_CHCK
+                               | CP15_CONTROL_MMU);
+
+    /* Configure the TTB Control register to use only TTB0 */
+    CP15TtbCtlTtb0Config();
+
+    /* Se the master page table with fault entries */
+    for(idx = MMU_PAGETABLE_NUM_ENTRY; idx !=0; idx--)
+    {
+        *masterPt++ = MMU_PAGETABLE_ENTRY_FAULT;
+    }
+}
+
+/**
+ * \brief   Maps a specific region for Virtual Address to Physical Address
+ *          conversion. This API actually updates the corresponding page table
+ *          entries. The mapping for any region is such that Virtual Address
+ *          = Physical Address. \n
+ *          Any region can be mapped as per the attributes given. Regions
+ *          can be specified with Memory Type, Inner/Outer Cache settings,
+ *          Security settings and Access Permissions.
+ *
+ * \param   region      Memory Region to be mapped. This shall be a structure
+ *                      pointer of Type REGION *. The structure is detailed in
+ *                      mmu.h file. \n
+ *
+ *            Example Configuration: \n
+ *              A 512MB RAM memory region starting at address 0x80000000 can be
+ *              configured as shown below. The memory is to be cacheable, with
+ *              Inner Cache - Write Through Write Allocate and Outer Cache -
+ *              Write Back Write Allocate attributes. \n
+ *
+ *              REGION regionRam = { MMU_PGTYPE_SECTION, \n
+ *                                   0x80000000, \n
+ *                                   512,  \n
+ *                                   MMU_MEMTYPE_NORMAL_SHAREABLE
+ *                                     (MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA),\n
+ *                                   MMU_REGION_NON_SECURE, \n
+ *                                   MMU_AP_PRV_RW_USR_RW, \n
+ *                                   (unsigned int*)pageTable};
+ *
+ * \return  None.
+ *
+ * \Note    The regions specify the desired cache policies. However, enabling
+ *          of cache at all desired levels shall be done separately.
+ **/
+void MMUMemRegionMap(REGION *region)
+{
+    unsigned int *ptEntryPtr;
+    unsigned int ptEntry;
+    int idx;
+
+    /* Get the first entry in the page table to set */
+    ptEntryPtr = region->masterPtPtr +
+                 (region->startAddr >> MMU_PAGEBOUND_SHIFT);
+
+    /* Set the pointer to the last entry */
+    ptEntryPtr += (region->numPages - 1);
+
+    /* Get the start Address MSB 3 nibbles. Ignore extended address */
+    ptEntry = (region->startAddr & region->pgType) & MMU_PGADDR_MASK;
+
+    /*
+    ** Update the page table entry with memory attributes and
+    ** Access Permissions and Security.
+    ** All the regions will be marked as global.
+    */
+    ptEntry |= ((MMU_PGTYPE_MASK & region->pgType)
+                | region->accsCtrl | region->memAttrib
+                | region->secureType);
+
+    /* Set the entries in the page table for the region attributes */
+    for(idx = (region->numPages - 1); idx >= 0; idx--)
+    {
+       *ptEntryPtr-- = ptEntry + (idx << MMU_PAGEBOUND_SHIFT) ;
+    }
+}
+
+/**
+ * \brief   Updates the Translation Table Base with the address of Master Page
+ *          Table and enables MMU.
+ *
+ * \param   masterPt      Master Page Table Base Address
+ *
+ * \return  None.
+ *
+ * \Note    Only TTB0 is used for page table walking.
+ **/
+void MMUEnable(unsigned int *masterPt)
+{
+    /* Set TTB0 register */
+    CP15Ttb0Set((unsigned int)masterPt);
+
+    /* Enable MMU */
+    CP15MMUEnable();
+}
+
+/***************************** End Of File ***********************************/
+
diff --git a/cpsw/src/netif/phy.c b/cpsw/src/netif/phy.c
new file mode 100755
index 0000000..1ce9494
--- /dev/null
+++ b/cpsw/src/netif/phy.c
@@ -0,0 +1,402 @@
+/**
+ *  \file   phy.c
+ *
+ *  \brief  APIs for configuring ethernet PHYs
+ *
+ *   This file contains the device abstraction APIs for ethernet PHYs.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#include "hw_types.h"
+#include "mdio.h"
+#include "phy.h"
+
+#define PHY_ADV_VAL_MASK                 (0x01e0)
+#define PHY_GIG_ADV_VAL_MASK             (0x0300)
+
+/*******************************************************************************
+*                        API FUNCTION DEFINITIONS
+*******************************************************************************/
+/**
+ * \brief   Reads the PHY ID.
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ *
+ * \return  32 bit PHY ID (ID1:ID2)
+ *
+ **/
+unsigned int PhyIDGet(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+    unsigned int id = 0;
+    unsigned short data;
+
+    /* read the ID1 register */
+    MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID1, &data);
+
+    /* update the ID1 value */
+    id = data << PHY_ID_SHIFT;
+ 
+    /* read the ID2 register */
+    MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID2, &data);
+
+    /* update the ID2 value */
+    id |= data; 
+
+    /* return the ID in ID1:ID2 format */
+    return id;
+}
+
+/**
+ * \brief   Reads a register from the the PHY
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   regIdx        Index of the register to be read
+ * \param   regValAdr     address where value of the register will be written
+ *
+ * \return  status of the read
+ *
+ **/
+unsigned int PhyRegRead(unsigned int mdioBaseAddr, unsigned int phyAddr,
+                        unsigned int regIdx, unsigned short *regValAdr)
+{
+    return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, regIdx, regValAdr));
+}
+
+/**
+ * \brief   Writes a register with the input
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   regIdx        Index of the register to be read
+ * \param   regValAdr     value to be written
+ *
+ * \return  None
+ *
+ **/
+void PhyRegWrite(unsigned int mdioBaseAddr, unsigned int phyAddr,
+                 unsigned int regIdx, unsigned short regVal)
+{
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, regIdx, regVal);
+}
+
+/**
+ * \brief   Enables Loop Back mode
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ *
+ * \return  status after enabling.  \n
+ *          TRUE if loop back is enabled \n
+ *          FALSE if not able to enable
+ *
+ **/
+unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+    unsigned short data;
+
+    if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+    {
+        return FALSE;
+    }
+
+    data |= PHY_LPBK_ENABLE;
+
+    /* Enable loop back */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+
+    return TRUE;
+}
+
+/**
+ * \brief   Disables Loop Back mode
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ *
+ * \return  status after enabling.  \n
+ *          TRUE if loop back is disabled \n
+ *          FALSE if not able to disable
+ *
+ **/
+unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+    unsigned short data;
+
+    if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+    {
+        return FALSE;
+    }
+
+    data &= ~(PHY_LPBK_ENABLE);
+
+    /* Disable loop back */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+
+    return TRUE;
+}
+
+/**
+ * \brief   Resets the PHY
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   speed         Speed to be enabled
+ * \param   duplexMode    Duplex Mode
+ *
+ * \return  status after configuring \n
+ *          TRUE if configuration successful
+ *          FALSE if configuration failed
+ *
+ **/
+unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+    unsigned short data;
+
+    data = PHY_SOFTRESET;
+
+    /* Reset the phy */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+
+    /* wait till the reset bit is auto cleared */
+    while(data & PHY_SOFTRESET)
+    {
+        /* Read the reset */
+        if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE)
+        {
+            return FALSE;
+        }
+    }
+
+    return TRUE;
+}
+
+/**
+ * \brief   Configures the PHY for a given speed and duplex mode.
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   speed         Speed to be enabled
+ * \param   duplexMode    Duplex Mode
+ *
+ * \return  status after configuring \n
+ *          TRUE if configuration successful
+ *          FALSE if configuration failed
+ *
+ **/
+unsigned int PhyConfigure(unsigned int mdioBaseAddr, unsigned int phyAddr,
+                          unsigned short speed, unsigned short duplexMode)
+{
+    /* Set the configurations */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, (speed | duplexMode));
+
+    return TRUE;
+}
+
+/**
+ * \brief   This function ask the phy device to start auto negotiation.
+ *          
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   advVal        Autonegotiation advertisement value
+ * \param   gigAdvVal     Gigabit capability advertisement value
+ *          advVal can take the following any OR combination of the values \n
+ *               PHY_100BTX - 100BaseTX \n
+ *               PHY_100BTX_FD - Full duplex capabilty for 100BaseTX \n
+ *               PHY_10BT - 10BaseT \n
+ *               PHY_10BT_FD - Full duplex capability for 10BaseT \n
+ *          gigAdvVal can take one of the following values \n
+ *               PHY_NO_1000BT - No 1000Base-T capability\n
+ *               PHY_1000BT_FD - Full duplex capabilty for 1000 Base-T \n
+ *               PHY_1000BT_HD - Half duplex capabilty for 1000 Base-T \n
+ *               FALSE - It is passed as an argument if phy dosen't support
+ *                       Giga bit capability 
+ *
+ * \return  status after autonegotiation \n
+ *          TRUE if autonegotiation started
+ *          FALSE if autonegotiation not started
+ *
+ **/
+unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr, unsigned int phyAddr,
+                              unsigned short *advPtr, unsigned short *gigAdvPtr)
+{
+    volatile unsigned short data;
+    volatile unsigned short anar;
+
+    if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+    {
+        return FALSE;
+    }
+   
+    data |= PHY_AUTONEG_ENABLE;
+
+    if (*gigAdvPtr != 0)
+    {
+        /* Set phy for gigabit speed */
+        data &= PHY_SPEED_MASK;
+        data |= PHY_SPEED_1000MBPS;
+    }
+   
+    /* Enable Auto Negotiation */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+
+    if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+    {
+        return FALSE;
+    }
+
+    /* Write Auto Negotiation capabilities */
+    MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, &anar);
+    anar &= ~PHY_ADV_VAL_MASK;
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, (anar |(*advPtr)));
+
+    /* Write Auto Negotiation Gigabyte capabilities */
+    anar = 0;
+    MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_1000BT_CONTROL, &anar);
+    anar &= ~PHY_GIG_ADV_VAL_MASK;
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_1000BT_CONTROL,
+                    (anar |(*gigAdvPtr)));
+
+    data |= PHY_AUTONEG_RESTART;
+
+    /* Start Auto Negotiation */
+    MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+
+    return TRUE;
+}
+
+/**
+ * \brief   Returns the status of Auto Negotiation completion.
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ *
+ * \return  Auto negotiation completion status \n
+ *          TRUE if auto negotiation is completed
+ *          FALSE if auto negotiation is not completed
+ **/
+unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr, unsigned int phyAddr)
+{
+    volatile unsigned short data;
+
+    MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data);
+
+    /* Auto negotiation completion status */
+    if(PHY_AUTONEG_COMPLETE == (data & (PHY_AUTONEG_STATUS)))
+    {
+        return TRUE;
+    }
+  
+    return FALSE;
+}
+
+/**
+ * \brief   Reads the Link Partner Ability register of the PHY.
+ *
+ * \param   mdioBaseAddr    Base Address of the MDIO Module Registers.
+ * \param   phyAddr         PHY Adress.
+ * \param   ptnerAblty      Pointer to which partner ability will be written.
+ * \param   gbpsPtnerAblty  Pointer to which Giga bit capability will be written.
+ *
+ *          gbpsPtnerAblty can take following Macros.\n
+ *
+ *          TRUE  - It is passed as argument if phy supports Giga bit capability.\n
+ *          FALSE - It is passed as argument if phy dosen't supports Giga bit
+ *                  capability.\n
+ *
+ * \return  status after reading \n
+ *          TRUE if reading successful
+ *          FALSE if reading failed
+ **/
+unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr, 
+                                  unsigned int phyAddr,
+                                  unsigned short *ptnerAblty,
+                                  unsigned short *gbpsPtnerAblty)
+{
+    unsigned int status;
+
+    status = MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY,
+                           ptnerAblty);
+
+    if (*gbpsPtnerAblty != 0)
+    {
+        status = status | MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_1000BT_STATUS,
+                                         gbpsPtnerAblty);
+    }
+
+    return status;
+}
+
+/**
+ * \brief   Reads the link status of the PHY.
+ *
+ * \param   mdioBaseAddr  Base Address of the MDIO Module Registers.
+ * \param   phyAddr       PHY Adress.
+ * \param   retries       The number of retries before indicating down status
+ *
+ * \return  link status after reading \n
+ *          TRUE if link is up
+ *          FALSE if link is down \n
+ *
+ * \note    This reads both the basic status register of the PHY and the
+ *          link register of MDIO for double check
+ **/
+unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr,
+                              unsigned int phyAddr,
+                              volatile unsigned int retries)
+{
+    volatile unsigned short linkStatus;
+ 
+    retries++;   
+    while (retries)
+    {
+        /* First read the BSR of the PHY */
+        MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &linkStatus);
+
+        if(linkStatus & PHY_LINK_STATUS)
+        {
+            return TRUE;
+        }
+   
+        retries--;
+    }
+
+    return FALSE;
+}
+
+/**************************** End Of File ***********************************/
diff --git a/cpsw/src/perf.c b/cpsw/src/perf.c
new file mode 100755
index 0000000..689a587
--- /dev/null
+++ b/cpsw/src/perf.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "arch/perf.h"
+
+void
+perf_init(char *fname)
+{
+}
diff --git a/file-import.yaml b/file-import.yaml
index da21ec2..9e362bf 100644
--- a/file-import.yaml
+++ b/file-import.yaml
@@ -45,15 +45,6 @@ files-to-import:
     - src/api/netifapi.c
     - src/api/if_api.c
     - src/api/err.c
-    - src/api/sockets.c
-    - src/api/netdb.c
-    - src/api/netbuf.c
-    - src/api/api_lib.c
-    - src/api/api_msg.c
-    - src/api/tcpip.c
-    - src/api/netifapi.c
-    - src/api/if_api.c
-    - src/api/err.c
     - src/netif/ethernet.c
     - src/netif/bridgeif_fdb.c
     - src/netif/lowpan6.c
diff --git a/lwip.py b/lwip.py
index 848ff16..037a730 100644
--- a/lwip.py
+++ b/lwip.py
@@ -29,11 +29,13 @@ from rtems_waf import rtems
 import yaml
 import os
 
-source_files = []
-driver_source = []
-include_files = {}
 
 def build(bld):
+    source_files = []
+    common_includes = './lwip/src/include ./uLan/ports/os/rtems ./rtemslwip/include '
+    driver_source = []
+    drv_incl = ' '
+
     arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
                                             bld.env.RTEMS_ARCH_BSP)
     with open('file-import.yaml', 'r') as cf:
@@ -41,11 +43,11 @@ def build(bld):
         for f in files['files-to-import']:
             if f[-2:] == '.c':
                 source_files.append(os.path.join('./lwip', f))
-        
-        for f in os.listdir('./uLan/ports/driver/tms570_emac'):
-            if f[-2:] == '.c':
-                driver_source.append(os.path.join('./uLan/ports/driver/tms570_emac', f))
+
     source_files.append('./uLan/ports/os/rtems/arch/sys_arch.c')
+    source_files.append('./rtemslwip/common/syslog.c')
+    source_files.append('./rtemslwip/common/rtems_lwip_io.c')
+    source_files.append('./rtemslwip/common/rtems_lwip_sysdefs.c')
     
     #source_files.append('./lwip/ports/port/sys_arch.c')
     #source_files.append('./lwip/ports/port/perf.c')
@@ -54,24 +56,65 @@ def build(bld):
     #source_files.append('./lwip/ports/port/netif/pcapif.c')
     #source_files.append('./lwip/ports/port/netif/sio.c')
     #source_files.append('./lwip/ports/port/netif/tapif.c')
+    
+    def walk_sources(path):
+        sources = []
+        for root, dirs, files in os.walk(path):
+            for name in files:
+                ext = os.path.splitext(name)[1]
+                src_root = os.path.split(root)
+                path = os.path.join(src_root[0], src_root[1])
+                if ext == '.c' or ext == '.S':
+                    sources.append(os.path.join(path, name))
+        return sources
+
+    # These files will not compile for BSPs other than TMS570
+    if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-tms570ls3137_hdk'):
+        drv_incl += './uLan/ports/driver/tms570_emac ./uLan/ports/os '
+        driver_source.extend(walk_sources('./uLan/ports/driver/tms570_emac'))
+
+    # These files will only compile for BeagleBone BSPs
+    if bld.env.RTEMS_ARCH_BSP.startswith('arm-rtems6-beaglebone'):
+        driver_source.extend(walk_sources('./rtemslwip/beaglebone'))
+        drv_incl += './rtemslwip/beaglebone ./cpsw/src/include '
+        driver_source.extend(walk_sources('./cpsw/src'))
 
     bld(features ='c',
         target='lwip_obj',
-        includes='./include ./lwip/src/include ./uLan/ports/os ./uLan/ports/driver/tms570_emac ./uLan/ports/os/rtems',
+        cflags='-g -Wall -O0',
+        includes=drv_incl + common_includes,
         source=source_files,
         )
-#    bld(features ='c',
-#        target='lwip_drv_obj',
-#        includes='./ ../ ../../src/include ./include ./lwip/src/include ./lwip/ports/os/rtems ./lwip/ports/os ./lwip/ports/drivers ' + os.path.relpath(os.path.join(arch_lib_path,'include')),
-#        source=driver_source,
-#        )
+
+    bld(features ='c',
+        target='driver_obj',
+        cflags='-g -Wall -O0',
+        includes=drv_incl + common_includes + os.path.relpath(os.path.join(bld.env.PREFIX, arch_lib_path,'include')) ,
+        source=driver_source,
+        )
     bld(features='c cstlib',
         target = 'lwip',
-        use=['lwip_obj'])
+        cflags='-g -Wall -O0',
+        use=['lwip_obj', 'driver_obj'])
 
     bld.program(features='c',
-                target='test01.exe',
-                source='./lwip/test/sample_app.c',
+                target='networking01.exe',
+                source='./rtemslwip/test/networking01/sample_app.c',
+                cflags='-g -Wall -O0',
                 use='lwip',
                 lib=['rtemscpu', 'rtemsbsp', 'rtemstest', 'lwip'],
-                includes='./include ./uLan/ports/os/rtems ./uLan/ports/os ./lwip/src/include ./uLan/ports/os/rtems ./lwip/test/' + os.path.relpath(os.path.join(arch_lib_path,'include')))
+                includes=drv_incl + common_includes + './rtemslwip/test/ ' + os.path.relpath(os.path.join(arch_lib_path,'include')))
+
+    arch_lib_path = rtems.arch_bsp_lib_path(bld.env.RTEMS_VERSION,
+                                            bld.env.RTEMS_ARCH_BSP)
+    lib_path = os.path.join(bld.env.PREFIX, arch_lib_path)
+    bld.read_stlib('telnetd', paths=[lib_path])
+    bld.read_stlib('rtemstest', paths=[lib_path])
+    bld.read_stlib('ftpd', paths=[lib_path])
+
+    bld.program(features='c',
+                target='telnetd01.exe',
+                source='./rtemslwip/test/telnetd01/init.c',
+                use='telnetd lwip rtemstest ftpd',
+                cflags='-g -Wall -O0',
+                includes=drv_incl + common_includes + './rtemslwip/test/ ' + os.path.relpath(os.path.join(arch_lib_path,'include')))
diff --git a/lwip/src/api/netdb.c b/lwip/src/api/netdb.c
index dfc5203..5217602 100644
--- a/lwip/src/api/netdb.c
+++ b/lwip/src/api/netdb.c
@@ -45,6 +45,7 @@
 #include "lwip/ip_addr.h"
 #include "lwip/api.h"
 #include "lwip/dns.h"
+#include "lwip/sockets.h"
 
 #include <string.h> /* memset */
 #include <stdlib.h> /* atoi */
@@ -431,7 +432,7 @@ getnameinfo(const struct sockaddr *sa, socklen_t salen, char *node,
 
     /* FIXME: This return just the address value. Try resolving instead. */
     if (node != NULL && nodelen > 0) {
-        if (inet_ntop(af, &sa_in->sin_addr, node, nodelen) == NULL) {
+        if (lwip_inet_ntop(af, &sa_in->sin_addr, node, nodelen) == NULL) {
             return EAI_FAIL;
         }
     }   
diff --git a/lwip/src/api/sockets.c b/lwip/src/api/sockets.c
index a331206..f47e68e 100644
--- a/lwip/src/api/sockets.c
+++ b/lwip/src/api/sockets.c
@@ -3274,6 +3274,14 @@ lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t opt
   return err ? -1 : 0;
 }
 
+/*
+int
+setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+    return lwip_setsockopt(s, level, optname, optval, optlen);
+}
+*/
+
 #if !LWIP_TCPIP_CORE_LOCKING
 /** lwip_setsockopt_callback: only used without CORE_LOCKING
  * to get into the tcpip_thread
diff --git a/lwip/src/core/memp.c b/lwip/src/core/memp.c
index 352ce5a..1917826 100644
--- a/lwip/src/core/memp.c
+++ b/lwip/src/core/memp.c
@@ -327,7 +327,7 @@ memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int li
 
 /**
  * Get an element from a specific pool.
- *
+                1 *
  * @param type the pool to get an element from
  *
  * @return a pointer to the allocated memory or a NULL pointer on error
diff --git a/lwip/src/core/tcp.c b/lwip/src/core/tcp.c
index bd7d64e..2996ee7 100644
--- a/lwip/src/core/tcp.c
+++ b/lwip/src/core/tcp.c
@@ -724,12 +724,14 @@ tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
 #endif /* SO_REUSE */
           {
             /* @todo: check accept_any_ip_version */
+#if 0
             if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) &&
                 (ip_addr_isany(&cpcb->local_ip) ||
                  ip_addr_isany(ipaddr) ||
                  ip_addr_cmp(&cpcb->local_ip, ipaddr))) {
               return ERR_USE;
             }
+#endif /* 0 */
           }
         }
       }
diff --git a/lwip/src/include/lwip/opt.h b/lwip/src/include/lwip/opt.h
index 82c420c..b19922f 100644
--- a/lwip/src/include/lwip/opt.h
+++ b/lwip/src/include/lwip/opt.h
@@ -923,6 +923,10 @@
 #define LWIP_DHCP                       0
 #endif /* !LWIP_IPV4 */
 
+#ifndef LWIP_DHCP_TIMEOUT
+#define LWIP_DHCP_TIMEOUT               100
+#endif
+
 /**
  * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
  */
diff --git a/lwip/src/include/lwip/sockets.h b/lwip/src/include/lwip/sockets.h
index d70d36c..2917041 100644
--- a/lwip/src/include/lwip/sockets.h
+++ b/lwip/src/include/lwip/sockets.h
@@ -48,6 +48,7 @@
 #include "lwip/err.h"
 #include "lwip/inet.h"
 #include "lwip/errno.h"
+#include <sys/socket.h>
 
 #include <string.h>
 
@@ -89,6 +90,7 @@ struct sockaddr_in6 {
 };
 #endif /* LWIP_IPV6 */
 
+#ifndef __rtems__
 struct sockaddr {
   u8_t        sa_len;
   sa_family_t sa_family;
@@ -104,6 +106,7 @@ struct sockaddr_storage {
   u32_t       s2_data3[3];
 #endif /* LWIP_IPV6 */
 };
+#endif /* __rtems__ */
 
 /* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED
    to prevent this code from redefining it. */
@@ -124,6 +127,7 @@ struct iovec {
 };
 #endif
 
+#ifndef __rtems__
 struct msghdr {
   void         *msg_name;
   socklen_t     msg_namelen;
@@ -144,6 +148,7 @@ struct cmsghdr {
   int        cmsg_level; /* originating protocol */
   int        cmsg_type;  /* protocol-specific type */
 };
+#endif /* __rtems__ */
 /* Data section follows header and possible padding, typically referred to as
       unsigned char cmsg_data[]; */
 
@@ -155,6 +160,7 @@ will need to increase long long */
 #define ALIGN_H(size) (((size) + sizeof(long) - 1U) & ~(sizeof(long)-1U))
 #define ALIGN_D(size) ALIGN_H(size)
 
+#ifndef __rtems__
 #define CMSG_FIRSTHDR(mhdr) \
           ((mhdr)->msg_controllen >= sizeof(struct cmsghdr) ? \
            (struct cmsghdr *)(mhdr)->msg_control : \
@@ -178,12 +184,14 @@ will need to increase long long */
 #define CMSG_LEN(length) (ALIGN_D(sizeof(struct cmsghdr)) + \
                            length)
 
+#endif /* __rtems__ */
 /* Set socket options argument */
 #define IFNAMSIZ NETIF_NAMESIZE
 struct ifreq {
   char ifr_name[IFNAMSIZ]; /* Interface name */
 };
 
+#ifndef __rtems__
 /* Socket protocol types (TCP/UDP/RAW) */
 #define SOCK_STREAM     1
 #define SOCK_DGRAM      2
@@ -217,9 +225,12 @@ struct ifreq {
 #define SO_ERROR        0x1007 /* get error status and clear */
 #define SO_TYPE         0x1008 /* get socket type */
 #define SO_CONTIMEO     0x1009 /* Unimplemented: connect timeout */
+#endif /* __rtems__ */
 #define SO_NO_CHECK     0x100a /* don't create UDP checksum */
 #define SO_BINDTODEVICE 0x100b /* bind to device */
 
+#ifndef __rtems__
+
 /*
  * Structure used for manipulating linger option.
  */
@@ -244,6 +255,7 @@ struct linger {
 #define PF_INET         AF_INET
 #define PF_INET6        AF_INET6
 #define PF_UNSPEC       AF_UNSPEC
+#endif /* __rtems__ */
 
 #define IPPROTO_IP      0
 #define IPPROTO_ICMP    1
@@ -256,14 +268,17 @@ struct linger {
 #define IPPROTO_UDPLITE 136
 #define IPPROTO_RAW     255
 
+#ifndef __rtems__
 /* Flags we can use with send and recv. */
 #define MSG_PEEK       0x01    /* Peeks at an incoming message */
 #define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
 #define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
 #define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#endif /* __rtems__ */
 #define MSG_MORE       0x10    /* Sender will send more */
+#ifndef __rtems__
 #define MSG_NOSIGNAL   0x20    /* Uninmplemented: Requests not to send the SIGPIPE signal if an attempt to send is made on a stream-oriented socket that is no longer connected. */
-
+#endif /* __rtems__ */
 
 /*
  * Options for level IPPROTO_IP
@@ -400,10 +415,15 @@ typedef struct ipv6_mreq {
  * we restrict parameters to at most 128 bytes.
  */
 #if !defined(FIONREAD) || !defined(FIONBIO)
+#undef IOCPARM_MASK
 #define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#ifndef __rtems__
 #define IOC_VOID        0x20000000UL    /* no parameters */
 #define IOC_OUT         0x40000000UL    /* copy out parameters */
+#endif /* __rtems __ */
+#undef IOC_IN
 #define IOC_IN          0x80000000UL    /* copy in parameters */
+#ifndef __rtems__
 #define IOC_INOUT       (IOC_IN|IOC_OUT)
                                         /* 0x20000000 distinguishes new &
                                            old ioctl's */
@@ -411,6 +431,8 @@ typedef struct ipv6_mreq {
 
 #define _IOR(x,y,t)     ((long)(IOC_OUT|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
 
+#endif /* __rtems__ */
+#undef _IOW
 #define _IOW(x,y,t)     ((long)(IOC_IN|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
 #endif /* !defined(FIONREAD) || !defined(FIONBIO) */
 
@@ -529,6 +551,8 @@ struct timeval {
 void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
 void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
 
+#ifndef __rtems__
+
 #if LWIP_COMPAT_SOCKETS == 2
 /* This helps code parsers/code completion by not having the COMPAT functions as defines */
 #define lwip_accept       accept
@@ -572,6 +596,7 @@ int fcntl(int s, int cmd, ...);
 #define ioctlsocket       ioctl
 #endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
 #endif /* LWIP_COMPAT_SOCKETS == 2 */
+#endif /* __rtems__ */
 
 int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
 int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
@@ -608,6 +633,7 @@ int lwip_fcntl(int s, int cmd, int val);
 const char *lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size);
 int lwip_inet_pton(int af, const char *src, void *dst);
 
+#ifndef __rtems__
 #if LWIP_COMPAT_SOCKETS
 #if LWIP_COMPAT_SOCKETS != 2
 /** @ingroup socket */
@@ -653,7 +679,7 @@ int lwip_inet_pton(int af, const char *src, void *dst);
 #define poll(fds,nfds,timeout)                    lwip_poll(fds,nfds,timeout)
 #endif
 /** @ingroup socket */
-#define ioctlsocket(s,cmd,argp)                   lwip_ioctl(s,cmd,argp)
+//#define ioctlsocket(s,cmd,argp)                   lwip_ioctl(s,cmd,argp)
 /** @ingroup socket */
 #define inet_ntop(af,src,dst,size)                lwip_inet_ntop(af,src,dst,size)
 /** @ingroup socket */
@@ -676,6 +702,7 @@ int lwip_inet_pton(int af, const char *src, void *dst);
 #define ioctl(s,cmd,argp)                         lwip_ioctl(s,cmd,argp)
 #endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
 #endif /* LWIP_COMPAT_SOCKETS != 2 */
+#endif
 
 #endif /* LWIP_COMPAT_SOCKETS */
 
diff --git a/rtemslwip/beaglebone/lwipopts.h b/rtemslwip/beaglebone/lwipopts.h
new file mode 100644
index 0000000..888fae4
--- /dev/null
+++ b/rtemslwip/beaglebone/lwipopts.h
@@ -0,0 +1,276 @@
+#if 0
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_LWIPOPTS_H__
+#define LWIP_HDR_LWIPOPTS_H__
+
+/* Prevent having to link sys_arch.c (we don't test the API layers in unit tests) */
+#define NO_SYS                          0
+#define LWIP_NETCONN                    1
+#define LWIP_SOCKET                     1
+#define LWIP_DNS                        1
+
+#define LWIP_IPV6                       1
+#define LWIP_IPV4                       1
+
+#define LWIP_ETHERNET                   1
+#define LWIP_NETIF_API                  1
+#define LWIP_AUTOIP                     1
+/* Enable DHCP to test it, disable UDP checksum to easier inject packets */
+#define LWIP_DHCP                       1
+#define LWIP_TIMEVAL_PRIVATE            0
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+//#define LWIP_COMPAT_SOCKETS             2
+#ifndef FIONREAD
+#define FIONREAD                        1
+#endif
+#ifndef FIONBIO
+#define FIONBIO                         1
+#endif
+#define THREAD_STACK_SIZE               4096
+
+#define LWIP_TIMERS                     1
+/* Minimal changes to opt.h required for tcp unit tests: */
+
+#define MEM_SIZE                        16000
+#define TCP_SND_QUEUELEN                40
+#define MEMP_NUM_TCP_SEG                TCP_SND_QUEUELEN
+#define TCP_SND_BUF                     (12 * TCP_MSS)
+#define TCP_WND                         (10 * TCP_MSS)
+#define LWIP_WND_SCALE                  1
+#define TCP_RCV_SCALE                   0
+#define PBUF_POOL_SIZE                  400 // pbuf tests need ~200KByte
+
+/* Minimal changes to opt.h required for etharp unit tests: */
+#define ETHARP_SUPPORT_STATIC_ENTRIES   1
+
+#endif /* LWIP_HDR_LWIPOPTS_H__ */
+
+#endif /* 0 */
+
+/**
+ * \file lwipopts.h - Configuration options for lwIP
+ *
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/*****************************************************************************
+**                           CONFIGURATIONS
+*****************************************************************************/
+
+/*
+** The macro CPSW_DUAL_MAC_MODE shall be defined for using CPSW ports in
+** Dual MAC mode.
+*/
+#define CPSW_DUAL_MAC_MODE
+
+/*
+** The below macro should be defined for using lwIP with cache. For cache
+** enabling, pbuf pool shall be cache line aligned. This is done by using
+** separate pool for each memory. The alignment of pbuf pool to cache line
+** size is done in /ports/cpsw/include/arch/cc.h.
+*/
+/*#define LWIP_CACHE_ENABLED*/
+
+#define SOC_CACHELINE_SIZE_BYTES        64            /* Number of bytes in
+                                                         a cache line */
+/*
+** The timeout for DHCP completion. lwIP library will wait for DHCP
+** completion for (LWIP_DHCP_TIMEOUT / 100) seconds.
+*/
+#define LWIP_DHCP_TIMEOUT               1000
+
+/*
+** The number of times DHCP is attempted. Each time, the library will wait
+** for (LWIP_DHCP_TIMEOUT / 100) seconds for DHCP completion.
+*/
+#define NUM_DHCP_TRIES                  5
+
+#define LWIP_ETHERNET 1
+#define LWIP_ARP 1
+#define LWIP_DNS 1
+
+/*****************************************************************************
+**            lwIP SPECIFIC DEFINITIONS - To be used by lwIP stack
+*****************************************************************************/
+#define HOST_TMR_INTERVAL               0
+#define DYNAMIC_HTTP_HEADERS
+
+/*****************************************************************************
+**                    Platform specific locking
+*****************************************************************************/
+#define SYS_LIGHTWEIGHT_PROT            1
+#define NO_SYS                          0
+#define NO_SYS_NO_TIMERS                0
+
+/*****************************************************************************
+**                          Memory Options
+*****************************************************************************/
+#define MEM_ALIGNMENT                   4
+#define MEM_SIZE                        (1024 * 1024) /* 4K */
+
+#define MEMP_NUM_PBUF                   96
+#define MEMP_NUM_TCP_PCB                32
+#define MEMP_NUM_TCP_SEG                32
+#define PBUF_POOL_SIZE                  512
+#define MEMP_MEM_MALLOC                 1
+#define MEMP_MEM_INIT                   1
+#define MEMP_OVERFLOW_CHECK             0
+
+#ifdef LWIP_CACHE_ENABLED
+#define MEMP_SEPARATE_POOLS             1            /* We want the pbuf
+                                                        pool cache line
+                                                        aligned*/
+#endif
+
+//#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)
+
+/*****************************************************************************
+**                           IP Options
+*****************************************************************************/
+#define IP_REASSEMBLY                   0
+#define IP_FRAG                         0
+#define LWIP_IPV4                       1
+#define LWIP_IPV6                       1
+
+/*****************************************************************************
+**                           DHCP Options
+*****************************************************************************/
+#define LWIP_DHCP                       1
+#define DHCP_DOES_ARP_CHECK             0
+
+/*****************************************************************************
+**                           Auto IP  Options
+*****************************************************************************/
+#define LWIP_AUTOIP                     1
+#define LWIP_DHCP_AUTOIP_COOP           ((LWIP_DHCP) && (LWIP_AUTOIP))
+
+/*****************************************************************************
+**                           TCP  Options
+*****************************************************************************/
+#define TCP_MSS                         1500
+#define TCP_WND                         (8 * TCP_MSS)
+#define TCP_SND_BUF                     (8 * TCP_MSS)
+#define TCP_OVERSIZE                    TCP_MSS
+#define LWIP_TCPIP_CORE_LOCKING         1
+
+/*****************************************************************************
+**                           PBUF  Options
+*****************************************************************************/
+#define PBUF_LINK_HLEN                  14
+#define PBUF_POOL_BUFSIZE               1520         /* + size of struct pbuf
+                                                        shall be cache line
+                                                        aligned be enabled */
+#define ETH_PAD_SIZE                    0
+#define LWIP_NETCONN                    1
+
+/*****************************************************************************
+**                           Socket  Options
+*****************************************************************************/
+#define LWIP_SOCKET                     1
+#define SO_REUSE                        1
+
+/*****************************************************************************
+**                          Debugging options
+*****************************************************************************/
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_OFF
+#define LWIP_DBG_TYPES_ON               (LWIP_DBG_ON | LWIP_DBG_TRACE \
+                                         |LWIP_DBG_STATE | LWIP_DBG_FRESH)
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#define IP_DEBUG			LWIP_DBG_OFF
+#define UDP_DEBUG			LWIP_DBG_OFF
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#define PBUF_DEBUG			LWIP_DBG_OFF
+#define TCPIP_DEBUG			LWIP_DBG_OFF
+#define APP_DEBUG			LWIP_DBG_OFF
+#define SOCKETS_DEBUG		LWIP_DBG_OFF
+#define LWIP_STATS                      0
+#define LWIP_STATS_DISPLAY              0
+#define LWIP_STATS_POSIX                0
+#define LWIP_DNS_API_DEFINE_ERRORS      1
+
+
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#define LWIP_COMPAT_SOCKETS            1
+
+ #define LWIP_TIMEVAL_PRIVATE 0
+
+ #define LWIP_RAW                        0
+
+#define tskIDLE_PRIORITY RTEMS_MAXIMUM_PRIORITY
+#define portTICK_RATE_MS (rtems_clock_get_ticks_per_second() * 1000)
+#define vTaskDelay(x) sys_arch_delay(x)
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/rtemslwip/common/rtems_lwip_io.c b/rtemslwip/common/rtems_lwip_io.c
new file mode 100644
index 0000000..8aa28b5
--- /dev/null
+++ b/rtemslwip/common/rtems_lwip_io.c
@@ -0,0 +1,1323 @@
+/*
+ *
+ * RTEMS Project (https://www.rtems.org/)
+ *
+ * Copyright (c) 2021 Vijay Kumar Banerjee <vijay@rtems.org>.
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#define LWIP_COMPAT_SOCKETS 0
+
+#include <string.h>
+#include <stdarg.h>
+/* #include <stdlib.h> */
+#include <stdio.h>
+#include <errno.h>
+
+#include <rtems.h>
+#include <rtems/libio_.h>
+#include <rtems/error.h>
+
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/fcntl.h>
+#include <sys/filio.h>
+#include <sys/sysctl.h>
+
+#include <rtems/thread.h>
+
+#include <lwip/tcpip.h>
+#include <lwip/api.h>
+#include <lwip/netbuf.h>
+#include <lwip/netdb.h>
+#include <lwip/netifapi.h>
+#include <lwip/sockets.h>
+#include <lwip/sys.h>
+#include <sys/errno.h>
+
+#include <lwip/init.h>
+#include "lwip/err.h"
+#include "lwip/tcp.h"
+#include <netif/etharp.h>
+
+#include <string.h>
+
+#include "lwip/tcpip.h"
+//#include "arch/eth_lwip.h"
+#include "lwip/api.h"
+#include "lwip/netbuf.h"
+#include "lwip/netdb.h"
+#include "lwip/netifapi.h"
+#include "lwip/sockets.h"
+#include "lwip/sys.h"
+
+#include "rtems_lwip_int.h"
+
+static const rtems_filesystem_file_handlers_r rtems_lwip_socket_handlers;
+
+static rtems_recursive_mutex rtems_lwip_mutex =
+  RTEMS_RECURSIVE_MUTEX_INITIALIZER( "_LWIP" );
+
+void rtems_lwip_semaphore_obtain( void )
+{
+    rtems_recursive_mutex_lock( &rtems_lwip_mutex );
+}
+
+/*
+ * Release network mutex
+ */
+void rtems_lwip_semaphore_release( void )
+{
+    rtems_recursive_mutex_unlock( &rtems_lwip_mutex );
+}
+
+static inline int rtems_lwip_iop_to_lwipfd( rtems_libio_t *iop )
+{
+  if ( iop == NULL ) {
+    errno = EBADF;
+
+    return -1;
+  }
+
+/*
+   if ((rtems_libio_iop_flags(iop) & LIBIO_FLAGS_OPEN) == 0) {
+    errno = EBADF;
+    return -1;
+   }
+ */
+
+  if ( iop->pathinfo.handlers != &rtems_lwip_socket_handlers ) {
+    errno = ENOTSOCK;
+
+    return -1;
+  }
+
+  return iop->data0;
+}
+
+/*
+ * Convert an RTEMS file descriptor to a LWIP socket pointer.
+ */
+int rtems_lwip_sysfd_to_lwipfd( int fd )
+{
+  if ( (uint32_t) fd >= rtems_libio_number_iops ) {
+    errno = EBADF;
+
+    return -1;
+  }
+
+  return rtems_lwip_iop_to_lwipfd( rtems_libio_iop( fd ) );
+}
+
+/*
+ * Create an RTEMS file descriptor for a socket
+ */
+static int rtems_lwip_make_sysfd_from_lwipfd( int lfwipfd )
+{
+  rtems_libio_t *iop;
+  int            fd;
+
+  iop = rtems_libio_allocate();
+
+  if ( iop == 0 )
+    rtems_set_errno_and_return_minus_one( ENFILE );
+
+  fd = rtems_libio_iop_to_descriptor( iop );
+  iop->data0 = lfwipfd;
+  iop->data1 = NULL;
+  iop->pathinfo.handlers = &rtems_lwip_socket_handlers;
+  iop->pathinfo.mt_entry = &rtems_filesystem_null_mt_entry;
+  rtems_filesystem_location_add_to_mt_entry( &iop->pathinfo );
+  rtems_libio_iop_flags_set( iop, LIBIO_FLAGS_READ_WRITE | LIBIO_FLAGS_OPEN );
+
+  return fd;
+}
+
+/*
+ *********************************************************************
+ *                       BSD-style entry points                      *
+ *********************************************************************
+ */
+int socket(
+  int domain,
+  int type,
+  int protocol
+)
+{
+  int fd;
+  int lwipfd;
+
+  if ( domain == rtems_lwip_sysdefs_PF_UNSPEC ) {
+    domain = PF_UNSPEC;
+  } else if ( domain == rtems_lwip_sysdefs_PF_INET ) {
+    domain = PF_INET;
+  } else if ( domain == rtems_lwip_sysdefs_PF_INET6 ) {
+    domain = PF_INET6;
+  } else {
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  if ( type == rtems_lwip_sysdefs_SOCK_STREAM ) {
+    type = SOCK_STREAM;
+  } else if ( type == rtems_lwip_sysdefs_SOCK_DGRAM ) {
+    type = SOCK_DGRAM;
+  } else {
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+
+  lwipfd = lwip_socket( domain, type, 0 );
+
+  if ( lwipfd < 0 ) {
+    fd = -1;
+  } else {
+    fd = rtems_lwip_make_sysfd_from_lwipfd( lwipfd );
+
+    if ( fd < 0 ) {
+      lwip_close( lwipfd );
+    }
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return fd;
+}
+
+int bind(
+  int                    s,
+  const struct sockaddr *name,
+  socklen_t              namelen
+)
+{
+  int                ret = -1;
+  int                lwipfd;
+  int                family;
+  struct sockaddr   *lwipname;
+  socklen_t          lwipnamelen;
+  struct sockaddr_in so_in;
+
+ #if LWIP_IPV6
+  struct sockaddr_in6 so_in6;
+ #endif
+
+  family = rtems_lwip_sysdefs_sockaddr_get_family( name );
+
+  if ( ( family == rtems_lwip_sysdefs_AF_INET ) &&
+       ( namelen >= rtems_lwip_sysdefs_sockaddr_in_size ) ) {
+    so_in.sin_len = sizeof( so_in );
+    so_in.sin_family = PF_INET;
+    so_in.sin_port = rtems_lwip_sysdefs_sockaddr_in_get_sin_port( name );
+    so_in.sin_addr.s_addr =
+      rtems_lwip_sysdefs_sockaddr_in_get_sin_addr( name );
+    lwipname = (struct sockaddr *) &so_in;
+    lwipnamelen = so_in.sin_len;
+ #if LWIP_IPV6
+  } else if ( ( family == rtems_lwip_sysdefs_AF_INET6 ) &&
+              ( namelen >= rtems_lwip_sysdefs_sockaddr_in6_size ) ) {
+    so_in6.sin6_len = sizeof( so_in6 );
+    so_in6.sin6_family = PF_INET6;
+    so_in6.sin6_port = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_port( name );
+    memcpy( &so_in6.sin6_addr,
+      rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr_const( name ),
+      sizeof( so_in6.sin6_addr ) );
+    so_in6.sin6_flowinfo = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_flowinfo(
+      name );
+    so_in6.sin6_scope_id = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_scope_id(
+      name );
+    lwipname = (struct sockaddr *) &so_in6;
+    lwipnamelen = so_in6.sin6_len;
+ #endif
+  } else {
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    ret = lwip_bind( lwipfd, lwipname, lwipnamelen );
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+int connect(
+  int                    s,
+  const struct sockaddr *name,
+  socklen_t              namelen
+)
+{
+  int                ret = -1;
+  int                lwipfd;
+  int                family;
+  struct sockaddr   *lwipname;
+  socklen_t          lwipnamelen;
+  struct sockaddr_in so_in;
+
+ #if LWIP_IPV6
+  struct sockaddr_in6 so_in6;
+ #endif
+
+  family = rtems_lwip_sysdefs_sockaddr_get_family( name );
+
+  if ( ( family == rtems_lwip_sysdefs_AF_INET ) &&
+       ( namelen >= rtems_lwip_sysdefs_sockaddr_in_size ) ) {
+    so_in.sin_len = sizeof( so_in );
+    so_in.sin_family = AF_INET;
+    so_in.sin_port = rtems_lwip_sysdefs_sockaddr_in_get_sin_port( name );
+    so_in.sin_addr.s_addr =
+      rtems_lwip_sysdefs_sockaddr_in_get_sin_addr( name );
+    lwipname = (struct sockaddr *) &so_in;
+    lwipnamelen = so_in.sin_len;
+ #if LWIP_IPV6
+  } else if ( ( family == rtems_lwip_sysdefs_AF_INET6 ) &&
+              ( namelen >= rtems_lwip_sysdefs_sockaddr_in6_size ) ) {
+    so_in6.sin6_len = sizeof( so_in6 );
+    so_in6.sin6_family = AF_INET6;
+    so_in6.sin6_port = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_port( name );
+    memcpy( &so_in6.sin6_addr,
+      rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr_const( name ),
+      sizeof( so_in6.sin6_addr ) );
+    so_in6.sin6_flowinfo = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_flowinfo(
+      name );
+    so_in6.sin6_scope_id = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_scope_id(
+      name );
+    lwipname = (struct sockaddr *) &so_in6;
+    lwipnamelen = so_in6.sin6_len;
+ #endif
+  } else {
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    ret = lwip_connect( lwipfd, lwipname, lwipnamelen );
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+int listen(
+  int s,
+  int backlog
+)
+{
+  int ret = -1;
+  int lwipfd;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    ret = lwip_listen( lwipfd, backlog );
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+int accept(
+  int              s,
+  struct sockaddr *name,
+  socklen_t       *namelen
+)
+{
+  int                ret = -1;
+  int                lwipfd;
+  struct sockaddr   *lwipname = name;
+  socklen_t          lwipnamelen = *namelen;
+  struct sockaddr_in so_in;
+
+ #if LWIP_IPV6
+  struct sockaddr_in6 so_in6;
+ #endif
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+
+    rtems_lwip_semaphore_release();
+    lwipfd = lwip_accept( lwipfd, lwipname, &lwipnamelen );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  if ( lwipfd < 0 )
+    return lwipfd;
+
+  if ( lwipname->sa_family == AF_INET ) {
+    memcpy( &so_in, lwipname, sizeof( so_in ) );
+    rtems_lwip_sysdefs_sockaddr_set_len( name,
+      rtems_lwip_sysdefs_sockaddr_in_size );
+    rtems_lwip_sysdefs_sockaddr_set_family( name, rtems_lwip_sysdefs_AF_INET );
+    rtems_lwip_sysdefs_sockaddr_in_set_sin_port( name, so_in.sin_port );
+    rtems_lwip_sysdefs_sockaddr_in_set_sin_addr( name, so_in.sin_addr.s_addr );
+ #if LWIP_IPV6
+  } else if ( lwipname->sa_family == AF_INET6 ) {
+    memcpy( &so_in6, lwipname, sizeof( so_in6 ) );
+    rtems_lwip_sysdefs_sockaddr_set_len( name,
+      rtems_lwip_sysdefs_sockaddr_in6_size );
+    rtems_lwip_sysdefs_sockaddr_set_family( name,
+      rtems_lwip_sysdefs_AF_INET6 );
+
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_port( name, so_in6.sin6_port );
+    memcpy( rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr( name ),
+      &so_in6.sin6_addr,
+      sizeof( so_in6.sin6_addr ) );
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_flowinfo( name,
+      so_in6.sin6_flowinfo );
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_scope_id( name,
+      so_in6.sin6_scope_id );
+ #endif
+  } else {
+    lwip_close( lwipfd );
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+  ret = rtems_lwip_make_sysfd_from_lwipfd( lwipfd );
+
+  if ( ret < 0 ) {
+    rtems_lwip_semaphore_release();
+    lwip_close( lwipfd );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  *namelen = rtems_lwip_sysdefs_sockaddr_get_len( name );
+
+  return ret;
+}
+
+/*
+ *  Shutdown routine
+ */
+
+int shutdown(
+  int s,
+  int how
+)
+{
+  int ret = -1;
+  int lwipfd;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    rtems_lwip_semaphore_release();
+    ret = lwip_shutdown( lwipfd, how );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+ssize_t recv(
+  int    s,
+  void  *buf,
+  size_t len,
+  int    flags
+)
+{
+  int ret = -1;
+  int lwipfd;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    rtems_lwip_semaphore_release();
+    ret = lwip_recv( lwipfd, buf, len, flags );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+ssize_t send(
+  int         s,
+  const void *buf,
+  size_t      len,
+  int         flags
+)
+{
+  int ret = -1;
+  int lwipfd;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    rtems_lwip_semaphore_release();
+    ret = lwip_send( lwipfd, buf, len, flags );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+ssize_t recvfrom(
+  int              s,
+  void            *buf,
+  size_t           len,
+  int              flags,
+  struct sockaddr *name,
+  socklen_t       *namelen
+)
+{
+  int                ret = -1;
+  int                lwipfd;
+  struct sockaddr   *lwipname = name;
+  socklen_t          lwipnamelen = *namelen;
+  struct sockaddr_in so_in;
+
+ #if LWIP_IPV6
+  struct sockaddr_in6 so_in6;
+ #endif
+
+  if ( name == NULL )
+    return recv( s, buf, len, flags );
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    rtems_lwip_semaphore_release();
+    lwipfd = lwip_recvfrom( lwipfd, buf, len, flags, lwipname, &lwipnamelen );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  if ( lwipfd < 0 )
+    return lwipfd;
+
+  if ( lwipname->sa_family == AF_INET ) {
+    memcpy( &so_in, lwipname, sizeof( so_in ) );
+    rtems_lwip_sysdefs_sockaddr_set_len( name,
+      rtems_lwip_sysdefs_sockaddr_in_size );
+    rtems_lwip_sysdefs_sockaddr_set_family( name, rtems_lwip_sysdefs_AF_INET );
+    rtems_lwip_sysdefs_sockaddr_in_set_sin_port( name, so_in.sin_port );
+    rtems_lwip_sysdefs_sockaddr_in_set_sin_addr( name, so_in.sin_addr.s_addr );
+ #if LWIP_IPV6
+  } else if ( lwipname->sa_family == AF_INET6 ) {
+    memcpy( &so_in6, lwipname, sizeof( so_in6 ) );
+    rtems_lwip_sysdefs_sockaddr_set_len( name,
+      rtems_lwip_sysdefs_sockaddr_in6_size );
+    rtems_lwip_sysdefs_sockaddr_set_family( name,
+      rtems_lwip_sysdefs_AF_INET6 );
+
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_port( name, so_in6.sin6_port );
+    memcpy( rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr( name ),
+      &so_in6.sin6_addr,
+      sizeof( so_in6.sin6_addr ) );
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_flowinfo( name,
+      so_in6.sin6_flowinfo );
+    rtems_lwip_sysdefs_sockaddr_in6_set_sin6_scope_id( name,
+      so_in6.sin6_scope_id );
+ #endif
+  } else {
+    lwip_close( lwipfd );
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+  ret = rtems_lwip_make_sysfd_from_lwipfd( lwipfd );
+
+  if ( ret < 0 ) {
+    lwip_close( lwipfd );
+  }
+
+  rtems_lwip_semaphore_release();
+
+  *namelen = rtems_lwip_sysdefs_sockaddr_get_len( name );
+
+  return ret;
+}
+
+ssize_t sendto(
+  int                    s,
+  const void            *buf,
+  size_t                 len,
+  int                    flags,
+  const struct sockaddr *name,
+  socklen_t              namelen
+)
+{
+  int                ret = -1;
+  int                lwipfd;
+  int                family;
+  struct sockaddr   *lwipname;
+  socklen_t          lwipnamelen;
+  struct sockaddr_in so_in;
+
+ #if LWIP_IPV6
+  struct sockaddr_in6 so_in6;
+ #endif
+
+  if ( name == NULL )
+    return send( s, buf, len, flags );
+
+  family = rtems_lwip_sysdefs_sockaddr_get_family( name );
+
+  if ( ( family == rtems_lwip_sysdefs_AF_INET ) &&
+       ( namelen >= rtems_lwip_sysdefs_sockaddr_in_size ) ) {
+    so_in.sin_len = sizeof( so_in );
+    so_in.sin_family = AF_INET;
+    so_in.sin_port = rtems_lwip_sysdefs_sockaddr_in_get_sin_port( name );
+    so_in.sin_addr.s_addr =
+      rtems_lwip_sysdefs_sockaddr_in_get_sin_addr( name );
+    lwipname = (struct sockaddr *) &so_in;
+    lwipnamelen = so_in.sin_len;
+ #if LWIP_IPV6
+  } else if ( ( family == rtems_lwip_sysdefs_AF_INET6 ) &&
+              ( namelen >= rtems_lwip_sysdefs_sockaddr_in6_size ) ) {
+    so_in6.sin6_len = sizeof( so_in6 );
+    so_in6.sin6_family = AF_INET6;
+    so_in6.sin6_port = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_port( name );
+    memcpy( &so_in6.sin6_addr,
+      rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr_const( name ),
+      sizeof( so_in6.sin6_addr ) );
+    so_in6.sin6_flowinfo = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_flowinfo(
+      name );
+    so_in6.sin6_scope_id = rtems_lwip_sysdefs_sockaddr_in6_get_sin6_scope_id(
+      name );
+    lwipname = (struct sockaddr *) &so_in6;
+    lwipnamelen = so_in6.sin6_len;
+ #endif
+  } else {
+    errno = EINVAL;
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) >= 0 ) {
+    rtems_lwip_semaphore_release();
+    ret = lwip_sendto( lwipfd, buf, len, flags, lwipname, lwipnamelen );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+#if 0
+
+/*
+ * All `transmit' operations end up calling this routine.
+ */
+ssize_t sendmsg(
+  int                  s,
+  const struct msghdr *mp,
+  int                  flags
+)
+{
+  int           ret = -1;
+  int           error;
+  struct uio    auio;
+  struct iovec *iov;
+  int           lwipfd;
+  struct mbuf  *to;
+  struct mbuf  *control = NULL;
+  int           i;
+  int           len;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = rtems_lwip_sysfd_to_lwipfd( s ) ) == NULL ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  auio.uio_iov = mp->msg_iov;
+  auio.uio_iovcnt = mp->msg_iovlen;
+  auio.uio_segflg = UIO_USERSPACE;
+  auio.uio_rw = UIO_WRITE;
+  auio.uio_offset = 0;
+  auio.uio_resid = 0;
+  iov = mp->msg_iov;
+
+  for ( i = 0; i < mp->msg_iovlen; i++, iov++ ) {
+    if ( ( auio.uio_resid += iov->iov_len ) < 0 ) {
+      errno = EINVAL;
+      rtems_lwip_semaphore_release();
+
+      return -1;
+    }
+  }
+
+  if ( mp->msg_name ) {
+    error = sockargstombuf( &to, mp->msg_name, mp->msg_namelen, MT_SONAME );
+
+    if ( error ) {
+      errno = error;
+      rtems_lwip_semaphore_release();
+
+      return -1;
+    }
+  } else {
+    to = NULL;
+  }
+
+  if ( mp->msg_control ) {
+    if ( mp->msg_controllen < sizeof( struct cmsghdr ) ) {
+      errno = EINVAL;
+
+      if ( to )
+        m_freem( to );
+
+      rtems_lwip_semaphore_release();
+
+      return -1;
+    }
+
+    sockargstombuf( &control, mp->msg_control, mp->msg_controllen,
+      MT_CONTROL );
+  } else {
+    control = NULL;
+  }
+
+  len = auio.uio_resid;
+  error = sosend( so, to, &auio, (struct mbuf *) 0, control, flags );
+
+  if ( error ) {
+    if ( auio.uio_resid != len && ( error == EINTR || error == EWOULDBLOCK ) )
+      error = 0;
+  }
+
+  if ( error )
+    errno = error;
+  else
+    ret = len - auio.uio_resid;
+
+  if ( to )
+    m_freem( to );
+
+  rtems_lwip_semaphore_release();
+
+  return ( ret );
+}
+
+/*
+ * All `receive' operations end up calling this routine.
+ */
+ssize_t recvmsg(
+  int            s,
+  struct msghdr *mp,
+  int            flags
+)
+{
+  int           ret = -1;
+  int           error;
+  struct uio    auio;
+  struct iovec *iov;
+  int           lwipfd;
+  struct mbuf  *from = NULL, *control = NULL;
+  int           i;
+  int           len;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = rtems_lwip_sysfd_to_lwipfd( s ) ) == NULL ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  auio.uio_iov = mp->msg_iov;
+  auio.uio_iovcnt = mp->msg_iovlen;
+  auio.uio_segflg = UIO_USERSPACE;
+  auio.uio_rw = UIO_READ;
+  auio.uio_offset = 0;
+  auio.uio_resid = 0;
+  iov = mp->msg_iov;
+
+  for ( i = 0; i < mp->msg_iovlen; i++, iov++ ) {
+    if ( ( auio.uio_resid += iov->iov_len ) < 0 ) {
+      errno = EINVAL;
+      rtems_lwip_semaphore_release();
+
+      return -1;
+    }
+  }
+
+  len = auio.uio_resid;
+  mp->msg_flags = flags;
+  error = soreceive( so, &from, &auio, (struct mbuf **) NULL,
+    mp->msg_control ? &control : (struct mbuf **) NULL,
+    &mp->msg_flags );
+
+  if ( error ) {
+    if ( auio.uio_resid != len && ( error == EINTR || error == EWOULDBLOCK ) )
+      error = 0;
+  }
+
+  if ( error ) {
+    errno = error;
+  } else {
+    ret = len - auio.uio_resid;
+
+    if ( mp->msg_name ) {
+      len = mp->msg_namelen;
+
+      if ( ( len <= 0 ) || ( from == NULL ) ) {
+        len = 0;
+      } else {
+        if ( len > from->m_len )
+          len = from->m_len;
+
+        memcpy( mp->msg_name, mtod( from, caddr_t ), len );
+      }
+
+      mp->msg_namelen = len;
+    }
+
+    if ( mp->msg_control ) {
+      struct mbuf *m;
+      void        *ctlbuf;
+
+      len = mp->msg_controllen;
+      m = control;
+      mp->msg_controllen = 0;
+      ctlbuf = mp->msg_control;
+
+      while ( m && ( len > 0 ) ) {
+        unsigned int tocopy;
+
+        if ( len >= m->m_len )
+          tocopy = m->m_len;
+        else {
+          mp->msg_flags |= MSG_CTRUNC;
+          tocopy = len;
+        }
+
+        memcpy( ctlbuf, mtod( m, caddr_t ), tocopy );
+        ctlbuf += tocopy;
+        len -= tocopy;
+        m = m->m_next;
+      }
+
+      mp->msg_controllen = ctlbuf - mp->msg_control;
+    }
+  }
+
+  if ( from )
+    m_freem( from );
+
+  if ( control )
+    m_freem( control );
+
+  rtems_lwip_semaphore_release();
+
+  return ( ret );
+}
+
+#endif
+
+int setsockopt(
+  int         s,
+  int         level,
+  int         name,
+  const void *val,
+  socklen_t   len
+)
+{
+
+#if 0
+  int          lwipfd;
+  struct mbuf *m = NULL;
+  int          error;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = rtems_lwip_sysfd_to_lwipfd( s ) ) == NULL ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  if ( len > MLEN ) {
+    errno = EINVAL;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  if ( val ) {
+    error = sockargstombuf( &m, val, len, MT_SOOPTS );
+
+    if ( error ) {
+      errno = error;
+      rtems_lwip_semaphore_release();
+
+      return -1;
+    }
+  }
+
+  error = sosetopt( so, level, name, m );
+
+  if ( error ) {
+    errno = error;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_release();
+#endif
+  return 0;
+}
+
+#if 0
+
+int getsockopt(
+  int        s,
+  int        level,
+  int        name,
+  void      *aval,
+  socklen_t *avalsize
+)
+{
+  int          lwipfd;
+  struct mbuf *m = NULL, *m0;
+  char        *val = aval;
+  int          i, op, valsize;
+  int          error;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = rtems_lwip_sysfd_to_lwipfd( s ) ) == NULL ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  if ( val )
+    valsize = *avalsize;
+  else
+    valsize = 0;
+
+  if ( ( ( error =
+             sogetopt( so, level, name,
+               &m ) ) == 0 ) && val && valsize && m ) {
+    op = 0;
+
+    while ( m && op < valsize ) {
+      i = valsize - op;
+
+      if ( i > m->m_len )
+        i = m->m_len;
+
+      memcpy( val, mtod( m, caddr_t ), i );
+      op += i;
+      val += i;
+      m0 = m;
+      MFREE( m0, m );
+    }
+
+    *avalsize = op;
+  }
+
+  if ( m != NULL )
+    (void) m_free( m );
+
+  if ( error ) {
+    errno = error;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return 0;
+}
+
+static int getpeersockname(
+  int              s,
+  struct sockaddr *name,
+  socklen_t       *namelen,
+  int              pflag
+)
+{
+  int          lwipfd;
+  struct mbuf *m;
+  int          len = *namelen;
+  int          error;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = rtems_lwip_sysfd_to_lwipfd( s ) ) == NULL ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  m = m_getclr( M_WAIT, MT_SONAME );
+
+  if ( m == NULL ) {
+    errno = ENOBUFS;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  if ( pflag )
+    error = ( *so->so_proto->pr_usrreqs->pru_peeraddr )( so, m );
+  else
+    error = ( *so->so_proto->pr_usrreqs->pru_sockaddr )( so, m );
+
+  if ( error ) {
+    m_freem( m );
+    errno = error;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  if ( len > m->m_len ) {
+    len = m->m_len;
+    *namelen = len;
+  }
+
+  memcpy( name, mtod( m, caddr_t ), len );
+  m_freem( m );
+  rtems_lwip_semaphore_release();
+
+  return 0;
+}
+
+#endif
+
+int getpeername(
+  int              s,
+  struct sockaddr *name,
+  socklen_t       *namelen
+)
+{
+  int          lwipfd;
+  int          error;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( lwipfd = rtems_lwip_sysfd_to_lwipfd( s ) ) < 0 ) {
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  error = lwip_getpeername(lwipfd, name, namelen);
+
+  rtems_lwip_semaphore_release();
+
+  return error;
+}
+
+#if 0
+
+int getsockname(
+  int              s,
+  struct sockaddr *name,
+  socklen_t       *namelen
+)
+{
+  return getpeersockname( s, name, namelen, 0 );
+}
+
+int sysctl(
+  const int  *name,
+  u_int       namelen,
+  void       *oldp,
+  size_t     *oldlenp,
+  const void *newp,
+  size_t      newlen
+)
+{
+  int    error;
+  size_t j;
+
+  rtems_lwip_semaphore_obtain();
+  error =
+    userland_sysctl( 0, name, namelen, oldp, oldlenp, 1, newp, newlen, &j );
+  rtems_lwip_semaphore_release();
+
+  if ( oldlenp )
+    *oldlenp = j;
+
+  if ( error ) {
+    errno = error;
+
+    return -1;
+  }
+
+  return 0;
+}
+
+#endif
+
+/*
+ ************************************************************************
+ *                      RTEMS I/O HANDLER ROUTINES                      *
+ ************************************************************************
+ */
+static int rtems_lwip_close( rtems_libio_t *iop )
+{
+  int lwipfd;
+  int ret;
+
+  rtems_lwip_semaphore_obtain();
+  lwipfd = rtems_lwip_iop_to_lwipfd( iop );
+
+  if ( lwipfd < 0 ) {
+    ret = -1;
+  } else {
+    rtems_lwip_semaphore_release();
+    ret = lwip_close( lwipfd );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+static ssize_t rtems_lwip_read(
+  rtems_libio_t *iop,
+  void          *buffer,
+  size_t         count
+)
+{
+  int lwipfd;
+  int ret;
+
+  rtems_lwip_semaphore_obtain();
+  lwipfd = rtems_lwip_iop_to_lwipfd( iop );
+
+  if ( lwipfd < 0 ) {
+    ret = -1;
+  } else {
+    rtems_lwip_semaphore_release();
+    ret = lwip_read( lwipfd, buffer, count );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+static ssize_t rtems_lwip_write(
+  rtems_libio_t *iop,
+  const void    *buffer,
+  size_t         count
+)
+{
+  int lwipfd;
+  int ret;
+
+  rtems_lwip_semaphore_obtain();
+  lwipfd = rtems_lwip_iop_to_lwipfd( iop );
+
+  if ( lwipfd < 0 ) {
+    ret = -1;
+  } else {
+    rtems_lwip_semaphore_release();
+    ret = lwip_write( lwipfd, buffer, count );
+    rtems_lwip_semaphore_obtain();
+  }
+
+  rtems_lwip_semaphore_release();
+
+  return ret;
+}
+
+int so_ioctl(
+  rtems_libio_t *iop,
+  int            lwipfd,
+  uint32_t       command,
+  void          *buffer
+)
+{
+#if 0
+
+  switch ( command ) {
+    case FIONBIO:
+
+      if ( *(int *) buffer ) {
+        iop->flags |= O_NONBLOCK;
+        so->so_state |= SS_NBIO;
+      } else {
+        iop->flags &= ~O_NONBLOCK;
+        so->so_state &= ~SS_NBIO;
+      }
+
+      return 0;
+
+    case FIONREAD:
+      *(int *) buffer = so->so_rcv.sb_cc;
+
+      return 0;
+  }
+
+  if ( IOCGROUP( command ) == 'i' )
+    return ifioctl( so, command, buffer, NULL );
+
+  if ( IOCGROUP( command ) == 'r' )
+    return rtioctl( command, buffer, NULL );
+
+  return ( *so->so_proto->pr_usrreqs->pru_control )( so, command, buffer, 0 );
+#endif
+
+  return -1;
+}
+
+static int rtems_lwip_ioctl(
+  rtems_libio_t  *iop,
+  ioctl_command_t command,
+  void           *buffer
+)
+{
+#if 0
+  int lwipfd;
+  int error;
+
+  rtems_lwip_semaphore_obtain();
+
+  if ( ( so = iop->data1 ) == NULL ) {
+    errno = EBADF;
+    rtems_lwip_semaphore_release();
+
+    return -1;
+  }
+
+  error = so_ioctl( iop, so, command, buffer );
+  rtems_lwip_semaphore_release();
+
+  if ( error ) {
+    errno = error;
+
+    return -1;
+  }
+
+  return 0;
+#endif
+
+  return -1;
+}
+
+static int rtems_lwip_fcntl(
+  rtems_libio_t *iop,
+  int            cmd
+)
+{
+#if 0
+  int lwipfd;
+
+  if ( cmd == F_SETFL ) {
+    rtems_lwip_semaphore_obtain();
+
+    if ( ( so = iop->data1 ) == NULL ) {
+      rtems_lwip_semaphore_release();
+
+      return EBADF;
+    }
+
+    if ( rtems_libio_iop_is_no_delay( iop ) )
+      so->so_state |= SS_NBIO;
+    else
+      so->so_state &= ~SS_NBIO;
+
+    rtems_lwip_semaphore_release();
+  }
+
+  return 0;
+#endif
+
+  return -1;
+}
+
+static int rtems_lwip_fstat(
+  const rtems_filesystem_location_info_t *loc,
+  struct stat                            *sp
+)
+{
+  sp->st_mode = S_IFSOCK;
+
+  return 0;
+}
+
+static const rtems_filesystem_file_handlers_r rtems_lwip_socket_handlers = {
+  .open_h = rtems_filesystem_default_open,
+  .close_h = rtems_lwip_close,
+  .read_h = rtems_lwip_read,
+  .write_h = rtems_lwip_write,
+  .ioctl_h = rtems_lwip_ioctl,
+  .lseek_h = rtems_filesystem_default_lseek,
+  .fstat_h = rtems_lwip_fstat,
+  .ftruncate_h = rtems_filesystem_default_ftruncate,
+  .fsync_h = rtems_filesystem_default_fsync_or_fdatasync,
+  .fdatasync_h = rtems_filesystem_default_fsync_or_fdatasync,
+  .fcntl_h = rtems_lwip_fcntl,
+  .kqfilter_h = rtems_filesystem_default_kqfilter,
+  .mmap_h = rtems_filesystem_default_mmap,
+  .poll_h = rtems_filesystem_default_poll,
+  .readv_h = rtems_filesystem_default_readv,
+  .writev_h = rtems_filesystem_default_writev
+};
+
+const char *
+inet_ntop(int af, const void *src, char *dst, socklen_t size){
+	    return lwip_inet_ntop(af, src, dst, size);
+}
diff --git a/rtemslwip/common/rtems_lwip_sysdefs.c b/rtemslwip/common/rtems_lwip_sysdefs.c
new file mode 100644
index 0000000..3877811
--- /dev/null
+++ b/rtemslwip/common/rtems_lwip_sysdefs.c
@@ -0,0 +1,185 @@
+/*
+ *
+ * RTEMS Project (https://www.rtems.org/)
+ *
+ * Copyright (c) 2021 Vijay Kumar Banerjee <vijay@rtems.org>.
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+
+#include "rtems_lwip_int.h"
+
+int rtems_lwip_sysdefs_AF_UNSPEC = AF_UNSPEC;
+int rtems_lwip_sysdefs_AF_UNIX = AF_UNIX;
+int rtems_lwip_sysdefs_AF_INET = AF_INET;
+int rtems_lwip_sysdefs_AF_INET6 = AF_INET6;
+int rtems_lwip_sysdefs_PF_UNSPEC = PF_UNSPEC;
+int rtems_lwip_sysdefs_PF_UNIX = PF_UNIX;
+int rtems_lwip_sysdefs_PF_INET = PF_INET;
+int rtems_lwip_sysdefs_PF_INET6 = PF_INET6;
+int rtems_lwip_sysdefs_SOCK_STREAM = SOCK_STREAM;
+int rtems_lwip_sysdefs_SOCK_DGRAM = SOCK_DGRAM;
+int rtems_lwip_sysdefs_SOCK_RAW = SOCK_RAW;
+int rtems_lwip_sysdefs_sockaddr_in_size = sizeof( struct sockaddr_in );
+int rtems_lwip_sysdefs_sockaddr_in6_size = sizeof( struct sockaddr_in6 );
+
+int rtems_lwip_sysdefs_sockaddr_get_len( const void *sockaddr )
+{
+  const struct sockaddr *so = sockaddr;
+
+  return so->sa_len;
+}
+
+int rtems_lwip_sysdefs_sockaddr_get_family( const void *sockaddr )
+{
+  const struct sockaddr *so = sockaddr;
+
+  return so->sa_family;
+}
+
+uint16_t rtems_lwip_sysdefs_sockaddr_in_get_sin_port( const void *sockaddr )
+{
+  const struct sockaddr_in *so = sockaddr;
+
+  return so->sin_port;
+}
+
+uint32_t rtems_lwip_sysdefs_sockaddr_in_get_sin_addr( const void *sockaddr )
+{
+  const struct sockaddr_in *so = sockaddr;
+
+  return so->sin_addr.s_addr;
+}
+
+uint16_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_port( const void *sockaddr )
+{
+  const struct sockaddr_in6 *so = sockaddr;
+
+  return so->sin6_port;
+}
+
+const uint8_t *rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr_const(
+  const void *sockaddr )
+{
+  const struct sockaddr_in6 *so = sockaddr;
+
+  return (uint8_t *) &so->sin6_addr;
+}
+
+uint8_t *rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr(
+  void *sockaddr )
+{
+  struct sockaddr_in6 *so = sockaddr;
+
+  return (uint8_t *) &so->sin6_addr;
+}
+
+uint32_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_flowinfo(
+  const void *sockaddr )
+{
+  const struct sockaddr_in6 *so = sockaddr;
+
+  return so->sin6_flowinfo;
+}
+
+uint32_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_scope_id(
+  const void *sockaddr )
+{
+  const struct sockaddr_in6 *so = sockaddr;
+
+  return so->sin6_scope_id;
+}
+
+void rtems_lwip_sysdefs_sockaddr_set_len(
+  void *sockaddr,
+  int   len
+)
+{
+  struct sockaddr *so = sockaddr;
+
+  so->sa_len = len;
+}
+
+void rtems_lwip_sysdefs_sockaddr_set_family(
+  void *sockaddr,
+  int   family
+)
+{
+  struct sockaddr *so = sockaddr;
+
+  so->sa_family = family;
+}
+
+void rtems_lwip_sysdefs_sockaddr_in_set_sin_port(
+  void    *sockaddr,
+  uint16_t port
+)
+{
+  struct sockaddr_in *so = sockaddr;
+
+  so->sin_port = port;
+}
+
+void rtems_lwip_sysdefs_sockaddr_in_set_sin_addr(
+  void    *sockaddr,
+  uint32_t addr
+)
+{
+  struct sockaddr_in *so = sockaddr;
+
+  so->sin_addr.s_addr = addr;
+}
+
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_port(
+  void    *sockaddr,
+  uint16_t port
+)
+{
+  struct sockaddr_in6 *so = sockaddr;
+
+  so->sin6_port = port;
+}
+
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_flowinfo(
+  void    *sockaddr,
+  uint32_t flowinfo
+)
+{
+  struct sockaddr_in6 *so = sockaddr;
+
+  so->sin6_flowinfo = flowinfo;
+}
+
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_scope_id(
+  void    *sockaddr,
+  uint32_t scope_id
+)
+{
+  struct sockaddr_in6 *so = sockaddr;
+
+  so->sin6_scope_id = scope_id;
+}
diff --git a/rtemslwip/common/syslog.c b/rtemslwip/common/syslog.c
new file mode 100644
index 0000000..e544074
--- /dev/null
+++ b/rtemslwip/common/syslog.c
@@ -0,0 +1,89 @@
+/*
+ * RTEMS version of syslog and associated routines
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems.h>
+#include <rtems/thread.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <errno.h>
+#include <syslog.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <string.h>
+
+#include <unistd.h>
+
+static int LogStatus = LOG_CONS;
+static const char *LogTag = "syslog";
+static int LogFacility = LOG_USER;
+static int LogMask = 0xff;
+
+void
+syslog (int pri, const char *fmt, ...)
+{
+	va_list ap;
+
+	va_start (ap, fmt);
+	vsyslog (pri, fmt, ap);
+	va_end (ap);
+}
+
+/*
+ * FIXME: Should cbuf be static?  Then we wouldn't
+ *        have to worry about blowing stacks with a local variable
+ *        that large.  Could make cbuf bigger, too.
+ */
+void
+vsyslog (int pri, const char *fmt, va_list ap)
+{
+	int cnt;
+	char cbuf[200];
+
+	if (pri & ~(LOG_PRIMASK|LOG_FACMASK)) {
+		syslog (LOG_ERR|LOG_CONS|LOG_PERROR|LOG_PID,
+								"syslog: unknown facility/priority: %#x", pri);
+		pri &= LOG_PRIMASK|LOG_FACMASK;
+	}
+
+	if (!(LOG_MASK(LOG_PRI(pri)) & LogMask))
+		return;
+
+	if ((pri & LOG_FACMASK) == 0)
+		pri |= LogFacility;
+
+	cnt = snprintf (cbuf, sizeof (cbuf), "<%d>", pri);
+	if (LogTag && cnt < sizeof (cbuf) - 1)
+		cnt += snprintf (cbuf + cnt, sizeof (cbuf) - cnt, "%s", LogTag);
+	if (LogStatus & LOG_PID && cnt < sizeof (cbuf) - 1) {
+		rtems_id tid;
+		rtems_task_ident (RTEMS_SELF, 0, &tid);
+		cnt += snprintf (cbuf + cnt, sizeof (cbuf) - cnt, "[%#lx]", (unsigned long)tid);
+	}
+	if (LogTag && cnt < sizeof (cbuf) - 1)
+		cnt += snprintf (cbuf + cnt, sizeof (cbuf) - cnt, ": ");
+	cnt += vsnprintf (cbuf + cnt, sizeof (cbuf) - cnt, fmt, ap);
+	if (cnt > sizeof (cbuf) - 1)
+		cnt = sizeof (cbuf) - 1;
+	while (cnt > 0 && cbuf[cnt-1] == '\n')
+		cbuf[--cnt] = '\0';
+
+	if (LogStatus & LOG_PERROR)
+		printf ("%s\n", cbuf);
+}
+
+int
+setlogmask (int pmask)
+{
+	int omask;
+
+	omask = LogMask;
+	if (pmask != 0)
+		LogMask = pmask;
+	return (omask);
+}
diff --git a/rtemslwip/include/rtems_lwip_int.h b/rtemslwip/include/rtems_lwip_int.h
new file mode 100644
index 0000000..9d3d548
--- /dev/null
+++ b/rtemslwip/include/rtems_lwip_int.h
@@ -0,0 +1,92 @@
+/*
+ *
+ * RTEMS Project (https://www.rtems.org/)
+ *
+ * Copyright (c) 2021 Vijay Kumar Banerjee <vijay@rtems.org>.
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  1. Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef RTEMS_LWIP_INT_H
+#define RTEMS_LWIP_INT_H
+
+#include <stdint.h>
+
+extern int rtems_lwip_sysdefs_AF_UNSPEC;
+extern int rtems_lwip_sysdefs_AF_UNIX;
+extern int rtems_lwip_sysdefs_AF_INET;
+extern int rtems_lwip_sysdefs_AF_INET6;
+extern int rtems_lwip_sysdefs_PF_UNSPEC;
+extern int rtems_lwip_sysdefs_PF_UNIX;
+extern int rtems_lwip_sysdefs_PF_INET;
+extern int rtems_lwip_sysdefs_PF_INET6;
+extern int rtems_lwip_sysdefs_SOCK_STREAM;
+extern int rtems_lwip_sysdefs_SOCK_DGRAM;
+extern int rtems_lwip_sysdefs_SOCK_RAW;
+extern int rtems_lwip_sysdefs_sockaddr_in_size;
+extern int rtems_lwip_sysdefs_sockaddr_in6_size;
+
+int rtems_lwip_sysdefs_sockaddr_get_len( const void *sockaddr );
+int rtems_lwip_sysdefs_sockaddr_get_family( const void *sockaddr );
+uint16_t rtems_lwip_sysdefs_sockaddr_in_get_sin_port( const void *sockaddr );
+uint32_t rtems_lwip_sysdefs_sockaddr_in_get_sin_addr( const void *sockaddr );
+uint16_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_port( const void *sockaddr );
+const uint8_t *rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr_const(
+  const void *sockaddr );
+uint8_t *rtems_lwip_sysdefs_sockaddr_in6_get_sin6_addr_ptr(
+  void *sockaddr );
+uint32_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_flowinfo(
+  const void *sockaddr );
+uint32_t rtems_lwip_sysdefs_sockaddr_in6_get_sin6_scope_id(
+  const void *sockaddr );
+
+void rtems_lwip_sysdefs_sockaddr_set_len(
+  void *sockaddr,
+  int   len
+);
+void rtems_lwip_sysdefs_sockaddr_set_family(
+  void *sockaddr,
+  int   family
+);
+void rtems_lwip_sysdefs_sockaddr_in_set_sin_port(
+  void    *sockaddr,
+  uint16_t port
+);
+void rtems_lwip_sysdefs_sockaddr_in_set_sin_addr(
+  void    *sockaddr,
+  uint32_t addr
+);
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_port(
+  void    *sockaddr,
+  uint16_t port
+);
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_flowinfo(
+  void    *sockaddr,
+  uint32_t flowinfo
+);
+void rtems_lwip_sysdefs_sockaddr_in6_set_sin6_scope_id(
+  void    *sockaddr,
+  uint32_t scope_id
+);
+
+#endif /*RTEMS_LWIP_INT_H*/
diff --git a/rtemslwip/include/sys/sysctl.h b/rtemslwip/include/sys/sysctl.h
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/rtemslwip/include/sys/sysctl.h
@@ -0,0 +1 @@
+
diff --git a/lwip/test/buffer_test_io.h b/rtemslwip/test/buffer_test_io.h
index f0eae50..f0eae50 100644
--- a/lwip/test/buffer_test_io.h
+++ b/rtemslwip/test/buffer_test_io.h
diff --git a/lwip/test/sample_app.c b/rtemslwip/test/networking01/sample_app.c
index 576cd6b..576cd6b 100644
--- a/lwip/test/sample_app.c
+++ b/rtemslwip/test/networking01/sample_app.c
diff --git a/rtemslwip/test/telnetd01/init.c b/rtemslwip/test/telnetd01/init.c
new file mode 100644
index 0000000..f1fe036
--- /dev/null
+++ b/rtemslwip/test/telnetd01/init.c
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/telnetd.h>
+#include <lwip/dhcp.h>
+#include <lwip/tcpip.h>
+
+#include <tmacros.h>
+
+const char rtems_test_name[] = "TELNETD 1";
+
+//struct rtems_bsdnet_config rtems_bsdnet_config;
+
+rtems_shell_env_t env;
+
+static void telnet_shell( char *name, void *arg )
+{
+  rtems_shell_dup_current_env( &env );
+
+  env.devname = name;
+  env.taskname = "TLNT";
+
+  rtems_shell_main_loop( &env );
+}
+
+rtems_telnetd_config_table rtems_telnetd_config = {
+  .command = telnet_shell,
+  .stack_size = 8 * RTEMS_MINIMUM_STACK_SIZE,
+};
+
+#define print_ip( tag, ip ) \
+  printf( \
+  "%s: %" PRId32 ".%" PRId32 ".%" PRId32 ".%" PRId32 "\n", \
+  tag, \
+  ( ntohl( ip.addr ) >> 24 ) & 0xff, \
+  ( ntohl( ip.addr ) >> 16 ) & 0xff, \
+  ( ntohl( ip.addr ) >> 8 ) & 0xff, \
+  ntohl( ip.addr ) & 0xff \
+  );
+
+static int shell_main_netinfo(
+  int    argc,
+  char **argv
+)
+{
+  print_ip( "IP", net_interface.ip_addr.u_addr.ip4 );
+  print_ip( "Mask", net_interface.netmask.u_addr.ip4 );
+  print_ip( "GW", net_interface.gw.u_addr.ip4 );
+  return 0;
+}
+
+rtems_shell_cmd_t shell_NETINFO_Command = {
+  "netinfo",                                          /* name */
+  "netinfo - shows basic network info, no arguments", /* usage */
+  "net",                                              /* topic */
+  shell_main_netinfo,                                 /* command */
+  NULL,                                               /* alias */
+  NULL                                                /* next */
+};
+
+static rtems_task Init( rtems_task_argument argument )
+{
+  rtems_status_code sc;
+
+  TEST_BEGIN();
+
+  lwip_init();
+
+  rtems_shell_init_environment();
+
+  dhcp_start( &net_interface );
+
+  sc = rtems_telnetd_start( &rtems_telnetd_config );
+  rtems_test_assert( sc == RTEMS_SUCCESSFUL );
+
+  sc = rtems_shell_init(
+    "SHLL",                       /* task name */
+    RTEMS_MINIMUM_STACK_SIZE * 4, /* task stack size */
+    100,                          /* task priority */
+    "/dev/console",               /* device name */
+    false,                        /* run forever */
+    true,                         /* wait for shell to terminate */
+    NULL                          /* login check function,
+                                     use NULL to disable a login check */
+  );
+  rtems_test_assert( sc == RTEMS_SUCCESSFUL );
+  sys_arch_delay( 300000 );
+
+  TEST_END();
+  rtems_test_exit( 0 );
+}
+
+#define CONFIGURE_INIT
+
+#define CONFIGURE_MICROSECONDS_PER_TICK 10000
+
+#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
+#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
+#define CONFIGURE_APPLICATION_NEEDS_LIBBLOCK
+
+#define CONFIGURE_MAXIMUM_FILE_DESCRIPTORS 32
+
+#define CONFIGURE_SHELL_COMMANDS_INIT
+#define CONFIGURE_SHELL_COMMANDS_ALL
+#define CONFIGURE_SHELL_USER_COMMANDS &shell_NETINFO_Command
+
+#define CONFIGURE_MAXIMUM_TASKS 12
+
+#define CONFIGURE_MAXIMUM_POSIX_KEYS 1
+#define CONFIGURE_MAXIMUM_SEMAPHORES 20
+#define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 10
+
+#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
+
+#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
+
+#define CONFIGURE_INIT_TASK_ATTRIBUTES RTEMS_FLOATING_POINT
+
+#define CONFIGURE_UNLIMITED_OBJECTS
+#define CONFIGURE_UNIFIED_WORK_AREAS
+
+#include <rtems/shellconfig.h>
+
+#include <rtems/confdefs.h>
diff --git a/rtemslwip/test/telnetd01/telnetd01.doc b/rtemslwip/test/telnetd01/telnetd01.doc
new file mode 100644
index 0000000..fe1a4d3
--- /dev/null
+++ b/rtemslwip/test/telnetd01/telnetd01.doc
@@ -0,0 +1,24 @@
+# 
+# Copyright (c) 2018 embedded brains GmbH.  All rights reserved.
+# 
+#  embedded brains GmbH
+#  Dornierstr. 4
+#  82178 Puchheim
+#  Germany
+#  <rtems@embedded-brains.de>
+# 
+# The license and distribution terms for this file may be
+# found in the file LICENSE in this distribution or at
+# http://www.rtems.org/license/LICENSE.
+
+This file describes the directives and concepts tested by this test set.
+
+test set name: telnetd01
+
+directives:
+
+  - rtems_telnetd_start()
+
+concepts:
+
++ Check if Telnet server works.
diff --git a/rtemslwip/test/telnetd01/telnetd01.scn b/rtemslwip/test/telnetd01/telnetd01.scn
new file mode 100644
index 0000000..3e9cc00
--- /dev/null
+++ b/rtemslwip/test/telnetd01/telnetd01.scn
@@ -0,0 +1,11 @@
+*** BEGIN OF TEST TELNETD 1 ***
+*** TEST VERSION: 5.0.0.dc32b6aa0807fb70f9b26bc0bc6e164ddb49bd3a
+*** TEST STATE: EXPECTED_PASS
+*** TEST BUILD: RTEMS_NETWORKING
+*** TEST TOOLS: 7.3.0 20180125 (RTEMS 5, RSB 9670d7541e0621915e521fe76e7bb33de8cee661, Newlib d13c84eb07e35984bf7a974cd786a6cdac29e6b9)
+syslog: telnetd: configuration with invalid command
+syslog: telnetd: cannot create session task
+syslog: telnetd: started successfully on port 23
+syslog: telnetd: cannot bind server socket
+
+*** END OF TEST TELNETD 1 ***
diff --git a/lwip/test/tmacros.h b/rtemslwip/test/tmacros.h
index 8189149..8189149 100644
--- a/lwip/test/tmacros.h
+++ b/rtemslwip/test/tmacros.h
diff --git a/uLan/ports/driver/tms570_emac/eth_lwip.c b/uLan/ports/driver/tms570_emac/eth_lwip.c
index b1ae4bb..6105268 100644
--- a/uLan/ports/driver/tms570_emac/eth_lwip.c
+++ b/uLan/ports/driver/tms570_emac/eth_lwip.c
@@ -39,7 +39,7 @@
 #include "netif/etharp.h" /* includes - lwip/ip.h, lwip/netif.h, lwip/ip_addr.h, lwip/pbuf.h */
 #include "eth_lwip_default.h"
 #include "eth_lwip.h"
-#include "tms570_netif.h"
+#include "beaglebone.h"
 #include <stdio.h>
 
 /* The lwIP network interface structure for the Ethernet EMAC. */
diff --git a/uLan/ports/driver/tms570_emac/eth_lwip_default.h b/uLan/ports/driver/tms570_emac/eth_lwip_default.h
index 6194d06..863e9e1 100644
--- a/uLan/ports/driver/tms570_emac/eth_lwip_default.h
+++ b/uLan/ports/driver/tms570_emac/eth_lwip_default.h
@@ -3,7 +3,7 @@
 
 /* #define DEBUG 1 */
 /* #define STATIC_IP_ADDRESS 1 */
-
+#if 0
 void tms570_eth_memp_avaible(int type);
 
 #define ETH_LWIP_INIT_NETIF_FNC tms570_eth_init_netif
@@ -14,6 +14,7 @@ void tms570_eth_memp_avaible(int type);
 /**
  * Default MAC address for interface.
  */
+#endif /* 0 */
 #define MAC_ADDR_LEN              ETHARP_HWADDR_LEN
 
 #ifndef ETH_MAC_ADDR
diff --git a/uLan/ports/driver/tms570_emac/ti_drv_mdio.h b/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
index e115231..e17046c 100644
--- a/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
+++ b/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
@@ -32,6 +32,7 @@
 *
 */
 
+#if 0
 #ifndef __MDIO_H__
 #define __MDIO_H__
 
@@ -163,3 +164,4 @@ MDIOInit(volatile tms570_mdio_t *baseAddr, uint32_t mdioInputFreq,
 }
 #endif
 #endif /* __MDIO_H__ */
+#endif /* 0 */
diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.h b/uLan/ports/driver/tms570_emac/tms570_netif.h
index 325249a..c2087ed 100644..100755
--- a/uLan/ports/driver/tms570_emac/tms570_netif.h
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.h
@@ -1,60 +1,60 @@
-/*
- * Copyright (c) 2013, 2015 Czech Technical University in Prague
- * Czech Republic
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Premysl Houdek <houdepre@fel.cvut.cz>
- * Mentor: Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Industrial Informatics Group, FEE, Czech Technical University in Prague
- *
- * Based on work of Carlos Jenkins, Rostislav Lisovy, Jan Dolezal
- */
-
-#ifndef __TMS570_NETIF_H
-#define __TMS570_NETIF_H
-
-//#define TMS570_NETIF_DEBUG 1
-
-#ifdef TMS570_NETIF_DEBUG
-#define tms570_eth_debug_printf sys_arch_printk
-#else
-#define tms570_eth_debug_printf(...)
-#endif
-
-err_t tms570_eth_init_netif(struct netif *netif);
-struct tms570_netif_state *tms570_eth_init_state();
-
-#if TMS570_NETIF_DEBUG
-struct emac_rx_bd;
-int tms570_eth_debug_get_BD_num(volatile void *ptr, struct tms570_netif_state *nf_state);
-void tms570_eth_debug_print_rxch(struct tms570_netif_state *nf_state);
-void tms570_eth_debug_print_txch(struct tms570_netif_state *nf_state);
-void tms570_eth_debug_show_BD_chain(volatile struct emac_rx_bd *curr_bd, struct tms570_netif_state *nf_state);
-void tms570_eth_debug_show_rx(struct tms570_netif_state *nf_state);
-void tms570_eth_debug_show_tx(struct tms570_netif_state *nf_state);
-void tms570_eth_debug_print_HDP(struct tms570_netif_state *nf_state);
-void tms570_eth_debug_print_info(struct netif *netif);
-#endif /* TMS570_NETIF_DEBUG */
-
-#endif /* __TMS570_NETIF_H */
+/*

+ * Copyright (c) 2013, 2015 Czech Technical University in Prague

+ * Czech Republic

+ *

+ * Redistribution and use in source and binary forms, with or without modification,

+ * are permitted provided that the following conditions are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright notice,

+ *    this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright notice,

+ *    this list of conditions and the following disclaimer in the documentation

+ *    and/or other materials provided with the distribution.

+ * 3. The name of the author may not be used to endorse or promote products

+ *    derived from this software without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED

+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT

+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT

+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING

+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY

+ * OF SUCH DAMAGE.

+ *

+ * Author: Premysl Houdek <houdepre@fel.cvut.cz>

+ * Mentor: Pavel Pisa <pisa@cmp.felk.cvut.cz>

+ * Industrial Informatics Group, FEE, Czech Technical University in Prague

+ *

+ * Based on work of Carlos Jenkins, Rostislav Lisovy, Jan Dolezal

+ */

+

+#ifndef __TMS570_NETIF_H

+#define __TMS570_NETIF_H

+

+//#define TMS570_NETIF_DEBUG 1

+

+#ifdef TMS570_NETIF_DEBUG

+#define tms570_eth_debug_printf sys_arch_printk

+#else

+#define tms570_eth_debug_printf(...)

+#endif

+

+err_t tms570_eth_init_netif(struct netif *netif);

+struct tms570_netif_state *tms570_eth_init_state();

+

+#if TMS570_NETIF_DEBUG

+struct emac_rx_bd;

+int tms570_eth_debug_get_BD_num(volatile void *ptr, struct tms570_netif_state *nf_state);

+void tms570_eth_debug_print_rxch(struct tms570_netif_state *nf_state);

+void tms570_eth_debug_print_txch(struct tms570_netif_state *nf_state);

+void tms570_eth_debug_show_BD_chain(volatile struct emac_rx_bd *curr_bd, struct tms570_netif_state *nf_state);

+void tms570_eth_debug_show_rx(struct tms570_netif_state *nf_state);

+void tms570_eth_debug_show_tx(struct tms570_netif_state *nf_state);

+void tms570_eth_debug_print_HDP(struct tms570_netif_state *nf_state);

+void tms570_eth_debug_print_info(struct netif *netif);

+#endif /* TMS570_NETIF_DEBUG */

+

+#endif /* __TMS570_NETIF_H */

diff --git a/uLan/ports/os/lwipopts.h b/uLan/ports/os/lwipopts.h
index 50ac639..6e4287a 100644
--- a/uLan/ports/os/lwipopts.h
+++ b/uLan/ports/os/lwipopts.h
@@ -1,3 +1,4 @@
+#if 0
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
  * All rights reserved. 
@@ -43,12 +44,23 @@
 
 #define LWIP_ETHERNET                   1
 #define LWIP_NETIF_API                  1
+#define LWIP_AUTOIP                     1
 /* Enable DHCP to test it, disable UDP checksum to easier inject packets */
 #define LWIP_DHCP                       1
 #define LWIP_TIMEVAL_PRIVATE            0
-#define LWIP_POSIX_SOCKETS_IO_NAMES     0
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+//#define LWIP_COMPAT_SOCKETS             2
+#ifndef FIONREAD
+#define FIONREAD                        1
+#endif
+#ifndef FIONBIO
+#define FIONBIO                         1
+#endif
+#define THREAD_STACK_SIZE               4096
 
+#define LWIP_TIMERS                     1
 /* Minimal changes to opt.h required for tcp unit tests: */
+
 #define MEM_SIZE                        16000
 #define TCP_SND_QUEUELEN                40
 #define MEMP_NUM_TCP_SEG                TCP_SND_QUEUELEN
@@ -62,3 +74,199 @@
 #define ETHARP_SUPPORT_STATIC_ENTRIES   1
 
 #endif /* LWIP_HDR_LWIPOPTS_H__ */
+
+#endif /* 0 */
+
+/**
+ * \file lwipopts.h - Configuration options for lwIP
+ *
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/*****************************************************************************
+**                           CONFIGURATIONS
+*****************************************************************************/
+
+/*
+** The macro CPSW_DUAL_MAC_MODE shall be defined for using CPSW ports in
+** Dual MAC mode.
+*/
+#define CPSW_DUAL_MAC_MODE
+
+/*
+** The below macro should be defined for using lwIP with cache. For cache
+** enabling, pbuf pool shall be cache line aligned. This is done by using
+** separate pool for each memory. The alignment of pbuf pool to cache line
+** size is done in /ports/cpsw/include/arch/cc.h.
+*/
+/*#define LWIP_CACHE_ENABLED*/
+
+#define SOC_CACHELINE_SIZE_BYTES        64            /* Number of bytes in
+                                                         a cache line */
+/*
+** The timeout for DHCP completion. lwIP library will wait for DHCP
+** completion for (LWIP_DHCP_TIMEOUT / 100) seconds.
+*/
+#define LWIP_DHCP_TIMEOUT               1000
+
+/*
+** The number of times DHCP is attempted. Each time, the library will wait
+** for (LWIP_DHCP_TIMEOUT / 100) seconds for DHCP completion.
+*/
+#define NUM_DHCP_TRIES                  5
+
+#define LWIP_ETHERNET 1
+#define LWIP_ARP 1
+#define LWIP_DNS 1
+
+/*****************************************************************************
+**            lwIP SPECIFIC DEFINITIONS - To be used by lwIP stack
+*****************************************************************************/
+#define HOST_TMR_INTERVAL               0
+#define DYNAMIC_HTTP_HEADERS
+
+/*****************************************************************************
+**                    Platform specific locking
+*****************************************************************************/
+#define SYS_LIGHTWEIGHT_PROT            1
+#define NO_SYS                          0
+#define NO_SYS_NO_TIMERS                0
+
+/*****************************************************************************
+**                          Memory Options
+*****************************************************************************/
+#define MEM_ALIGNMENT                   4
+#define MEM_SIZE                        (1024 * 1024) /* 4K */
+
+#define MEMP_NUM_PBUF                   96
+#define MEMP_NUM_TCP_PCB                32
+#define MEMP_NUM_TCP_SEG                32
+#define PBUF_POOL_SIZE                  512
+#define MEMP_MEM_MALLOC                 1
+#define MEMP_MEM_INIT                   1
+#define MEMP_OVERFLOW_CHECK             0
+
+#ifdef LWIP_CACHE_ENABLED
+#define MEMP_SEPARATE_POOLS             1            /* We want the pbuf
+                                                        pool cache line
+                                                        aligned*/
+#endif
+
+//#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)
+
+/*****************************************************************************
+**                           IP Options
+*****************************************************************************/
+#define IP_REASSEMBLY                   0
+#define IP_FRAG                         0
+#define LWIP_IPV4                       1
+#define LWIP_IPV6                       1
+
+/*****************************************************************************
+**                           DHCP Options
+*****************************************************************************/
+#define LWIP_DHCP                       1
+#define DHCP_DOES_ARP_CHECK             0
+
+/*****************************************************************************
+**                           Auto IP  Options
+*****************************************************************************/
+#define LWIP_AUTOIP                     1
+#define LWIP_DHCP_AUTOIP_COOP           ((LWIP_DHCP) && (LWIP_AUTOIP))
+
+/*****************************************************************************
+**                           TCP  Options
+*****************************************************************************/
+#define TCP_MSS                         1500
+#define TCP_WND                         (8 * TCP_MSS)
+#define TCP_SND_BUF                     (8 * TCP_MSS)
+#define TCP_OVERSIZE                    TCP_MSS
+#define LWIP_TCPIP_CORE_LOCKING         1
+
+/*****************************************************************************
+**                           PBUF  Options
+*****************************************************************************/
+#define PBUF_LINK_HLEN                  14
+#define PBUF_POOL_BUFSIZE               1520         /* + size of struct pbuf
+                                                        shall be cache line
+                                                        aligned be enabled */
+#define ETH_PAD_SIZE                    0
+#define LWIP_NETCONN                    1
+
+/*****************************************************************************
+**                           Socket  Options
+*****************************************************************************/
+#define LWIP_SOCKET                     1
+#define SO_REUSE                        1
+
+/*****************************************************************************
+**                          Debugging options
+*****************************************************************************/
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_OFF
+#define LWIP_DBG_TYPES_ON               (LWIP_DBG_ON | LWIP_DBG_TRACE \
+                                         |LWIP_DBG_STATE | LWIP_DBG_FRESH)
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#define IP_DEBUG			LWIP_DBG_OFF
+#define UDP_DEBUG			LWIP_DBG_OFF
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#define PBUF_DEBUG			LWIP_DBG_OFF
+#define TCPIP_DEBUG			LWIP_DBG_OFF
+#define APP_DEBUG			LWIP_DBG_OFF
+#define SOCKETS_DEBUG		LWIP_DBG_OFF
+#define LWIP_STATS                      0
+#define LWIP_STATS_DISPLAY              0
+#define LWIP_STATS_POSIX                0
+#define LWIP_DNS_API_DEFINE_ERRORS      1
+
+
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#define LWIP_COMPAT_SOCKETS            0
+
+ #define LWIP_TIMEVAL_PRIVATE 0
+
+ #define LWIP_RAW                        0
+
+#endif /* __LWIPOPTS_H__ */