BBB: Clean up *.c and *.h files using 'astyle --unpad-paren --align-pointer=name --lineend=linux --add-brackets --convert-tabs -A4 <file>'

Note: <file> is the file being formatted

8 files changed, 1381 insertions, 1317 deletions

diff --git a/ports/beagleboneblack/am335x_mmc.c b/ports/beagleboneblack/am335x_mmc.c
index bba60a2..913917f 100644
--- a/ports/beagleboneblack/am335x_mmc.c
+++ b/ports/beagleboneblack/am335x_mmc.c
@@ -16,472 +16,500 @@ uint16_t mmcrca;
 int mmcInum;
 
 char *mmcHelp[] = {
-	"MultiMediaCard Interface",
-	"[options] {operation} [args]...",
+    "MultiMediaCard Interface",
+    "[options] {operation} [args]...",
 #if INCLUDE_VERBOSEHELP
-	"",
-	"Options:",
-	" -i ##	interface # (default is 0)",
-	" -v 	additive verbosity",
-	"",
-	"Operations:",
-	" init",
-	" read {dest} {blk} {blktot}",
-	" write {source} {blk} {blktot}",
+    "",
+    "Options:",
+    " -i ##	interface # (default is 0)",
+    " -v 	additive verbosity",
+    "",
+    "Operations:",
+    " init",
+    " read {dest} {blk} {blktot}",
+    " write {source} {blk} {blktot}",
 #endif /* INCLUDE_VERBOSEHELP */
-	0
+    0
 };
 
 int
 mmccmd(uint32_t cmd, uint32_t arg, uint32_t resp[4])
 {
-	/* Clear the SD_STAT register for proper update of status bits after CMD invocation */
-	MMC1_REG(SD_STAT) = 0xFFFFFFFF;
-
-	MMC1_REG(SD_ARG) = arg;
-	MMC1_REG(SD_CMD) = cmd;
-
-	/* CMDx complete? */
-	while (!(MMC1_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
-
-	resp[0] = MMC1_REG(SD_RSP10);
-	resp[1] = MMC1_REG(SD_RSP32);
-	resp[2] = MMC1_REG(SD_RSP54);
-	resp[3] = MMC1_REG(SD_RSP76);
-
-	/* CMDx error? */
-	if (MMC1_REG(SD_STAT) & SD_STAT_ERRI)
-		return(-1);
-	else
-		return(0);
+    /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
+    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
+
+    MMC1_REG(SD_ARG) = arg;
+    MMC1_REG(SD_CMD) = cmd;
+
+    /* CMDx complete? */
+    while(!(MMC1_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
+
+    resp[0] = MMC1_REG(SD_RSP10);
+    resp[1] = MMC1_REG(SD_RSP32);
+    resp[2] = MMC1_REG(SD_RSP54);
+    resp[3] = MMC1_REG(SD_RSP76);
+
+    /* CMDx error? */
+    if(MMC1_REG(SD_STAT) & SD_STAT_ERRI) {
+        return(-1);
+    } else {
+        return(0);
+    }
 }
 
 int
 mmc(int argc, char *argv[])
 {
-	char *cmd, *buf;
-	int opt, verbose, mmcret, blknum, blkcnt;
-
-	verbose = 0;
-
-	while ((opt = getopt(argc, argv, "i:v")) != -1) {
-		switch (opt) {
-			case 'i':
-				mmcInum = atoi(optarg);
-				break;
-			case 'v':
-				verbose++;
-				break;
-			default:
-				return(CMD_PARAM_ERROR);
-		}
-	}
-
-	if (argc < optind + 1)
-		return(CMD_PARAM_ERROR);
-
-	cmd = argv[optind];
-
-	if (mmcInstalled(mmcInum) == 0) {
-		printf("MMC not installed\n");
-		return(CMD_FAILURE);
-	}
-
-	if (strcmp(cmd, "init") == 0) {
-		mmcret = mmcInit(mmcInum, verbose);
-		if(mmcret < 0) {
-			printf("mmcInit returned %d\n", mmcret);
-			return(CMD_FAILURE);
-		}
-	}
-	else if (strcmp(cmd, "read") == 0) {
-		if (argc != (optind + 4))
-			return(CMD_PARAM_ERROR);
-
-		buf = (char *)strtoul(argv[optind + 1], 0, 0);
-		blknum = strtoul(argv[optind + 2], 0, 0);
-		blkcnt = strtoul(argv[optind + 3], 0, 0);
-
-		mmcret = mmcRead(mmcInum, buf, blknum, blkcnt);
-		if (mmcret < 0) {
-			printf("mmcRead returned %d\n", mmcret);
-			return(CMD_FAILURE);
-		}
-	}
-	else if (strcmp(cmd, "write") == 0) {
-		if (argc != (optind + 4))
-			return(CMD_PARAM_ERROR);
-
-		buf = (char *)strtoul(argv[optind + 1], 0, 0);
-		blknum = strtoul(argv[optind + 2], 0, 0);
-		blkcnt = strtoul(argv[optind + 3], 0, 0);
-
-		mmcret = mmcWrite(mmcInum, buf, blknum, blkcnt);
-		if (mmcret < 0) {
-			printf("mmcWrite returned %d\n", mmcret);
-			return(CMD_FAILURE);
-		}
-	}
-	else {
-		printf("mmc op <%s> not found\n", cmd);
-		return(CMD_FAILURE);
-	}
-
-	return(CMD_SUCCESS);
+    char *cmd, *buf;
+    int opt, verbose, mmcret, blknum, blkcnt;
+
+    verbose = 0;
+
+    while((opt = getopt(argc, argv, "i:v")) != -1) {
+        switch(opt) {
+        case 'i':
+            mmcInum = atoi(optarg);
+            break;
+        case 'v':
+            verbose++;
+            break;
+        default:
+            return(CMD_PARAM_ERROR);
+        }
+    }
+
+    if(argc < optind + 1) {
+        return(CMD_PARAM_ERROR);
+    }
+
+    cmd = argv[optind];
+
+    if(mmcInstalled(mmcInum) == 0) {
+        printf("MMC not installed\n");
+        return(CMD_FAILURE);
+    }
+
+    if(strcmp(cmd, "init") == 0) {
+        mmcret = mmcInit(mmcInum, verbose);
+        if(mmcret < 0) {
+            printf("mmcInit returned %d\n", mmcret);
+            return(CMD_FAILURE);
+        }
+    } else if(strcmp(cmd, "read") == 0) {
+        if(argc != (optind + 4)) {
+            return(CMD_PARAM_ERROR);
+        }
+
+        buf = (char *)strtoul(argv[optind + 1], 0, 0);
+        blknum = strtoul(argv[optind + 2], 0, 0);
+        blkcnt = strtoul(argv[optind + 3], 0, 0);
+
+        mmcret = mmcRead(mmcInum, buf, blknum, blkcnt);
+        if(mmcret < 0) {
+            printf("mmcRead returned %d\n", mmcret);
+            return(CMD_FAILURE);
+        }
+    } else if(strcmp(cmd, "write") == 0) {
+        if(argc != (optind + 4)) {
+            return(CMD_PARAM_ERROR);
+        }
+
+        buf = (char *)strtoul(argv[optind + 1], 0, 0);
+        blknum = strtoul(argv[optind + 2], 0, 0);
+        blkcnt = strtoul(argv[optind + 3], 0, 0);
+
+        mmcret = mmcWrite(mmcInum, buf, blknum, blkcnt);
+        if(mmcret < 0) {
+            printf("mmcWrite returned %d\n", mmcret);
+            return(CMD_FAILURE);
+        }
+    } else {
+        printf("mmc op <%s> not found\n", cmd);
+        return(CMD_FAILURE);
+    }
+
+    return(CMD_SUCCESS);
 }
 
 int
 mmcInit(int interface, int verbose)
 {
-	uint32_t cmd, arg, resp[4];
-
-	/* Reset the MMC1 Controller */
-	MMC1_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
-	while (!(MMC1_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
-
-	/* Reset the command and data lines */
-	MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
-	while (MMC1_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
-
-	/* Configure the MMC1 controller capabilities to enable 3.0 V operating voltage */
-	MMC1_REG(SD_CAPA) |= SD_CAPA_VS30;
-
-	/* Configure SD_IE register to update certain status bits in SD_STAT */
-	MMC1_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
-		SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
-		SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
-		SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
-		SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
-
-	/* Configure the operating voltage to 3.0 V */
-	MMC1_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
-	MMC1_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
-
-	/* Turn on the bus */
-	MMC1_REG(SD_HCTL) |= SD_HCTL_SDBP;
-	while (!(MMC1_REG(SD_HCTL) & SD_HCTL_SDBP));
-
-	/* Enable the internal clock */
-	MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
-
-	/* Configure Clock Frequency Select to 100 KHz */
-	MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (960 << 6);
-
-	/* Wait for clock to stabilize */
-	while (!(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
-
-	/* Configure SD_SYSCONFIG */
-	MMC1_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
-	MMC1_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
-		SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
-
-	/* Enable the clock to the eMMC */
-	MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_CEN;
-
-	/* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
-	   "Card Detection, Identification, and Selection" */
-	MMC1_REG(SD_CON) |= SD_CON_INIT;
-	/* Clear the SD_STAT register */
-	MMC1_REG(SD_STAT) = 0xFFFFFFFF;
-	MMC1_REG(SD_ARG) = 0x00000000;
-	MMC1_REG(SD_CMD) = 0x00000000;
-	while (!(MMC1_REG(SD_STAT) & SD_STAT_CC));
-	/* Clear CC flag in SD_STAT */
-	MMC1_REG(SD_STAT) |= SD_STAT_CC;
-	MMC1_REG(SD_CON) &= ~SD_CON_INIT;
-
-	/* Clear the SD_STAT register */
-	MMC1_REG(SD_STAT) = 0xFFFFFFFF;
-
-	/* Enable open-drain mode until we enter Stand-by State as illustrated in the
-	   JEDEC JESD84-A43 Embedded MultiMediaCard Product Standard specification, Table 5 */
-	MMC1_REG(SD_CON) |= SD_CON_OD;
-
-	/* Send CMD0/GO_IDLE_STATE to reset the eMMC on MMC1 interface */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Send CMD1 and poll busy bit in response */
-	do {
-		arg = 0x40FF8000;
-		cmd = SD_CMD_CMD1_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_R3;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while (!(MMC1_REG(SD_RSP10) & 0x80000000));
-
-	/* Send CMD2, i.e. ALL_SEND_CID */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Set RCA of eMMC */
-	mmcrca = 0x3A3A;
-
-	/* Send CMD3 to set the relative card address (RCA) of the eMMC */
-	arg = (mmcrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD3_SET_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the eMMC to enter Stand-by State */
-	do {
-		/* Send CMD13 to get the status of the MMC */
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	/* Disable open-drain mode */
-	MMC1_REG(SD_CON) &= ~SD_CON_OD;
-
-	/* Send CMD7 to put the eMMC into Transfer State */
-	arg = (mmcrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for eMMC to enter Transfer State */
-	do {
-		/* Send CMD13 to get the status of the eMMC */
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-
-	/* Send CMD6 to change bus-width to 8-bits */
-	arg = (3 << 24) | (183 << 16) | (2 << 8);
-	cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-	while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
-	do {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-
-	/* Configure the MMC1 controller to use an 8-bit data width */
-	MMC1_REG(SD_CON) |= SD_CON_DW8_8BIT;
-
-	/* Send CMD6 to change to high-speed mode */
-	arg = 0x03B90100;
-	cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-	while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
-	do {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-
-	/* Change the clock frequency to 48 MHz and set the DTO to the maximum value setting */
-	MMC1_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
-	MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
-	MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (2 << 6);
-
-	/* Wait for clock to stabilize */
-	while ((MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
-
-	/* Put the eMMC into Stand-by State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the eMMC to enter Stand-by State */
-	do {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	return(0);
+    uint32_t cmd, arg, resp[4];
+
+    /* Reset the MMC1 Controller */
+    MMC1_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
+    while(!(MMC1_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
+
+    /* Reset the command and data lines */
+    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
+    while(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
+
+    /* Configure the MMC1 controller capabilities to enable 3.0 V operating voltage */
+    MMC1_REG(SD_CAPA) |= SD_CAPA_VS30;
+
+    /* Configure SD_IE register to update certain status bits in SD_STAT */
+    MMC1_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
+                      SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
+                      SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
+                      SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
+                      SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
+
+    /* Configure the operating voltage to 3.0 V */
+    MMC1_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
+    MMC1_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
+
+    /* Turn on the bus */
+    MMC1_REG(SD_HCTL) |= SD_HCTL_SDBP;
+    while(!(MMC1_REG(SD_HCTL) & SD_HCTL_SDBP));
+
+    /* Enable the internal clock */
+    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
+
+    /* Configure Clock Frequency Select to 100 KHz */
+    MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (960 << 6);
+
+    /* Wait for clock to stabilize */
+    while(!(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
+
+    /* Configure SD_SYSCONFIG */
+    MMC1_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
+    MMC1_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
+                              SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
+
+    /* Enable the clock to the eMMC */
+    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_CEN;
+
+    /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
+       "Card Detection, Identification, and Selection" */
+    MMC1_REG(SD_CON) |= SD_CON_INIT;
+    /* Clear the SD_STAT register */
+    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
+    MMC1_REG(SD_ARG) = 0x00000000;
+    MMC1_REG(SD_CMD) = 0x00000000;
+    while(!(MMC1_REG(SD_STAT) & SD_STAT_CC));
+    /* Clear CC flag in SD_STAT */
+    MMC1_REG(SD_STAT) |= SD_STAT_CC;
+    MMC1_REG(SD_CON) &= ~SD_CON_INIT;
+
+    /* Clear the SD_STAT register */
+    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
+
+    /* Enable open-drain mode until we enter Stand-by State as illustrated in the
+       JEDEC JESD84-A43 Embedded MultiMediaCard Product Standard specification, Table 5 */
+    MMC1_REG(SD_CON) |= SD_CON_OD;
+
+    /* Send CMD0/GO_IDLE_STATE to reset the eMMC on MMC1 interface */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Send CMD1 and poll busy bit in response */
+    do {
+        arg = 0x40FF8000;
+        cmd = SD_CMD_CMD1_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_R3;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while(!(MMC1_REG(SD_RSP10) & 0x80000000));
+
+    /* Send CMD2, i.e. ALL_SEND_CID */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Set RCA of eMMC */
+    mmcrca = 0x3A3A;
+
+    /* Send CMD3 to set the relative card address (RCA) of the eMMC */
+    arg = (mmcrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD3_SET_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the eMMC to enter Stand-by State */
+    do {
+        /* Send CMD13 to get the status of the MMC */
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    /* Disable open-drain mode */
+    MMC1_REG(SD_CON) &= ~SD_CON_OD;
+
+    /* Send CMD7 to put the eMMC into Transfer State */
+    arg = (mmcrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for eMMC to enter Transfer State */
+    do {
+        /* Send CMD13 to get the status of the eMMC */
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+
+    /* Send CMD6 to change bus-width to 8-bits */
+    arg = (3 << 24) | (183 << 16) | (2 << 8);
+    cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+    while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
+    do {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+
+    /* Configure the MMC1 controller to use an 8-bit data width */
+    MMC1_REG(SD_CON) |= SD_CON_DW8_8BIT;
+
+    /* Send CMD6 to change to high-speed mode */
+    arg = 0x03B90100;
+    cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+    while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
+    do {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+
+    /* Change the clock frequency to 48 MHz and set the DTO to the maximum value setting */
+    MMC1_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
+    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
+    MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (2 << 6);
+
+    /* Wait for clock to stabilize */
+    while((MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
+
+    /* Put the eMMC into Stand-by State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the eMMC to enter Stand-by State */
+    do {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    return(0);
 }
 
 int
 mmcRead(int interface, char *buf, int blknum, int blkcnt)
 {
-	uint32_t cmd, arg, resp[4];
-	uint32_t *wordptr = (uint32_t *) buf;
-	int byteindex;
-
-	/* Get the SD card's status via CMD13 */
-	arg = (mmcrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Ensure that the card is in Transfer State before proceeding */
-	if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
-			SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-			SD_CMD_RSP_TYPE_R1B;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-
-		/* Wait for the SD card to enter Transfer State */
-		do {
-			arg = (mmcrca << 16) & 0xFFFF0000;
-			cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
-				SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-				SD_CMD_RSP_TYPE_R1;
-			if (mmccmd(cmd, arg, resp) == -1)
-				return(-1);
-		} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-	}
-
-	/* Set the block length and the number of blocks to read */
-	MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
-	/* Read multiple blocks via CMD18 */
-	arg = blknum;
-	cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
-		SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Check the data buffer to see if there is data to be read */
-	do {
-		while (!(MMC1_REG(SD_STAT) & SD_STAT_BRR));
-
-		/* Clear the BRR status bit in SD_STAT */
-		MMC1_REG(SD_STAT) |= SD_STAT_BRR;
-
-		for (byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
-			*wordptr = MMC1_REG(SD_DATA);
-			wordptr++;
-		}
-	} while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Put the eMMC into Stand-by State */
-	arg = 0;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the eMMC to enter Stand-by State */
-	do {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	return(0);
+    uint32_t cmd, arg, resp[4];
+    uint32_t *wordptr = (uint32_t *) buf;
+    int byteindex;
+
+    /* Get the SD card's status via CMD13 */
+    arg = (mmcrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Ensure that the card is in Transfer State before proceeding */
+    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
+              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+              SD_CMD_RSP_TYPE_R1B;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+
+        /* Wait for the SD card to enter Transfer State */
+        do {
+            arg = (mmcrca << 16) & 0xFFFF0000;
+            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
+                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+                  SD_CMD_RSP_TYPE_R1;
+            if(mmccmd(cmd, arg, resp) == -1) {
+                return(-1);
+            }
+        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+    }
+
+    /* Set the block length and the number of blocks to read */
+    MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
+    /* Read multiple blocks via CMD18 */
+    arg = blknum;
+    cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
+          SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Check the data buffer to see if there is data to be read */
+    do {
+        while(!(MMC1_REG(SD_STAT) & SD_STAT_BRR));
+
+        /* Clear the BRR status bit in SD_STAT */
+        MMC1_REG(SD_STAT) |= SD_STAT_BRR;
+
+        for(byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
+            *wordptr = MMC1_REG(SD_DATA);
+            wordptr++;
+        }
+    } while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Put the eMMC into Stand-by State */
+    arg = 0;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the eMMC to enter Stand-by State */
+    do {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    return(0);
 }
 
 int
 mmcWrite(int interface, char *buf, int blknum, int blkcnt)
 {
-	uint32_t cmd, arg, resp[4];
-	uint32_t *wordptr = (uint32_t *) buf;
-	int byteindex;
-
-	/* Get the eMMC status by sending CMD13 */
-	arg = (mmcrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Ensure that the eMMC is in the Transfer State before proceeding */
-	if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
-			SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-			SD_CMD_RSP_TYPE_R1B;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-
-		/* Wait for eMMC to enter Transfer State */
-		do {
-			arg = (mmcrca << 16) & 0xFFFF0000;
-			cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
-				SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-				SD_CMD_RSP_TYPE_R1;
-			if (mmccmd(cmd, arg, resp) == -1)
-				return(-1);
-		} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-	}
-
-	/* Set the block length in bytes and the number of blocks to write to the SD card */
-	MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
-	/* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
-	 * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
-	 */
-	arg = blknum;
-	cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
-		SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Write the data */
-	do {
-		/* Wait until data is ready to be written */
-		while (!(MMC1_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
-
-		if (MMC1_REG(SD_STAT) & SD_STAT_TC)
-			break;
-
-		/* Clear the BWR status bit in SD_STAT */
-		MMC1_REG(SD_STAT) |= SD_STAT_BWR;
-
-		for (byteindex = 0; byteindex < (0x200 / 4); byteindex++)
-			MMC1_REG(SD_DATA) = *wordptr++;
-	} while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Put the eMMC into Stand-by State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (mmccmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for eMMC to enter Stand-by State */
-	do {
-		arg = (mmcrca << 16) & 0xFFFF0000;
-		cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (mmccmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	return(0);
+    uint32_t cmd, arg, resp[4];
+    uint32_t *wordptr = (uint32_t *) buf;
+    int byteindex;
+
+    /* Get the eMMC status by sending CMD13 */
+    arg = (mmcrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Ensure that the eMMC is in the Transfer State before proceeding */
+    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
+               SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+               SD_CMD_RSP_TYPE_R1B;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+
+        /* Wait for eMMC to enter Transfer State */
+        do {
+            arg = (mmcrca << 16) & 0xFFFF0000;
+            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
+                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+                  SD_CMD_RSP_TYPE_R1;
+            if(mmccmd(cmd, arg, resp) == -1) {
+                return(-1);
+            }
+        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+    }
+
+    /* Set the block length in bytes and the number of blocks to write to the SD card */
+    MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
+    /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
+     * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
+     */
+    arg = blknum;
+    cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
+          SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Write the data */
+    do {
+        /* Wait until data is ready to be written */
+        while(!(MMC1_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
+
+        if(MMC1_REG(SD_STAT) & SD_STAT_TC) {
+            break;
+        }
+
+        /* Clear the BWR status bit in SD_STAT */
+        MMC1_REG(SD_STAT) |= SD_STAT_BWR;
+
+        for(byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
+            MMC1_REG(SD_DATA) = *wordptr++;
+        }
+    } while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Put the eMMC into Stand-by State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(mmccmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for eMMC to enter Stand-by State */
+    do {
+        arg = (mmcrca << 16) & 0xFFFF0000;
+        cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+               SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(mmccmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    return(0);
 }
 
 int
 mmcInstalled(int interface)
 {
-	return(1);
+    return(1);
 }
diff --git a/ports/beagleboneblack/am335x_sd.c b/ports/beagleboneblack/am335x_sd.c
index 7eb0180..7d844b4 100644
--- a/ports/beagleboneblack/am335x_sd.c
+++ b/ports/beagleboneblack/am335x_sd.c
@@ -15,405 +15,435 @@ uint16_t sdrca;
 int
 sdcmd(uint32_t cmd, uint32_t arg, uint32_t resp[4])
 {
-	/* Clear the SD_STAT register for proper update of status bits after CMD invocation */
-	MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
-
-	MMCHS0_REG(SD_ARG) = arg;
-	MMCHS0_REG(SD_CMD) = cmd;
-
-	/* CMDx complete? */
-	while (!(MMCHS0_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
-
-	resp[0] = MMCHS0_REG(SD_RSP10);
-	resp[1] = MMCHS0_REG(SD_RSP32);
-	resp[2] = MMCHS0_REG(SD_RSP54);
-	resp[3] = MMCHS0_REG(SD_RSP76);
-
-	/* CMDx error? */
-	if (MMCHS0_REG(SD_STAT) & SD_STAT_ERRI)
-		return(-1);
-	else
-		return(0);
+    /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
+    MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
+
+    MMCHS0_REG(SD_ARG) = arg;
+    MMCHS0_REG(SD_CMD) = cmd;
+
+    /* CMDx complete? */
+    while(!(MMCHS0_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
+
+    resp[0] = MMCHS0_REG(SD_RSP10);
+    resp[1] = MMCHS0_REG(SD_RSP32);
+    resp[2] = MMCHS0_REG(SD_RSP54);
+    resp[3] = MMCHS0_REG(SD_RSP76);
+
+    /* CMDx error? */
+    if(MMCHS0_REG(SD_STAT) & SD_STAT_ERRI) {
+        return(-1);
+    } else {
+        return(0);
+    }
 }
 
 int
 sdCardCmd(int interface, int cmd, unsigned long arg, unsigned char *resp)
 {
-	return(-1);
+    return(-1);
 }
 
 int
 sdInit(int interface, int verbosity)
 {
-	uint32_t cmd, arg, resp[4];
-
-	/* Reset the MMC/SD controller */
-	MMCHS0_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
-	while (!(MMCHS0_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
-
-	/* Reset the command and data lines */
-	MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
-	while (MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
-
-	/* Configure the MMC/SD controller capabilities to enable 3.0 V operating voltage */
-	MMCHS0_REG(SD_CAPA) = SD_CAPA_VS30;
-
-	/* Configure SD_IE register to update certain status bits in SD_STAT */
-	MMCHS0_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
-		SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
-		SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
-		SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
-		SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
-
-	/* Disable open-drain mode (only used for MMC cards) and 8-bit data width  */
-	MMCHS0_REG(SD_CON) &= ~(SD_CON_OD | SD_CON_DW8);
-
-	/* Configure the operating voltage to 3.0 V */
-	MMCHS0_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
-	MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
-
-	/* Set the data width to 4-bits */
-	MMCHS0_REG(SD_HCTL) |= SD_HCTL_DTW;
-
-	/* Turn on the bus */
-	MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDBP;
-	while (!(MMCHS0_REG(SD_HCTL) & SD_HCTL_SDBP));
-
-	/* Enable the internal clock */
-	MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
-
-	/* Configure Clock Frequency Select to 100 KHz */
-	MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~(SD_SYSCTL_CLKD)) | (960 << 6);
-
-	/* Wait for clock to stabilize */
-	while (!(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
-
-	/* Configure SD_SYSCONFIG */
-	MMCHS0_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
-	MMCHS0_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
-		SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
-
-	/* Enable the clock to the SD card */
-	MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_CEN_ENABLE;
-
-	/* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
-	   "Card Detection, Identicication, and Selection" */
-	MMCHS0_REG(SD_CON) |= SD_CON_INIT;
-	/* Clear the SD_STAT register */
-	MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
-	MMCHS0_REG(SD_ARG) = 0x00000000;
-	MMCHS0_REG(SD_CMD) = 0x00000000;
-	while (!(MMCHS0_REG(SD_STAT) & SD_STAT_CC));
-	/* Clear CC flag in SD_STAT */
-	MMCHS0_REG(SD_STAT) |= SD_STAT_CC;
-	MMCHS0_REG(SD_CON) &= ~SD_CON_INIT;
-
-	/* Change the clock frequency to 6 MHz and set the DTO to the maximum value setting */
-	MMCHS0_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
-	MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
-	MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (16 << 6);
-
-	/* Wait for clock to stabilize */
-	while ((MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
-
-	/* Send CMD0/GO_IDLE_STATE to reset the SD card connected to MMC0 interface */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Send CMD8/SEND_IF_COND to verify that the SD card satisfies MMC/SD controller
-	   requirements */
-	arg = 0x00000188;
-	cmd = SD_CMD_CMD8_SEND_IF_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R7;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Determine what type of SD card is connected, i.e. standard capacity, high capacity, etc. 
-	 * We perform a CMD55/ACMD41 loop until the "Card power up status bit" is set in the OCR
-	 * register from the SD card to determine when we have a valid response */
-	do {
-		arg = 0x00000000;
-		cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-
-		arg = 0x40060000;
-		cmd = SD_CMD_ACMD41_SD_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL |
-			SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE |
-			SD_CMD_RSP_TYPE_R3;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while (!(resp[0] & SD_RSP10_R3_CARD_POWER_UP_STATUS));
-
-	/* Check SD_RSP10 to determine whether the card connected is high capacity or not */
-	if (resp[0] & SD_RSP10_R3_CARD_CAPACITY_STATUS)
-		sdInfoTbl[interface].highcapacity = 1;
-	else
-		sdInfoTbl[interface].highcapacity = 0;
-
-	/* Send CMD2 to get SD's CID and to put the card into Identification State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Send CMD3, i.e. request new relative address (RCA) and to put the card into
-	   Stand-by State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD3_SEND_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R6;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Save the RCA published from the SD card, this will be used in future CMDx commands */
-	sdrca = (MMCHS0_REG(SD_RSP10) >> 16) & 0xFFFF;
-
-	/* Wait for the SD card to enter Stand-by State */
-	do {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	/* Put the card with the RCA obtained previously into Transfer State via CMD7 */
-	arg = (sdrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the SD card to enter Transfer State */
-	do {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-
-	/* Set the bus-width to 4-bits */
-
-	/* Send CMD55 to get ready to configure the bus-width via ACMD6 */
-	arg = (sdrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Send ACMD6, SET_BUS_WIDTH to set the bus-width to 4-bits */
-	arg = 0x00000002;
-	cmd = SD_CMD_ACMD6_SET_BUS_WIDTH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Put the SD card into Stand-by State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the SD card to enter Stand-by State */
-	do {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	/* This point is reached when SD controller initialization and SD card
-	   communication is successful */
-	return(0);
+    uint32_t cmd, arg, resp[4];
+
+    /* Reset the MMC/SD controller */
+    MMCHS0_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
+    while(!(MMCHS0_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
+
+    /* Reset the command and data lines */
+    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
+    while(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
+
+    /* Configure the MMC/SD controller capabilities to enable 3.0 V operating voltage */
+    MMCHS0_REG(SD_CAPA) = SD_CAPA_VS30;
+
+    /* Configure SD_IE register to update certain status bits in SD_STAT */
+    MMCHS0_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
+                        SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
+                        SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
+                        SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
+                        SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
+
+    /* Disable open-drain mode (only used for MMC cards) and 8-bit data width  */
+    MMCHS0_REG(SD_CON) &= ~(SD_CON_OD | SD_CON_DW8);
+
+    /* Configure the operating voltage to 3.0 V */
+    MMCHS0_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
+    MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
+
+    /* Set the data width to 4-bits */
+    MMCHS0_REG(SD_HCTL) |= SD_HCTL_DTW;
+
+    /* Turn on the bus */
+    MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDBP;
+    while(!(MMCHS0_REG(SD_HCTL) & SD_HCTL_SDBP));
+
+    /* Enable the internal clock */
+    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
+
+    /* Configure Clock Frequency Select to 100 KHz */
+    MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~(SD_SYSCTL_CLKD)) | (960 << 6);
+
+    /* Wait for clock to stabilize */
+    while(!(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
+
+    /* Configure SD_SYSCONFIG */
+    MMCHS0_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
+    MMCHS0_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
+                                SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
+
+    /* Enable the clock to the SD card */
+    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_CEN_ENABLE;
+
+    /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
+       "Card Detection, Identicication, and Selection" */
+    MMCHS0_REG(SD_CON) |= SD_CON_INIT;
+    /* Clear the SD_STAT register */
+    MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
+    MMCHS0_REG(SD_ARG) = 0x00000000;
+    MMCHS0_REG(SD_CMD) = 0x00000000;
+    while(!(MMCHS0_REG(SD_STAT) & SD_STAT_CC));
+    /* Clear CC flag in SD_STAT */
+    MMCHS0_REG(SD_STAT) |= SD_STAT_CC;
+    MMCHS0_REG(SD_CON) &= ~SD_CON_INIT;
+
+    /* Change the clock frequency to 6 MHz and set the DTO to the maximum value setting */
+    MMCHS0_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
+    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
+    MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (16 << 6);
+
+    /* Wait for clock to stabilize */
+    while((MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
+
+    /* Send CMD0/GO_IDLE_STATE to reset the SD card connected to MMC0 interface */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Send CMD8/SEND_IF_COND to verify that the SD card satisfies MMC/SD controller
+       requirements */
+    arg = 0x00000188;
+    cmd = SD_CMD_CMD8_SEND_IF_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R7;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Determine what type of SD card is connected, i.e. standard capacity, high capacity, etc.
+     * We perform a CMD55/ACMD41 loop until the "Card power up status bit" is set in the OCR
+     * register from the SD card to determine when we have a valid response */
+    do {
+        arg = 0x00000000;
+        cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+
+        arg = 0x40060000;
+        cmd = SD_CMD_ACMD41_SD_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL |
+              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE |
+              SD_CMD_RSP_TYPE_R3;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while(!(resp[0] & SD_RSP10_R3_CARD_POWER_UP_STATUS));
+
+    /* Check SD_RSP10 to determine whether the card connected is high capacity or not */
+    if(resp[0] & SD_RSP10_R3_CARD_CAPACITY_STATUS) {
+        sdInfoTbl[interface].highcapacity = 1;
+    } else {
+        sdInfoTbl[interface].highcapacity = 0;
+    }
+
+    /* Send CMD2 to get SD's CID and to put the card into Identification State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Send CMD3, i.e. request new relative address (RCA) and to put the card into
+       Stand-by State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD3_SEND_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R6;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Save the RCA published from the SD card, this will be used in future CMDx commands */
+    sdrca = (MMCHS0_REG(SD_RSP10) >> 16) & 0xFFFF;
+
+    /* Wait for the SD card to enter Stand-by State */
+    do {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    /* Put the card with the RCA obtained previously into Transfer State via CMD7 */
+    arg = (sdrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the SD card to enter Transfer State */
+    do {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+
+    /* Set the bus-width to 4-bits */
+
+    /* Send CMD55 to get ready to configure the bus-width via ACMD6 */
+    arg = (sdrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Send ACMD6, SET_BUS_WIDTH to set the bus-width to 4-bits */
+    arg = 0x00000002;
+    cmd = SD_CMD_ACMD6_SET_BUS_WIDTH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Put the SD card into Stand-by State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the SD card to enter Stand-by State */
+    do {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    /* This point is reached when SD controller initialization and SD card
+       communication is successful */
+    return(0);
 }
 
 int
 sdRead(int interface, char *buf, int blknum, int blkcount)
 {
-	uint32_t cmd, arg, resp[4];
-	uint32_t *wordptr = (uint32_t *) buf;
-	int byteindex;
-
-	/* Get the SD card's status via CMD13 */
-	arg = (sdrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Ensure that the card is in Transfer State before proceeding */
-	if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
-			SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-			SD_CMD_RSP_TYPE_R1B;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-
-		/* Wait for the SD card to enter Transfer State */
-		do {
-			arg = (sdrca << 16) & 0xFFFF0000;
-			cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
-				SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-				SD_CMD_RSP_TYPE_R1;
-			if (sdcmd(cmd, arg, resp) == -1)
-				return(-1);
-		} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-	}
-
-	/* Set the block length and the number of blocks to read */
-	MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
-	/* Send CMD18, i.e. read multiple blocks */
-	arg = blknum;
-	cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
-		SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Check the data buffer to see if there is data to be read */
-	do {
-		while (!(MMCHS0_REG(SD_STAT) & SD_STAT_BRR));
-
-		/* Clear the BRR status bit in SD_STAT */
-		MMCHS0_REG(SD_STAT) |= SD_STAT_BRR;
-
-		for (byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
-			*wordptr = (MMCHS0_REG(SD_DATA));
-			wordptr++;
-		}
-	} while (!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Put the SD card into Stand-by State */
-	arg = 0;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for the SD card to enter Stand-by State */
-	do {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	return(0);
+    uint32_t cmd, arg, resp[4];
+    uint32_t *wordptr = (uint32_t *) buf;
+    int byteindex;
+
+    /* Get the SD card's status via CMD13 */
+    arg = (sdrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Ensure that the card is in Transfer State before proceeding */
+    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
+              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+              SD_CMD_RSP_TYPE_R1B;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+
+        /* Wait for the SD card to enter Transfer State */
+        do {
+            arg = (sdrca << 16) & 0xFFFF0000;
+            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
+                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+                  SD_CMD_RSP_TYPE_R1;
+            if(sdcmd(cmd, arg, resp) == -1) {
+                return(-1);
+            }
+        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+    }
+
+    /* Set the block length and the number of blocks to read */
+    MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
+    /* Send CMD18, i.e. read multiple blocks */
+    arg = blknum;
+    cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
+          SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Check the data buffer to see if there is data to be read */
+    do {
+        while(!(MMCHS0_REG(SD_STAT) & SD_STAT_BRR));
+
+        /* Clear the BRR status bit in SD_STAT */
+        MMCHS0_REG(SD_STAT) |= SD_STAT_BRR;
+
+        for(byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
+            *wordptr = (MMCHS0_REG(SD_DATA));
+            wordptr++;
+        }
+    } while(!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Put the SD card into Stand-by State */
+    arg = 0;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for the SD card to enter Stand-by State */
+    do {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    return(0);
 }
 
 int
 sdWrite(int interface, char *buf, int blknum, int blkcount)
 {
-	uint32_t cmd, arg, resp[4];
-	uint32_t *wordptr = (uint32_t *) buf;
-	int byteindex;
-
-	/* Get the SD card's status by sending CMD13 */
-	arg = (sdrca << 16) & 0xFFFF0000;
-	cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Ensure that the card is in the Transfer State before proceeding */
-	if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
-		arg = (sdrca << 16) & 0xFFFF0000;
-		cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
-			SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-			SD_CMD_RSP_TYPE_R1B;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-
-		/* Wait for SD card to enter Transfer State */
-		do {
-			arg = (sdrca << 16) & 0xFFFF0000;
-			cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
-				SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
-				SD_CMD_RSP_TYPE_R1;
-			if (sdcmd(cmd, arg, resp) == -1)
-				return(-1);
-		} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
-	}
-
-	/* Set the block length in bytes and the number of blocks to write to the SD card */
-	MMCHS0_REG(SD_BLK) = SD_BLKSIZE | ( blkcount << 16);
-	/* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
-	 * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
-	 */
-	arg = blknum;
-	cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
-		SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Write the data */
-	do {
-		/* Wait until data is ready to be written */
-		while (!(MMCHS0_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
-
-		if (MMCHS0_REG(SD_STAT) & SD_STAT_TC)
-			break;
-
-		/* Clear the BWR status bit in SD_STAT */
-		MMCHS0_REG(SD_STAT) |= SD_STAT_BWR;
-
-		for (byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++)
-			MMCHS0_REG(SD_DATA) = *wordptr++;
-	} while (!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
-
-	/* Put the SD card into Stand-by State */
-	arg = 0x00000000;
-	cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-		SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
-	if (sdcmd(cmd, arg, resp) == -1)
-		return(-1);
-
-	/* Wait for SD card to enter Stand-by State */
-	do {
-		arg= (sdrca << 16) & 0xFFFF0000;
-		cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
-			SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
-		if (sdcmd(cmd, arg, resp) == -1)
-			return(-1);
-	} while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
-
-	return(0);
+    uint32_t cmd, arg, resp[4];
+    uint32_t *wordptr = (uint32_t *) buf;
+    int byteindex;
+
+    /* Get the SD card's status by sending CMD13 */
+    arg = (sdrca << 16) & 0xFFFF0000;
+    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Ensure that the card is in the Transfer State before proceeding */
+    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
+        arg = (sdrca << 16) & 0xFFFF0000;
+        cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
+               SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+               SD_CMD_RSP_TYPE_R1B;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+
+        /* Wait for SD card to enter Transfer State */
+        do {
+            arg = (sdrca << 16) & 0xFFFF0000;
+            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
+                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
+                  SD_CMD_RSP_TYPE_R1;
+            if(sdcmd(cmd, arg, resp) == -1) {
+                return(-1);
+            }
+        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
+    }
+
+    /* Set the block length in bytes and the number of blocks to write to the SD card */
+    MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
+    /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
+     * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
+     */
+    arg = blknum;
+    cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
+          SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Write the data */
+    do {
+        /* Wait until data is ready to be written */
+        while(!(MMCHS0_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
+
+        if(MMCHS0_REG(SD_STAT) & SD_STAT_TC) {
+            break;
+        }
+
+        /* Clear the BWR status bit in SD_STAT */
+        MMCHS0_REG(SD_STAT) |= SD_STAT_BWR;
+
+        for(byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
+            MMCHS0_REG(SD_DATA) = *wordptr++;
+        }
+    } while(!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
+
+    /* Put the SD card into Stand-by State */
+    arg = 0x00000000;
+    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
+    if(sdcmd(cmd, arg, resp) == -1) {
+        return(-1);
+    }
+
+    /* Wait for SD card to enter Stand-by State */
+    do {
+        arg= (sdrca << 16) & 0xFFFF0000;
+        cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
+               SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
+        if(sdcmd(cmd, arg, resp) == -1) {
+            return(-1);
+        }
+    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
+
+    return(0);
 }
 
 int
 sdInstalled(int interface)
 {
-	if ((MMCHS0_REG(SD_CON) & SD_CON_CDP) == SD_CON_CDP_ACTIVE_HIGH)
-		if (MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS)
-			return(1);
-		else
-			return(0);
-	else
-		if (MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS)
-			return(0);
-		else
-			return(1);
+    if((MMCHS0_REG(SD_CON) & SD_CON_CDP) == SD_CON_CDP_ACTIVE_HIGH)
+        if(MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS) {
+            return(1);
+        } else {
+            return(0);
+        }
+    else if(MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS) {
+        return(0);
+    } else {
+        return(1);
+    }
 }
 
 int
 sdPowerup(int tot)
 {
-	return(-1);
+    return(-1);
 }
 
 int
 sdReadCxD(int interface, unsigned char *buf, int cmd)
 {
-	return(-1);
+    return(-1);
 }
diff --git a/ports/beagleboneblack/config.h b/ports/beagleboneblack/config.h
index 761e120..1475a8e 100644
--- a/ports/beagleboneblack/config.h
+++ b/ports/beagleboneblack/config.h
@@ -29,19 +29,19 @@
 //#define CONSOLE_UART_BASE (OMAP35XX_L4_IO_BASE+0x6C000)
 #define CONSOLE_UART_BASE UART0_BASE
 
-#define SIO_STEP 4
-#define IEN_DEFAULT 0x40
-#define MCTL_DEFAULT 0x01
+#define SIO_STEP                4
+#define IEN_DEFAULT             0x40
+#define MCTL_DEFAULT            0x01
 
-#define TIMER_TICKS_PER_MSEC	545000
+#define TIMER_TICKS_PER_MSEC    545000
 
 /* DEFAULT_ETHERADD & DEFAULT_IPADD:
  * Refer to notes in ethernet.c function EthernetStartup() for details
  * regarding the use of these definitions.
  * DEFAULT_IPADD could be set to "DHCP" or "BOOTP" as well.
  */
-#define	DEFAULT_ETHERADD "00:30:23:40:00:"  	// Cogent Block
-#define DEFAULT_IPADD    "192.168.254.110"		
+#define DEFAULT_ETHERADD "00:30:23:40:00:"      // Cogent Block
+#define DEFAULT_IPADD    "192.168.254.110"
 
 #define CPU_LE
 
@@ -49,9 +49,9 @@
 // prints out the startup banner...
 // If this is defined, then the output similar to the following will
 // be printed just above the uMon header...
-//		Silicon ID: 1.0
-//		CPU Rev: 2, Variant: 1
-//		CM Rev: 1.0, PRM Rev: 1.0
+//      Silicon ID: 1.0
+//      CPU Rev: 2, Variant: 1
+//      CM Rev: 1.0, PRM Rev: 1.0
 // #define USR_HEADER_FUNC show_revision
 
 /* Defining DONT_CENTER_MONHEADER eliminates the automatic centering
@@ -63,47 +63,47 @@
  *  Number of transmit and receive buffers allocated to ethernet.
  *  The total of XBUFCNT+RBUFCNT should not exceed MAXEBDS
  */
-#define XBUFCNT 	8
-#define RBUFCNT 	8
-#define XBUFSIZE	2048
-#define RBUFSIZE	2048
+#define XBUFCNT     8
+#define RBUFCNT     8
+#define XBUFSIZE    2048
+#define RBUFSIZE    2048
 
 /* LOOPS_PER_SECOND:
  * Approximately the size of a loop that will cause a 1-second delay.
  * This can be guestimated or modified with the sleep -c command at the
  * monitor command line.
  */
-#define LOOPS_PER_SECOND    15000
+#define LOOPS_PER_SECOND        15000
 
-#define INCLUDE_NANDCMD			0
+#define INCLUDE_NANDCMD         0
 
 #if INCLUDE_NANDCMD
 /* Needed for NAND to work with TFSRAM:
  */
-#define NAND_TFS_BASE			0x10000		// base of TFS in NAND
-
-#define FLASHRAM_BASE			0x80300000
-#define FLASHRAM_END			0x8037ffff
-#define FLASHRAM_SECTORSIZE		0x00010000
-#define FLASHRAM_SPARESIZE		FLASHRAM_SECTORSIZE
-#define FLASHRAM_BANKNUM		1
-#define FLASHRAM_SECTORCOUNT	8
+#define NAND_TFS_BASE           0x10000     // base of TFS in NAND
+
+#define FLASHRAM_BASE           0x80300000
+#define FLASHRAM_END            0x8037ffff
+#define FLASHRAM_SECTORSIZE     0x00010000
+#define FLASHRAM_SPARESIZE      FLASHRAM_SECTORSIZE
+#define FLASHRAM_BANKNUM        1
+#define FLASHRAM_SECTORCOUNT    8
 #endif
 
 /* Flash bank configuration:
  */
 #ifdef FLASHRAM_BASE
-#define FLASHBANKS				2
+#define FLASHBANKS              2
 #else
-#define FLASHBANKS				1
+#define FLASHBANKS              1
 #endif
-#define SINGLE_FLASH_DEVICE 	1
-#define FLASH_COPY_TO_RAM 		1
-#define FLASH_BANK0_BASE_ADDR  	0x08000000
-#define FLASH_PROTECT_RANGE  	"0-2"
+#define SINGLE_FLASH_DEVICE     1
+#define FLASH_COPY_TO_RAM       1
+#define FLASH_BANK0_BASE_ADDR   0x08000000
+#define FLASH_PROTECT_RANGE     "0-2"
 #define FLASH_BANK0_WIDTH       2
 #define FLASH_LARGEST_SECTOR    0x20000
-#define FLASH_LOOP_TIMEOUT		10000000
+#define FLASH_LOOP_TIMEOUT      10000000
 #define BUFFERED_WRITE
 
 /* TFS definitions:
@@ -115,17 +115,17 @@
  *  TFSSECTORCOUNT: Number of eraseable sectors that TFS covers, not including
  *                  the TFSSPARE sector.
  */
-#define TFSSPARESIZE    		FLASH_LARGEST_SECTOR
-#define TFS_DEVTOT      		1
-#define TFSSTART        		(FLASH_BANK0_BASE_ADDR+0x060000)
-//#define TFSEND          		(FLASH_BANK0_BASE_ADDR+0x007dffff)	// 8MB Flash
-#define TFSEND          		(FLASH_BANK0_BASE_ADDR+0x00edffff)	// 16MB Flash
-//#define TFSEND          		(FLASH_BANK0_BASE_ADDR+0x03dfffff)	// 64MB Flash
-#define TFSSPARE        		(TFSEND+1)
-#define TFSSECTORCOUNT			((TFSSPARE-TFSSTART)/0x20000)
-#define TFS_EBIN_ELFMSBIN		1
-#define TFS_VERBOSE_STARTUP		1
-#define TFS_ALTDEVTBL_BASE		&alt_tfsdevtbl_base
+#define TFSSPARESIZE            FLASH_LARGEST_SECTOR
+#define TFS_DEVTOT              1
+#define TFSSTART                (FLASH_BANK0_BASE_ADDR+0x060000)
+//#define TFSEND                (FLASH_BANK0_BASE_ADDR+0x007dffff)  // 8MB Flash
+#define TFSEND                  (FLASH_BANK0_BASE_ADDR+0x00edffff)  // 16MB Flash
+//#define TFSEND                (FLASH_BANK0_BASE_ADDR+0x03dfffff)  // 64MB Flash
+#define TFSSPARE                (TFSEND+1)
+#define TFSSECTORCOUNT          ((TFSSPARE-TFSSTART)/0x20000)
+#define TFS_EBIN_ELFMSBIN       1
+#define TFS_VERBOSE_STARTUP     1
+#define TFS_ALTDEVTBL_BASE      &alt_tfsdevtbl_base
 
 /* Specify CPU/PLATFORM type and name so that common code can be used
  * for a similar cpu, on different platforms.
@@ -141,22 +141,22 @@
  * allocated to malloc in the monitor.  Note that this size can be dynamically
  * increased using the heap extension option in the heap command.
  */
-#define ALLOCSIZE	1024 	// (64*1024)
-#define MONSTACKSIZE	(16*1024)
+#define ALLOCSIZE           1024    // (64*1024)
+#define MONSTACKSIZE        (16*1024)
 
 
 /* Specify inclusion of subsystems within the monitor here.
  * Refer to comments in common/monitor/inc_check.h for details on
  * each of these macros.
  */
-						
-#define INCLUDE_MEMTRACE	0
+
+#define INCLUDE_MEMTRACE        0
 #define INCLUDE_MEMCMDS         1
 #define INCLUDE_EDIT            0
 #define INCLUDE_DISASSEMBLER    0
 #define INCLUDE_UNZIP           0
 #define INCLUDE_ETHERNET        0
-#define INCLUDE_ICMP		0
+#define INCLUDE_ICMP            0
 #define INCLUDE_TFTP            0
 #define INCLUDE_DHCPBOOT        0
 #define INCLUDE_TFS             0
@@ -176,22 +176,22 @@
 #define INCLUDE_PROFILER        0
 #define INCLUDE_BBC             0
 #define INCLUDE_STOREMAC        0
-#define INCLUDE_SHELLVARS	0
-#define INCLUDE_MALLOC		0
-#define INCLUDE_PORTCMD	        0
-#define INCLUDE_SYSLOG	        0
-#define INCLUDE_HWTMR	        0
+#define INCLUDE_SHELLVARS       0
+#define INCLUDE_MALLOC          0
+#define INCLUDE_PORTCMD         0
+#define INCLUDE_SYSLOG          0
+#define INCLUDE_HWTMR           0
 #define INCLUDE_VERBOSEHELP     0
-#define INCLUDE_GDB		0
-#define INCLUDE_USRLVL		0
-#define INCLUDE_JFFS2		0
-#define INCLUDE_JFFS2ZLIB	0
-#define INCLUDE_FBI		0
-#define INCLUDE_TSI		0
-#define INCLUDE_SD		1
-#define INCLUDE_DNS		0
-#define INCLUDE_BLINKLED	1
-#define TARGET_BLINKLED target_blinkled
+#define INCLUDE_GDB             0
+#define INCLUDE_USRLVL          0
+#define INCLUDE_JFFS2           0
+#define INCLUDE_JFFS2ZLIB       0
+#define INCLUDE_FBI             0
+#define INCLUDE_TSI             0
+#define INCLUDE_SD              1
+#define INCLUDE_DNS             0
+#define INCLUDE_BLINKLED        1
+#define TARGET_BLINKLED         target_blinkled
 
 /* Inclusion of this next file will make sure that all of the above
  * inclusions are legal; and warn/adjust where necessary.
diff --git a/ports/beagleboneblack/cpuio.c b/ports/beagleboneblack/cpuio.c
index a8a901d..22afb37 100644
--- a/ports/beagleboneblack/cpuio.c
+++ b/ports/beagleboneblack/cpuio.c
@@ -12,9 +12,9 @@
 int
 getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
 {
-	*lo = ((48000000/16)/baud) & 0x00ff;
-	*hi = (((48000000/16)/baud) & 0xff00) >> 8;
-	return(0);
+    *lo = ((48000000/16)/baud) & 0x00ff;
+    *hi = (((48000000/16)/baud) & 0xff00) >> 8;
+    return(0);
 }
 
 /* devInit():
@@ -24,7 +24,7 @@ getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
 int
 devInit(int baud)
 {
-        return(0);
+    return(0);
 }
 
 /* ConsoleBaudSet():
@@ -37,8 +37,8 @@ devInit(int baud)
 /*int
 ConsoleBaudSet(int baud)
 {
-	// ADD_CODE_HERE 
-	return(0);
+    // ADD_CODE_HERE
+    return(0);
 }*/
 
 /* target_console_empty():
@@ -51,9 +51,9 @@ ConsoleBaudSet(int baud)
 /*int
 target_console_empty(void)
 {
-	// if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
-		return(0);
-	return(1);
+    // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
+        return(0);
+    return(1);
 }*/
 
 /* intsoff():
@@ -63,10 +63,10 @@ target_console_empty(void)
 ulong
 intsoff(void)
 {
-	ulong status = 0;
+    ulong status = 0;
 
-	/* ADD_CODE_HERE */
-	return(status);
+    /* ADD_CODE_HERE */
+    return(status);
 }
 
 /* intsrestore():
@@ -76,7 +76,7 @@ intsoff(void)
 void
 intsrestore(ulong status)
 {
-	/* ADD_CODE_HERE */
+    /* ADD_CODE_HERE */
 }
 
 /* cacheInitForTarget():
@@ -93,7 +93,7 @@ intsrestore(ulong status)
 void
 cacheInitForTarget(void)
 {
-	/* ADD_CODE_HERE */
+    /* ADD_CODE_HERE */
 }
 
 /* target_reset():
@@ -105,11 +105,11 @@ cacheInitForTarget(void)
 void
 target_reset(void)
 {
-//	flushDcache(0,0);
-//	disableDcache();
-//	invalidateIcache(0,0);
-//	disableIcache();
-	monrestart(INITIALIZE);
+//  flushDcache(0,0);
+//  disableDcache();
+//  invalidateIcache(0,0);
+//  disableIcache();
+    monrestart(INITIALIZE);
 }
 
 /* Override the default exception handlers provided by the AM335x
@@ -118,454 +118,455 @@ target_reset(void)
 void
 ram_vector_install(void)
 {
-	extern unsigned long abort_data;
-	extern unsigned long abort_prefetch;
-	extern unsigned long undefined_instruction;
-	extern unsigned long software_interrupt;
-	extern unsigned long interrupt_request;
-	extern unsigned long fast_interrupt_request;
-	extern unsigned long not_assigned;
-
-	*(ulong **)0x4030ce24 = &undefined_instruction;
-	*(ulong **)0x4030ce28 = &software_interrupt;
-	*(ulong **)0x4030ce2c = &abort_prefetch;
-	*(ulong **)0x4030ce30 = &abort_data;
-	*(ulong **)0x4030ce34 = &not_assigned;
-	*(ulong **)0x4030ce38 = &interrupt_request;
-	*(ulong **)0x4030ce3c = &fast_interrupt_request;
+    extern unsigned long abort_data;
+    extern unsigned long abort_prefetch;
+    extern unsigned long undefined_instruction;
+    extern unsigned long software_interrupt;
+    extern unsigned long interrupt_request;
+    extern unsigned long fast_interrupt_request;
+    extern unsigned long not_assigned;
+
+    *(ulong **)0x4030ce24 = &undefined_instruction;
+    *(ulong **)0x4030ce28 = &software_interrupt;
+    *(ulong **)0x4030ce2c = &abort_prefetch;
+    *(ulong **)0x4030ce30 = &abort_data;
+    *(ulong **)0x4030ce34 = &not_assigned;
+    *(ulong **)0x4030ce38 = &interrupt_request;
+    *(ulong **)0x4030ce3c = &fast_interrupt_request;
 }
 
 void
 pinMuxInit(void)
 {
-	// Set pin mux configuration for UART0 RX/TX pins
-	CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
-		PULL_OFF | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
-		PULL_OFF | MUXMODE_0;
-
-	// Configure GPIO pins tied to four USR LEDS...
-	// GPIO1_21: USER0 LED (D2)
-	CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
-		PULL_OFF | MUXMODE_7;
-	// GPIO1_22: USER1 LED (D3)
-	CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
-		PULL_OFF | MUXMODE_7;
-	// GPIO1_23: USER2 LED (D4)
-	CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
-		PULL_OFF | MUXMODE_7;
-	// GPIO1_24: USER3 LED (D5)
-	CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
-		PULL_OFF | MUXMODE_7;
-
-	// Configure the pins for the MMC0 interface
-	CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
-		MUXMODE_0;
-	CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_0;
-	CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_5;
-
-	// Configure the pins for the MMC1 interface
-	/* MMC1_DAT0 */
-	CNTL_MODULE_REG(CONF_GPMC_AD0) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT1 */
-	CNTL_MODULE_REG(CONF_GPMC_AD1) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT2 */
-	CNTL_MODULE_REG(CONF_GPMC_AD2) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT3 */
-	CNTL_MODULE_REG(CONF_GPMC_AD3) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT4 */
-	CNTL_MODULE_REG(CONF_GPMC_AD4) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT5 */
-	CNTL_MODULE_REG(CONF_GPMC_AD5) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT6 */
-	CNTL_MODULE_REG(CONF_GPMC_AD6) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_DAT7 */
-	CNTL_MODULE_REG(CONF_GPMC_AD7) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_1;
-	/* MMC1_CLK */
-	CNTL_MODULE_REG(CONF_GPMC_CSN1) = RX_ON | PULL_OFF |
-		MUXMODE_2;
-	/* MMC1_CMD */
-	CNTL_MODULE_REG(CONF_GPMC_CSN2) = RX_ON | PULL_ON |
-		PULLUP | MUXMODE_2;
+    // Set pin mux configuration for UART0 RX/TX pins
+    CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
+                                      PULL_OFF | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
+                                      PULL_OFF | MUXMODE_0;
+
+    // Configure GPIO pins tied to four USR LEDS...
+    // GPIO1_21: USER0 LED (D2)
+    CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
+                                    PULL_OFF | MUXMODE_7;
+    // GPIO1_22: USER1 LED (D3)
+    CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
+                                    PULL_OFF | MUXMODE_7;
+    // GPIO1_23: USER2 LED (D4)
+    CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
+                                    PULL_OFF | MUXMODE_7;
+    // GPIO1_24: USER3 LED (D5)
+    CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
+                                    PULL_OFF | MUXMODE_7;
+
+    // Configure the pins for the MMC0 interface
+    CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
+                                      PULLUP | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
+                                      PULLUP | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
+                                      PULLUP | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
+                                      PULLUP | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
+                                     MUXMODE_0;
+    CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_0;
+    CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_5;
+
+    // Configure the pins for the MMC1 interface
+    /* MMC1_DAT0 */
+    CNTL_MODULE_REG(CONF_GPMC_AD0) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT1 */
+    CNTL_MODULE_REG(CONF_GPMC_AD1) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT2 */
+    CNTL_MODULE_REG(CONF_GPMC_AD2) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT3 */
+    CNTL_MODULE_REG(CONF_GPMC_AD3) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT4 */
+    CNTL_MODULE_REG(CONF_GPMC_AD4) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT5 */
+    CNTL_MODULE_REG(CONF_GPMC_AD5) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT6 */
+    CNTL_MODULE_REG(CONF_GPMC_AD6) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_DAT7 */
+    CNTL_MODULE_REG(CONF_GPMC_AD7) = RX_ON | PULL_ON |
+                                     PULLUP | MUXMODE_1;
+    /* MMC1_CLK */
+    CNTL_MODULE_REG(CONF_GPMC_CSN1) = RX_ON | PULL_OFF |
+                                      MUXMODE_2;
+    /* MMC1_CMD */
+    CNTL_MODULE_REG(CONF_GPMC_CSN2) = RX_ON | PULL_ON |
+                                      PULLUP | MUXMODE_2;
 }
 
 void
 InitGPIO1(void)
 {
-	// GPIO_CTRL: Enable GPIO1 module
-	GPIO1_REG(0x130) = 0;
+    // GPIO_CTRL: Enable GPIO1 module
+    GPIO1_REG(0x130) = 0;
 
-	// GPIO_OE: 25-24 are outputs...
-	GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
+    // GPIO_OE: 25-24 are outputs...
+    GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
 
-	// All LEDs off...
-	GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
+    // All LEDs off...
+    GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
 }
 
 /* If any CPU IO wasn't initialized in reset.S, do it here...
- * This just provides a "C-level" IO init opportunity. 
+ * This just provides a "C-level" IO init opportunity.
  */
 void
 initCPUio(void)
 {
-	ram_vector_install();
+    ram_vector_install();
 
-	// Enable the control module:
-	CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
+    // Enable the control module:
+    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
 
-	// Enable clock for UART0:
-	CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
+    // Enable clock for UART0:
+    CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
 
-	// Enable clock for GPIO1:
-	CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
+    // Enable clock for GPIO1:
+    CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
 
-	/* Enable MMC0 clocks */
-	CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
-	while (CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
+    /* Enable MMC0 clocks */
+    CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
+    while(CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
 
-	/* Enable MMC1 clocks */
-	CM_PER_REG(CM_PER_MMC1_CLKCTRL) |= CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE;
-	while (CM_PER_REG(CM_PER_MMC1_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
+    /* Enable MMC1 clocks */
+    CM_PER_REG(CM_PER_MMC1_CLKCTRL) |= CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE;
+    while(CM_PER_REG(CM_PER_MMC1_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
 
-	pinMuxInit();
+    pinMuxInit();
 
-	InitUART(DEFAULT_BAUD_RATE);
-	InitGPIO1();
+    InitUART(DEFAULT_BAUD_RATE);
+    InitGPIO1();
 
-	// Set UART0 mode to 16x
-	UART0_REG(UART_MDR1) &= ~7;
+    // Set UART0 mode to 16x
+    UART0_REG(UART_MDR1) &= ~7;
 }
 
 int
 led(int num, int on)
 {
-	unsigned long bit;
-
-	switch(num) {
-		case 0:	// D0
-			bit = USR0_LED;
-			break;
-		case 1:	// D1
-			bit = USR1_LED;
-			break;
-		case 2:	// D2
-			bit = USR2_LED;
-			break;
-		case 3:	// D3
-			bit = USR3_LED;
-			break;
-		default:
-			return(-1);
-	}
-
-	// GPIO21-24:
-	if (on)
-	    GPIO1_REG(0x13c) |= bit;
-	else
-	    GPIO1_REG(0x13c) &= ~bit;
-	return(0);
+    unsigned long bit;
+
+    switch(num) {
+    case 0: // D0
+        bit = USR0_LED;
+        break;
+    case 1: // D1
+        bit = USR1_LED;
+        break;
+    case 2: // D2
+        bit = USR2_LED;
+        break;
+    case 3: // D3
+        bit = USR3_LED;
+        break;
+    default:
+        return(-1);
+    }
+
+    // GPIO21-24:
+    if(on) {
+        GPIO1_REG(0x13c) |= bit;
+    } else {
+        GPIO1_REG(0x13c) &= ~bit;
+    }
+    return(0);
 }
 
 void
 target_blinkled(void)
 {
 #if INCLUDE_BLINKLED
-	static uint8_t ledstate;
-	static struct elapsed_tmr tmr;
+    static uint8_t ledstate;
+    static struct elapsed_tmr tmr;
 
-#define STATLED_ON()	led(0,1)
-#define STATLED_OFF()	led(0,0)
+#define STATLED_ON()    led(0,1)
+#define STATLED_OFF()   led(0,0)
 #ifndef BLINKON_MSEC
 #define BLINKON_MSEC 10000
 #define BLINKOFF_MSEC 10000
 #endif
 
-	switch(ledstate) {
-		case 0:
-			startElapsedTimer(&tmr,BLINKON_MSEC);
-			STATLED_ON();
-			ledstate = 1;
-			break;
-		case 1:
-			if(msecElapsed(&tmr)) {
-				STATLED_OFF();
-				ledstate = 2;
-				startElapsedTimer(&tmr,BLINKOFF_MSEC);
-			}
-			break;
-		case 2:
-			if(msecElapsed(&tmr)) {
-				STATLED_ON();
-				ledstate = 1;
-				startElapsedTimer(&tmr,BLINKON_MSEC);
-			}
-			break;
-	}
+    switch(ledstate) {
+    case 0:
+        startElapsedTimer(&tmr,BLINKON_MSEC);
+        STATLED_ON();
+        ledstate = 1;
+        break;
+    case 1:
+        if(msecElapsed(&tmr)) {
+            STATLED_OFF();
+            ledstate = 2;
+            startElapsedTimer(&tmr,BLINKOFF_MSEC);
+        }
+        break;
+    case 2:
+        if(msecElapsed(&tmr)) {
+            STATLED_ON();
+            ledstate = 1;
+            startElapsedTimer(&tmr,BLINKON_MSEC);
+        }
+        break;
+    }
 #endif
 }
 
 void
 mpu_pll_init(void)
 {
-	uint32_t cm_clkmode_dpll_mpu;
-	uint32_t cm_clksel_dpll_mpu;
-	uint32_t cm_div_m2_dpll_mpu;
-
-	// Put MPU PLL in MN Bypass mode
-	cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
-	cm_clkmode_dpll_mpu &= ~0x00000007;
-	cm_clkmode_dpll_mpu |= 0x00000004;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
-	// Wait for MPU PLL to enter MN Bypass mode
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
-
-	// Set the ARM core frequency to 1 GHz
-	cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
-	cm_clksel_dpll_mpu &= ~0x0007FF7F;
-	cm_clksel_dpll_mpu |= 1000 << 8;
-	cm_clksel_dpll_mpu |= 23;
-	CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
-	cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
-	cm_div_m2_dpll_mpu &= ~0x0000001F;
-	cm_div_m2_dpll_mpu |= 0x00000001;
-	CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
-
-	// Lock MPU PLL
-	cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
-	cm_clkmode_dpll_mpu &= ~0x00000007;
-	cm_clkmode_dpll_mpu |= 0x00000007;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
-	// Wait for MPU PLL to lock
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
+    uint32_t cm_clkmode_dpll_mpu;
+    uint32_t cm_clksel_dpll_mpu;
+    uint32_t cm_div_m2_dpll_mpu;
+
+    // Put MPU PLL in MN Bypass mode
+    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
+    cm_clkmode_dpll_mpu &= ~0x00000007;
+    cm_clkmode_dpll_mpu |= 0x00000004;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
+    // Wait for MPU PLL to enter MN Bypass mode
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
+
+    // Set the ARM core frequency to 1 GHz
+    cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
+    cm_clksel_dpll_mpu &= ~0x0007FF7F;
+    cm_clksel_dpll_mpu |= 1000 << 8;
+    cm_clksel_dpll_mpu |= 23;
+    CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
+    cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
+    cm_div_m2_dpll_mpu &= ~0x0000001F;
+    cm_div_m2_dpll_mpu |= 0x00000001;
+    CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
+
+    // Lock MPU PLL
+    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
+    cm_clkmode_dpll_mpu &= ~0x00000007;
+    cm_clkmode_dpll_mpu |= 0x00000007;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
+    // Wait for MPU PLL to lock
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
 }
 
 void
 core_pll_init(void)
 {
-	uint32_t cm_clkmode_dpll_core;
-	uint32_t cm_clksel_dpll_core;
-	uint32_t cm_div_m4_dpll_core;
-	uint32_t cm_div_m5_dpll_core;
-	uint32_t cm_div_m6_dpll_core;
-
-	// Put Core PLL in MN Bypass mode
-	cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
-	cm_clkmode_dpll_core &= ~0x00000007;
-	cm_clkmode_dpll_core |= 0x00000004;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
-	// Wait for Core PLL to enter MN Bypass mode
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
-
-	// Configure the multiplier and divider
-	cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
-	cm_clksel_dpll_core &= ~0x0007FF7F;
-	cm_clksel_dpll_core |= 1000 << 8;
-	cm_clksel_dpll_core |= 23;
-	CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
-	// Configure the M4, M5, and M6 dividers
-	cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
-	cm_div_m4_dpll_core &= ~0x0000001F;
-	cm_div_m4_dpll_core |= 10;
-	CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
-	cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
-	cm_div_m5_dpll_core &= ~0x0000001F;
-	cm_div_m5_dpll_core |= 8;
-	CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
-	cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
-	cm_div_m6_dpll_core &= ~0x0000001F;
-	cm_div_m6_dpll_core |= 4;
-	CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
-
-	// Lock Core PLL
-	cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
-	cm_clkmode_dpll_core &= ~0x00000007;
-	cm_clkmode_dpll_core |= 0x00000007;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
-	// Wait for Core PLL to lock
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
+    uint32_t cm_clkmode_dpll_core;
+    uint32_t cm_clksel_dpll_core;
+    uint32_t cm_div_m4_dpll_core;
+    uint32_t cm_div_m5_dpll_core;
+    uint32_t cm_div_m6_dpll_core;
+
+    // Put Core PLL in MN Bypass mode
+    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
+    cm_clkmode_dpll_core &= ~0x00000007;
+    cm_clkmode_dpll_core |= 0x00000004;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
+    // Wait for Core PLL to enter MN Bypass mode
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
+
+    // Configure the multiplier and divider
+    cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
+    cm_clksel_dpll_core &= ~0x0007FF7F;
+    cm_clksel_dpll_core |= 1000 << 8;
+    cm_clksel_dpll_core |= 23;
+    CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
+    // Configure the M4, M5, and M6 dividers
+    cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
+    cm_div_m4_dpll_core &= ~0x0000001F;
+    cm_div_m4_dpll_core |= 10;
+    CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
+    cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
+    cm_div_m5_dpll_core &= ~0x0000001F;
+    cm_div_m5_dpll_core |= 8;
+    CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
+    cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
+    cm_div_m6_dpll_core &= ~0x0000001F;
+    cm_div_m6_dpll_core |= 4;
+    CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
+
+    // Lock Core PLL
+    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
+    cm_clkmode_dpll_core &= ~0x00000007;
+    cm_clkmode_dpll_core |= 0x00000007;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
+    // Wait for Core PLL to lock
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
 }
 
 void
 ddr_pll_init(void)
 {
-	uint32_t cm_clkmode_dpll_ddr;
-	uint32_t cm_clksel_dpll_ddr;
-	uint32_t cm_div_m2_dpll_ddr;
-
-	// Put DDR PLL in MN Bypass mode
-	cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
-	cm_clkmode_dpll_ddr &= ~0x00000007;
-	cm_clkmode_dpll_ddr |= 0x00000004;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
-	// Wait for DDR PLL to enter MN Bypass mode
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
-
-	// Set the DDR frequency to 400 MHz
-	cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
-	cm_clksel_dpll_ddr &= ~0x0007FF7F;
-	cm_clksel_dpll_ddr |= 400 << 8;
-	cm_clksel_dpll_ddr |= 23;
-	CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
-	// Set M2 divider
-	cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
-	cm_div_m2_dpll_ddr &= ~0x0000001F;
-	cm_div_m2_dpll_ddr |= 1;
-	CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
-
-	// Lock the DDR PLL
-	cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
-	cm_clkmode_dpll_ddr &= ~0x00000007;
-	cm_clkmode_dpll_ddr |= 0x00000007;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
-	// Wait for DDR PLL to lock
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
+    uint32_t cm_clkmode_dpll_ddr;
+    uint32_t cm_clksel_dpll_ddr;
+    uint32_t cm_div_m2_dpll_ddr;
+
+    // Put DDR PLL in MN Bypass mode
+    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
+    cm_clkmode_dpll_ddr &= ~0x00000007;
+    cm_clkmode_dpll_ddr |= 0x00000004;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
+    // Wait for DDR PLL to enter MN Bypass mode
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
+
+    // Set the DDR frequency to 400 MHz
+    cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
+    cm_clksel_dpll_ddr &= ~0x0007FF7F;
+    cm_clksel_dpll_ddr |= 400 << 8;
+    cm_clksel_dpll_ddr |= 23;
+    CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
+    // Set M2 divider
+    cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
+    cm_div_m2_dpll_ddr &= ~0x0000001F;
+    cm_div_m2_dpll_ddr |= 1;
+    CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
+
+    // Lock the DDR PLL
+    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
+    cm_clkmode_dpll_ddr &= ~0x00000007;
+    cm_clkmode_dpll_ddr |= 0x00000007;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
+    // Wait for DDR PLL to lock
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
 }
 
 void
 per_pll_init(void)
 {
-	uint32_t cm_clkmode_dpll_per;
-	uint32_t cm_clksel_dpll_per;
-	uint32_t cm_div_m2_dpll_per;
-
-	// Put Per PLL in MN Bypass mode
-	cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
-	cm_clkmode_dpll_per &= ~0x00000007;
-	cm_clkmode_dpll_per |= 0x00000004;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
-	// Wait for Per PLL to enter MN Bypass mode
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
-
-	// Configure the multiplier and divider
-	cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
-	cm_clksel_dpll_per &= ~0xFF0FFFFF;
-	cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
-		CM_CLKSEL_DPLL_PER_DPLL_DIV;
-	CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
-	// Set M2 divider
-	cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
-	cm_div_m2_dpll_per &= ~0x0000007F;
-	cm_div_m2_dpll_per |= 5;
-	CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
-
-	// Lock the Per PLL
-	cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
-	cm_clkmode_dpll_per &= ~0x00000007;
-	cm_clkmode_dpll_per |= 0x00000007;
-	CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
-	// Wait for Per PLL to lock
-	while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
+    uint32_t cm_clkmode_dpll_per;
+    uint32_t cm_clksel_dpll_per;
+    uint32_t cm_div_m2_dpll_per;
+
+    // Put Per PLL in MN Bypass mode
+    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
+    cm_clkmode_dpll_per &= ~0x00000007;
+    cm_clkmode_dpll_per |= 0x00000004;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
+    // Wait for Per PLL to enter MN Bypass mode
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
+
+    // Configure the multiplier and divider
+    cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
+    cm_clksel_dpll_per &= ~0xFF0FFFFF;
+    cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
+                          CM_CLKSEL_DPLL_PER_DPLL_DIV;
+    CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
+    // Set M2 divider
+    cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
+    cm_div_m2_dpll_per &= ~0x0000007F;
+    cm_div_m2_dpll_per |= 5;
+    CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
+
+    // Lock the Per PLL
+    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
+    cm_clkmode_dpll_per &= ~0x00000007;
+    cm_clkmode_dpll_per |= 0x00000007;
+    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
+    // Wait for Per PLL to lock
+    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
 }
 
 void
 pll_init(void)
 {
-	mpu_pll_init();
-	core_pll_init();
-	ddr_pll_init();
-	per_pll_init();
+    mpu_pll_init();
+    core_pll_init();
+    ddr_pll_init();
+    per_pll_init();
 }
 
 void
 ddr_init(void)
 {
-	uint32_t reg;
-
-        // Enable the control module:
-        CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
-
-	// Enable EMIF module
-	reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
-	reg &= ~3;
-	reg |= 2;
-	CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
-	while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
-
-	// Configure VTP control
-	CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
-	CNTL_MODULE_REG(VTP_CTRL) &= ~1;
-	CNTL_MODULE_REG(VTP_CTRL) |= 1;
-	// Wait for VTP control to be ready
-	while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
-
-	// Configure the DDR PHY CMDx/DATAx registers
-	DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
-	DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
-	DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
-	DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
-	DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
-	DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
-
-	DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
-	DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
-	DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
-	DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
-
-	DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
-	DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
-	DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
-	DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
-
-	CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
-	CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
-	CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
-	CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
-	CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
-
-	CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
-
-	CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
-
-	// Enable dynamic power down when no read is being performed and set read latency
-	// to CAS Latency + 2 - 1
-	EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
-	EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
-
-	// Configure the AC timing characteristics
-	EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
-	EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
-	EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
-	EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
-	EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
-	EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
-
-	// Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
-	EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
-	// set the referesh rate shadow register to the same value as previous
-	EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
-
-	// Configure the ZQ Calibration
-	EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
-
-	// Configure the SDRAM characteristics
-	reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
-		SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
-		SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
-		SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
-		SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
-		SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
-		SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
-	EMIF0_REG(SDRAM_CONFIG) = reg;
-	CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
-
-	// Set the external bank position to 0
-	EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
+    uint32_t reg;
+
+    // Enable the control module:
+    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
+
+    // Enable EMIF module
+    reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
+    reg &= ~3;
+    reg |= 2;
+    CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
+    while((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
+
+    // Configure VTP control
+    CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
+    CNTL_MODULE_REG(VTP_CTRL) &= ~1;
+    CNTL_MODULE_REG(VTP_CTRL) |= 1;
+    // Wait for VTP control to be ready
+    while((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
+
+    // Configure the DDR PHY CMDx/DATAx registers
+    DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
+    DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
+    DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
+    DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
+    DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
+    DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
+
+    DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
+    DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
+    DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
+    DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
+
+    DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
+    DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
+    DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
+    DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
+
+    CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
+    CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
+    CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
+    CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
+    CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
+
+    CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
+
+    CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
+
+    // Enable dynamic power down when no read is being performed and set read latency
+    // to CAS Latency + 2 - 1
+    EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
+    EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
+
+    // Configure the AC timing characteristics
+    EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
+    EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
+    EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
+    EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
+    EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
+    EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
+
+    // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
+    EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
+    // set the referesh rate shadow register to the same value as previous
+    EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
+
+    // Configure the ZQ Calibration
+    EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
+
+    // Configure the SDRAM characteristics
+    reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
+           SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
+           SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
+           SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
+           SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
+           SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
+           SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
+    EMIF0_REG(SDRAM_CONFIG) = reg;
+    CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
+
+    // Set the external bank position to 0
+    EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
 }
diff --git a/ports/beagleboneblack/cpuio.h b/ports/beagleboneblack/cpuio.h
index d1c4fd7..0e64a09 100644
--- a/ports/beagleboneblack/cpuio.h
+++ b/ports/beagleboneblack/cpuio.h
@@ -1,12 +1,12 @@
 #define DEFAULT_BAUD_RATE 115200
 
-#define HWREAD32(a)	*(volatile unsigned long *)(a)
-#define HWREAD16(a)	*(volatile unsigned short *)(a)
-#define HWREAD8(a)	*(volatile unsigned char *)(a)
+#define HWREAD32(a) *(volatile unsigned long *)(a)
+#define HWREAD16(a) *(volatile unsigned short *)(a)
+#define HWREAD8(a)  *(volatile unsigned char *)(a)
 
-#define HWWRITE32(a,b)	*(volatile unsigned long *)(a) = (b)
-#define HWWRITE16(a,b)	*(volatile unsigned short *)(a) = (b)
-#define HWWRITE8(a,b)	*(volatile unsigned char *)(a) = (b)
+#define HWWRITE32(a,b)  *(volatile unsigned long *)(a) = (b)
+#define HWWRITE16(a,b)  *(volatile unsigned short *)(a) = (b)
+#define HWWRITE8(a,b)   *(volatile unsigned char *)(a) = (b)
 
 #define GPIO1_21    (1<<21)
 #define GPIO1_22    (1<<22)
diff --git a/ports/beagleboneblack/etherdev.c b/ports/beagleboneblack/etherdev.c
index 690d21b..050f18f 100644
--- a/ports/beagleboneblack/etherdev.c
+++ b/ports/beagleboneblack/etherdev.c
@@ -7,7 +7,7 @@
 // Author(s):    Michael Kelly, Cogent Computer Systems, Inc.
 // Contributors: Luis Torrico, Cogent Computer Systems, Inc.
 // Date:         05-26-2002
-// Modified:	 06-26-2007
+// Modified:     06-26-2007
 // Description:  This file contains the interface layer between Micro Monitor
 //               and the Ethernet driver for the LAN921x on the CSB733.
 //
@@ -36,12 +36,12 @@ ulong tx_buf[400];
 
 /*
  * enreset():
- *	Reset the PHY and MAC.
+ *  Reset the PHY and MAC.
  */
 void
 enreset(void)
 {
-	smsc911x_reset();
+    smsc911x_reset();
 }
 
 /*
@@ -57,23 +57,23 @@ enreset(void)
 int
 eninit(void)
 {
-	return smsc911x_init();
+    return smsc911x_init();
 
 }
 
 int
 EtherdevStartup(int verbose)
 {
-	/* Initialize local device error counts (if any) here. */
-	/* OPT_ADD_CODE_HERE */
+    /* Initialize local device error counts (if any) here. */
+    /* OPT_ADD_CODE_HERE */
 
-	/* Put ethernet controller in reset: */
-	enreset();
+    /* Put ethernet controller in reset: */
+    enreset();
 
-	/* Initialize controller: */
-	eninit();
+    /* Initialize controller: */
+    eninit();
 
-	return(0);
+    return(0);
 }
 
 /* disablePromiscuousReception():
@@ -82,7 +82,7 @@ EtherdevStartup(int verbose)
 void
 disablePromiscuousReception(void)
 {
-	smsc911x_disable_promiscuous_reception();
+    smsc911x_disable_promiscuous_reception();
 }
 
 /* enablePromiscuousReception():
@@ -91,7 +91,7 @@ disablePromiscuousReception(void)
 void
 enablePromiscuousReception(void)
 {
-	smsc911x_enable_promiscuous_reception();
+    smsc911x_enable_promiscuous_reception();
 }
 
 /* disableBroadcastReception():
@@ -100,7 +100,7 @@ enablePromiscuousReception(void)
 void
 disableBroadcastReception(void)
 {
-	smsc911x_disable_broadcast_reception();
+    smsc911x_disable_broadcast_reception();
 }
 
 /* enableBroadcastReception():
@@ -109,32 +109,32 @@ disableBroadcastReception(void)
 void
 enableBroadcastReception(void)
 {
-	smsc911x_enable_broadcast_reception();
+    smsc911x_enable_broadcast_reception();
 }
 
 void
 disableMulticastReception(void)
 {
-	smsc911x_disable_multicast_reception();
+    smsc911x_disable_multicast_reception();
 }
 
 void
 enableMulticastReception(void)
 {
-	smsc911x_enable_multicast_reception();
+    smsc911x_enable_multicast_reception();
 }
 
 
-/* 
+/*
  * enselftest():
- *	Run a self test of the ethernet device(s).  This can be stubbed
- *	with a return(1).
- *	Return 1 if success; else -1 if failure.
+ *  Run a self test of the ethernet device(s).  This can be stubbed
+ *  with a return(1).
+ *  Return 1 if success; else -1 if failure.
  */
 int
 enselftest(int verbose)
 {
-	return(1);
+    return(1);
 }
 
 /* ShowEtherdevStats():
@@ -144,7 +144,7 @@ enselftest(int verbose)
 void
 ShowEtherdevStats(void)
 {
-	/* OPT_ADD_CODE_HERE */
+    /* OPT_ADD_CODE_HERE */
 }
 
 /* getXmitBuffer():
@@ -156,7 +156,7 @@ ShowEtherdevStats(void)
 uchar *
 getXmitBuffer(void)
 {
-	return((uchar *) tx_buf);
+    return((uchar *) tx_buf);
 }
 
 /* sendBuffer():
@@ -166,24 +166,25 @@ getXmitBuffer(void)
 int
 sendBuffer(int length)
 {
-	ulong temp32;
+    ulong temp32;
 
-    if (length < 64)
+    if(length < 64) {
         length = 64;
+    }
 
-	if (EtherVerbose &  SHOW_OUTGOING)
-		printPkt((struct ether_header *)tx_buf,length,ETHER_OUTGOING);
+    if(EtherVerbose &  SHOW_OUTGOING) {
+        printPkt((struct ether_header *)tx_buf,length,ETHER_OUTGOING);
+    }
 
-	// tell the cs8900a to send the tx buffer pointed to by tx_buf
-	temp32 = smsc911x_tx((ulong)tx_buf, (ulong)length);
+    // tell the cs8900a to send the tx buffer pointed to by tx_buf
+    temp32 = smsc911x_tx((ulong)tx_buf, (ulong)length);
 
-	EtherXFRAMECnt++;
-	if (temp32) {
-		return -1;
-	}
-	else {
-		return 0;
-	}
+    EtherXFRAMECnt++;
+    if(temp32) {
+        return -1;
+    } else {
+        return 0;
+    }
 }
 
 /* DisableEtherdev():
@@ -192,7 +193,7 @@ sendBuffer(int length)
 void
 DisableEtherdev(void)
 {
-	enreset();
+    enreset();
 }
 
 /* extGetIpAdd():
@@ -203,7 +204,7 @@ DisableEtherdev(void)
 char *
 extGetIpAdd(void)
 {
-	return((char *)0);
+    return((char *)0);
 }
 
 /* extGetEtherAdd():
@@ -214,7 +215,7 @@ extGetIpAdd(void)
 char *
 extGetEtherAdd(void)
 {
-	return((char *)0);
+    return((char *)0);
 }
 
 /*
@@ -225,17 +226,17 @@ extGetEtherAdd(void)
 int
 polletherdev(void)
 {
-	ulong pktbuf[RBUFSIZE/4];
-	int	pktlen, pktcnt = 0;
+    ulong pktbuf[RBUFSIZE/4];
+    int pktlen, pktcnt = 0;
 
-	pktlen = smsc911x_rx((uchar *)pktbuf);
+    pktlen = smsc911x_rx((uchar *)pktbuf);
 
-	if(pktlen) {
-		pktcnt = 1;
-		EtherRFRAMECnt++;
-		processPACKET((struct ether_header *)pktbuf, pktlen);
-	}
-	return(pktcnt);
+    if(pktlen) {
+        pktcnt = 1;
+        EtherRFRAMECnt++;
+        processPACKET((struct ether_header *)pktbuf, pktlen);
+    }
+    return(pktcnt);
 }
 
 #endif
diff --git a/ports/beagleboneblack/tfsdev.h b/ports/beagleboneblack/tfsdev.h
index 4331851..50e013f 100644
--- a/ports/beagleboneblack/tfsdev.h
+++ b/ports/beagleboneblack/tfsdev.h
@@ -10,22 +10,26 @@
 */
 
 struct tfsdev tfsdevtbl[] = {
-    {   "//FLASH/",
+    {
+        "//FLASH/",
         TFSSTART,
         TFSEND,
         TFSSPARE,
         TFSSPARESIZE,
         TFSSECTORCOUNT,
-        TFS_DEVTYPE_FLASH, },
+        TFS_DEVTYPE_FLASH,
+    },
 
 #ifdef FLASHRAM_BASE
-    {   "//RAM/",
+    {
+        "//RAM/",
         FLASHRAM_BASE,
         FLASHRAM_END-FLASHRAM_SECTORSIZE,
         FLASHRAM_END-FLASHRAM_SECTORSIZE+1,
         FLASHRAM_SECTORSIZE,
         FLASHRAM_SECTORCOUNT-1,
-        TFS_DEVTYPE_RAM | TFS_DEVINFO_AUTOINIT, },
+        TFS_DEVTYPE_RAM | TFS_DEVINFO_AUTOINIT,
+    },
 #endif
     { 0, TFSEOT,0,0,0,0,0 }
 };
diff --git a/ports/beagleboneblack/xcmdtbl.h b/ports/beagleboneblack/xcmdtbl.h
index 9b6a0b9..70cc54f 100644
--- a/ports/beagleboneblack/xcmdtbl.h
+++ b/ports/beagleboneblack/xcmdtbl.h
@@ -9,4 +9,4 @@
     { "dummy",    dummycmd,   dummyHelp,    0 },
 */
 
-{"mmc",		mmc,		mmcHelp, 	0},
+{"mmc",     mmc,        mmcHelp,    0},