sis - Simple Instruction Simulator

	Commit message (Expand)	Author	Files	Lines
2020-12-15	Added support for RISCV32 systems with CLINT/PLIC	Jiri Gaisler	1	-2/+6
2020-12-01	Added emulation of GR740 SOC2.25	Jiri Gaisler	1	-1/+1
2020-10-28	Add networking support using host tap device2.23	Jiri Gaisler	1	-0/+1
2020-09-09	Map RISC-V FPU CSR on host cpu using fenv.h	Jiri Gaisler	1	-1/+1
2019-11-09	Support building on MinGW-W64/MSYS22.19	Jiri Gaisler	1	-1/+2
2019-07-02	Make readline conditional and add linenoise it not present.	Chris Johns	1	-3/+10