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diff --git a/sis.info b/sis.info new file mode 100644 index 0000000..10f23dc --- /dev/null +++ b/sis.info @@ -0,0 +1,890 @@ +This is sis.info, produced by makeinfo version 6.5 from sis.texi. + +This manual is for SIS (version 2.14, 9 April 2019). + + Copyright (C) 2019 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this + document under the terms of the GNU Free Documentation License, + Version 1.3 or any later version published by the Free Software + Foundation; with no Invariant Sections, with no Front-Cover Texts, + and with no Back-Cover Texts. A copy of the license is included in + the section entitled "GNU Free Documentation License". +INFO-DIR-SECTION Texinfo documentation system +START-INFO-DIR-ENTRY +* sis: (sis)Invoking sis. +END-INFO-DIR-ENTRY + + +File: sis.info, Node: Top, Next: Introduction, Up: (dir) + +SIS +*** + +This manual is for SIS (version 2.14, 9 April 2019). + +* Menu: + +* Introduction:: +* Invoking sis:: +* Commands :: +* Emulated Systems :: +* GNU Free Documentation License:: +* Index:: + + +File: sis.info, Node: Introduction, Next: Invoking sis, Prev: Top, Up: Top + +1 Introduction +************** + +SIS is a SPARC V7/V8 and RISC-V RV32IMACF architecture simulator. It +consist of two parts, the simulator core and a user defined memory +module. The simulator core executes the instructions while the memory +module emulates memory and peripherals. + + +File: sis.info, Node: Invoking sis, Next: Commands, Prev: Introduction, Up: Top + +2 Invoking sis +************** + +The simulator is started as follows: + sis [options] [file] + + The following options are recognized: + +'-c FILE' + Read sis commands from FILE at startup. + +'-cov' + Enable code coverage and write a coverage file at exit. + +'-d CLOCKS' + Set the the number of CLOCKS in each time-slice for multi-processor + simulation. Default is 50, set lower for higher accuracy. + +'-erc32' + Emulate the SPARC V7 ERC32 processor + +'-freq FREQ' + Set frequency of emulated cpu. This is used by the 'perf' command + to calculated the MIPS figure for a particular configuration. The + frequency must be an integer indicating the frequency in MHz. + +'-gdb' + Start a gdb server, listening on port 1234. An alternative port + can be specified with -PORT NN. + +'-leon2' + Emulate the SPARC V8 LEON2 processor + +'-leon3' + Emulate the SPARC V8 LEON3 processor + +'-m CORES' + Enable the number of CORES (2 - 4) in a leon3 or RISC-V + multi-processor system. + +'-nfp' + Disable the simulated FPU, so each FPU instruction will generate a + FPU disabled trap. + +'-port PORT' + Use PORT for the gdb server. Default is port 1234. + +'-r' + Start execution immediately without an interactive shell. This is + useful for automated testing. + +'-riscv' + Emulate a RISC-V RV32IMACF processor + +'-tlim DELAY' + Used together with -R to limit the amount of simulated time that + the simulator runs for before exiting. The following units are + recognized: US, MS and S. To limit simulated time to 100 seconds, + use: -TLIM 100 S. + +'-uart1 DEVICE' + Connect UART1 (console) of the simulator to DEVICE. stdin/stout is + default. +'-v' + Increase the debug level with 1, to provide more diagnostic + messages. Can be added multiple times. + +'file' + The executable file to be loaded must be an SPARC or RISCV ELF + file. On start-up, the file is loaded into the simulated memory. + + +File: sis.info, Node: Commands, Next: Emulated Systems, Prev: Invoking sis, Up: Top + +3 Commands +********** + +Below is the description of commands that are recognized by the +simulator. The command-line is parsed using GNU readline. A command +history of 64 commands is maintained. Use the up/down arrows to recall +previous commands. For more details, see the readline documentation. + +'batch FILE' + + Execute a batch file of SIS commands. + +'+bp ADDRESS' +'break ADDRESS' + + Set a breakpoint at ADDRESS. + +'bp' + Print all breakpoints. + +'delete NUM' + Delete breakpoint NUM. Use 'bp' or 'break' to see which number is + assigned to the breakpoints. + +'csr' + Show RISC-V CSR registers + +'cont [COUNT]' + Continue execution at present position, optionally for COUNT + instructions. + +'dis [ADDR] [COUNT]' + Disassemble [COUNT] instructions at address [ADDR]. Default values + for COUNT is 16 and ADDR is the present program counter. + +'echo STRING' + Print STRING to the simulator window. + +'float' + Print the FPU registers + +'gdb [PORT]' + Start the gdb server interface. Default port is 1234, but can be + overriden using the PORT argument. 'gdb' should be started with + 'target extended-remote localhost:1234'. + +'go ADDRESS [COUNT]' + Set pc to ADDRESS and resume execution. If COUNT is given, 'sis' + will stop after COUNT instructions have been executed. + +'help' + Print a small help menu for the SIS commands. + +'hist [TRACE_LENGTH]' + + Enable the instruction trace buffer. The TRACE_LENGTH last + executed instructions will be placed in the trace buffer. A 'hist' + command without a TRACE_LENGTH will display the trace buffer. + Specifying a zero trace length will disable the trace buffer. + +'load FILE_NAME' + + Load an ELF file into simulator memory. + +'mem [ADDR] [COUNT]' + + Display memory at [ADDR] for [COUNT] bytes. Same default values as + for the 'dis' command. + +'quit' + Exits the simulator. + +'perf [reset]' + The 'perf' command will display various execution statistics. A + 'perf reset' command will reset the statistics. This can be used + if statistics shall be calculated only over a part of the program. + The 'run' and 'reset' command also resets the statistic + information. + +'reg [REG_NAME] [VALUE]' + Print or set the CPU registers. 'reg' without parameters prints + the CPU registers. 'reg' REG_NAME VALUE sets the corresponding + register to VALUE. Valid register names for SPARC are psr, tbr, + wim, y, g1-g7, o0-o7 and l0-l7. Valid register names for RISCV-V + are mtvec, mstatus, pc, ra, sp, gp, tp, t0-t6, s0-s11 and a0-a7. + +'reset' + Perform a power-on reset. This command is equal to 'run 0'. + +'run [COUNT]' + + Reset the simulator and start execution from the entry point of the + loaded ELF file. If an instruction count is given (COUNT), the + simulator will stop after the specified number of instructions. + The event queue is emptied but any set breakpoints remain. + +'step' + + Execute one instruction and print it to the simulator console. + Equal to command 'trace 1' + +'sym' + + List symbols and corresponding addresses in the loaded program. + +'trace [COUNT]' + + Resume the simulator at the present position and print each execute + instruction executes. If an instruction count is given (COUNT), + the simulator will stop after the specified number of instructions. + +'wmem ADDR DATA' + Write DATA to memory at ADDR. Data is written as a 32-bit word. + +'wp' + Print all watchpoints + +'+wpr ADDRESS' + Adds an read watchpoint at address <address>. + +'-wpr NUM' + Delete read watchpoint NUM. Use WP to see which number is assigned + to the watchpoints. + +'+wpw ADDRESS' +'watch ADDRESS' + Adds an write watchpoint at ADDRESS. + +'-wpw NUM' + + Delete write watchpoint NUM. Use 'wp' to see which number is + assigned to the watchpoints. + + Typing a 'Ctrl-C' will interrupt a running simulator. + + Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are +all interpreted as 'cont'. + + +File: sis.info, Node: Emulated Systems, Next: GNU Free Documentation License, Prev: Commands, Up: Top + +4 Emulated Systems +****************** + +'sis' is capable of emulating four different processor systems: + +'ERC32' + ERC32 SPARC V7 processor + +'LEON2' + LEON2 SPARC V8 processor + +'LEON3' + LEON3 SPARC V8 processor + +'RISC-V' + RISC-V (RV32IMACFD) processor + + The following sections outline the emulation characteristics of the +four supported systems. + +4.1 ERC32 SPARC V7 processor +============================ + +The radiation-hard ERC32 processor was developed by ESA in the mid-90's +for critical space application. It was used in the control computer for +the International Space Station (ISS) and also in the ATV re-supply ship +for the ISS. The sub-sequent single-chip ERC32SC was used in a multitude +of satellites, launchers and interplanetary probes, and is still being +manufactured by Atmel. See the ESA ERC32 page +(http://http://microelectronics.esa.int/erc32/index.html) for more +technical documetation. + + Sis emulates the original three-chip version of the ERC32 processor, +consisting of the integer unit (IU), floating-point unit (FPU) and the +memort controller (MEC). The IU is based on the Cypress CY601 SPARC V7 +processor, while the FPU is based on the Meiko FPU. The MEC implements +various peripheral functions and a memory controller. The single-chip +verion of ERC32 (ERC32SC/TSC695F) is functionally identical to the +original chip-set, but can operate at a higher frequency (25 MHz) + +The following functions of the ERC32 are emulated by sis: + + * IU & FPU with accurate timing + * UART A & B + * Real-time clock + * General purpose timer + * Interrupt controller + * Breakpoint register + * Watchpoint register + * 16 Mbyte ROM + * 16 Mbyte RAM + +4.1.1 IU and FPU instruction timing. +------------------------------------ + +The simulator provides cycle true simulation for ERC32. The following +table shows the emulated instruction timing for IU & FPU: + +Instruction Cycles +----------------------------- +jmpl, rett 2 +load 2 +store 3 +load double 3 +store double 4 +other integer ops 1 +fabs 2 +fadds 4 +faddd 4 +fcmps 4 +fcmpd 4 +fdivs 20 +fdivd 35 +fmovs 2 +fmuls 5 +fmuld 9 +fnegs 2 +fsqrts 37 +fsqrtd 65 +fsubs 4 +fsubd 4 +fdtoi 7 +fdots 3 +fitos 6 +fitod 6 +fstoi 6 +fstod 2 + + The parallel operation between the IU and FPU is modelled. This +means that a FPU instruction will execute in parallel with other +instructions as long as no data or resource dependency is detected. See +the 90C602E data sheet for the various types of dependencies. Tracing +using the 'trace' command will display the current simulator time in the +left column. This time indicates when the instruction is fetched. If a +dependency is detected, the following fetch will be delayed until the +conflict is resolved. + + The load dependency in the IU is also modelled - if the destination +register of a load instruction is used by the following instruction, an +idle cycle is inserted. + +4.1.2 UART A and B +------------------ + +UART A is by default connected to the console, while UART B is disabled. +Both UARTs can be connected to any file/device using the -uart1 and +-uart2 options at start-up. The following registers are implemented: + +Register Address +-------------------------------------- +UART A RX and TX register 0x01f800e0 +UART B RX and TX register 0x01f800e4 +UART status register 0x01f800e8 + + The UARTs generate interrupt 4 and 5 after each received or +transmitted character. The error interrupt is generated if overflow +occurs - other errors cannot occur. + + +File: sis.info, Node: GNU Free Documentation License, Next: Index, Prev: Emulated Systems, Up: Top + +Appendix A GNU Free Documentation License +***************************************** + + Version 1.3, 3 November 2008 + + Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. + <http://fsf.org/> + + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + 0. PREAMBLE + + The purpose of this License is to make a manual, textbook, or other + functional and useful document "free" in the sense of freedom: to + assure everyone the effective freedom to copy and redistribute it, + with or without modifying it, either commercially or + noncommercially. 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A copy of the license is included in the section entitled ``GNU + Free Documentation License''. + + If you have Invariant Sections, Front-Cover Texts and Back-Cover +Texts, replace the "with...Texts." line with this: + + with the Invariant Sections being LIST THEIR TITLES, with + the Front-Cover Texts being LIST, and with the Back-Cover Texts + being LIST. + + If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. + + If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of free +software license, such as the GNU General Public License, to permit +their use in free software. + + +File: sis.info, Node: Index, Prev: GNU Free Documentation License, Up: Top + +Index +***** + + +* Menu: + +* Commands: Commands. (line 6) +* Emulated Systems: Emulated Systems. (line 6) +* Introduction: Introduction. (line 6) +* invoking sis: Invoking sis. (line 6) +* sis: Invoking sis. (line 6) + + + +Tag Table: +Node: Top697 +Node: Introduction948 +Node: Invoking sis1310 +Node: Commands3362 +Node: Emulated Systems7466 +Node: GNU Free Documentation License11416 +Node: Index36564 + +End Tag Table |