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diff --git a/README.riscv b/README.riscv new file mode 100644 index 0000000..49af929 --- /dev/null +++ b/README.riscv @@ -0,0 +1,71 @@ + +1. RISC-V emulation + +The file 'riscv.h' contains a model of RISC-V RV32IMACFD cpu. It +uses the same GRLIB peripherals as the leon3 cpu, including +the interrupt controller, UART and timers. Single- and double-precision floats +are supported as defined in the F/D extension with the exeption that the +rounding mode is fixed to round-to-nearest. + + +1.1 Multiprocessing + +It is possible to emulate an SMP RISC-V system with up to 4 cores. +Add the switch -m <n> when starting the simulator, where n can be +2 - 4. The cores are simulated in a round-robin fashion with a time- +slice of 50 clocks. Shorter or longer time-slices can be selected +using -d <clocks>/ + +1.2 UART + +The UART emulates an APBUART and is located at address 0x80000100. +The following registers are implemented: + +- UART RX and TX register (0x80000100) +- UART status register (0x80000104) + +The UART generates interrupt 3. + +1.3 Timer unit (GPTIMER) + +The GPTIMER programmable counter is emulated and located at +address 0x80000300. It is configured with two timers and using IRQMP +interrupts 8 and 9. + +1.4 Interrupt controller + +The IRQMP interrupt controller is implemented as described in the +GRLIB IP manual, with the exception of the interrupt level register. +Extended interrupts are not supported. The registers are located +at address 0x80000200. + +The IRQMP interrupts (1 - 15) are mapped in RISC-V external interrupts 17 - 31. + +1.5 Memory interface + +The following memory areas are valid for the Leon3 simulator: + +0x00000000 - 0x01000000 ROM (16 Mbyte, loaded at start-up) +0x40000000 - 0x41000000 RAM (16 Mbyte, loaded at start-up) +0x80000000 - 0x81000000 APB bus, including plug&play +0xFFFFF000 - 0xFFFFFFFF AHB plug&play area + +Access to non-existing memory will result in a memory exception trap. + +1.6 Power-down mode + +The RISC-V power-down feature (WFI) is supported. When power-down is +entered, time is skipped forward until the next event in the event queue. +Ctrl-C in the simulator window will exit the power-down mode. + + 1.7 Code coverage + +Code coverage is currently only supported for 32-bit instructions, i.e. +the C-extension can not be used when code coverage is measured. + +1.8 RISC-V 64-bit timer + +The standard RISC-V 64-bit timer is provided and can be read through the time and +timeh CSR. The timer does not generare any interrupt and the timecmp register is not +implemented. + |