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authorJiri Gaisler <jiri@gaisler.se>2019-05-28 00:02:40 +0200
committerJiri Gaisler <jiri@gaisler.se>2019-05-28 00:09:27 +0200
commit9277f1913aa341efbf6d111ec25e1dc863158cf5 (patch)
tree71fd2e77837ad5cd15d732ec208bfeca990ed275 /sis.c
parentAdd emulated L1 cache to SMP configurations (diff)
downloadsis-9277f1913aa341efbf6d111ec25e1dc863158cf5.tar.bz2
Made L1 cache optional through --enable-l1cache
* Removed stale config.h * Updated autoconf script with relevant checks * Re-implemented leon3/grlib timer with less events * Bumped version to 2.15
Diffstat (limited to 'sis.c')
-rw-r--r--sis.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sis.c b/sis.c
index a1411ae..72466c6 100644
--- a/sis.c
+++ b/sis.c
@@ -26,6 +26,7 @@
#include <fcntl.h>
#include "sis.h"
#include <inttypes.h>
+#include <libgen.h>
/* Structures and functions from readline library */
@@ -184,9 +185,12 @@ main(argc, argv)
if (!freq) freq = 14;
}
+#ifdef ENABLE_L1CACHE
if (ncpu > 1)
printf(" L1 cache: %dK/%dK, %d bytes/line \n",
(1 << (L1IBITS - 10)), (1 << (L1DBITS - 10)), (1 << L1ILINEBITS));
+#endif
+
if (nfp)
printf(" FPU disabled\n");
ebase.freq = freq;