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author | Jiri Gaisler <jiri@gaisler.se> | 2019-05-22 21:56:59 +0200 |
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committer | Jiri Gaisler <jiri@gaisler.se> | 2019-05-27 10:35:06 +0200 |
commit | 6a742ad589f8a5967cb878e4065f70d93b90fb58 (patch) | |
tree | 7a71ab6385f0f177594ebe0be30f2c65f7e11497 /riscv.h | |
parent | Completed texi manual (diff) | |
download | sis-6a742ad589f8a5967cb878e4065f70d93b90fb58.tar.bz2 |
Add emulated L1 cache to SMP configurations
* Also improve timing accuracy for certain instructions
Diffstat (limited to 'riscv.h')
-rw-r--r-- | riscv.h | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -26,6 +26,9 @@ #define FPU_D_ENABLED #define T_JALR 2 #define T_BMISS 2 +#define T_MUL 8 +#define T_DIV 35 +#define T_AMO 5 #define TRAP_IEXC 1 #define TRAP_ILLEG 2 |