diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-08-09 09:59:45 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-08-10 08:34:34 +0200 |
| commit | ffec9f96fc727cc1745b2ee3e2fda965df8198d6 (patch) | |
| tree | 73f29c0ed8072083d00379382fe21304047386db /cpukit | |
| parent | 52e595104c10720265f390dd9bf11d7d0c58dde8 (diff) | |
arm: Fix cache support for ARM926EJ-S
The ARM926EJ-S is an ARMv5T architecture processor and lacks some
features of ARMv6 processors such as the ARM1176JZF-S.
Close #4940.
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h index 333cd7c8a0..c239eaccc8 100644 --- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h +++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h @@ -1309,15 +1309,17 @@ arm_cp15_data_cache_test_and_clean(void) ); } -/* In DDI0301H_arm1176jzfs_r0p7_trm - * 'MCR p15, 0, <Rd>, c7, c14, 0' means - * Clean and Invalidate Entire Data Cache - */ ARM_CP15_TEXT_SECTION static inline void arm_cp15_data_cache_clean_and_invalidate(void) { ARM_SWITCH_REGISTERS; +#if __ARM_ARCH >= 6 + /* + * In DDI0301H_arm1176jzfs_r0p7_trm + * 'MCR p15, 0, <Rd>, c7, c14, 0' means + * Clean and Invalidate Entire Data Cache + */ uint32_t sbz = 0; __asm__ volatile ( @@ -1328,6 +1330,22 @@ arm_cp15_data_cache_clean_and_invalidate(void) : [sbz] "r" (sbz) : "memory" ); +#else + /* + * Assume this is an ARM926EJ-S. Use the test, clean, and invalidate DCache + * operation. + */ + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "1:\n" + "mrc p15, 0, r15, c7, c14, 3\n" + "bne 1b\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : + : "memory" + ); +#endif } ARM_CP15_TEXT_SECTION static inline void |