diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2023-08-13 17:15:13 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-08-22 12:19:16 -0500 |
| commit | 78001d58604992ecee1062c73dd94ca5531ea0c0 (patch) | |
| tree | d97f9f79231ea559fcfe71a29bc117bc974ebcfa /cpukit | |
| parent | 3d0dc8450ef53eaa19a0c54931795af09c5e1935 (diff) | |
cpukit/score/aarch64: Use correct MAIR index
The MAIR index currently assigned (1) for uncached memory segments is
not configured properly for this purpose. Instead, this switches
uncached memory segment flags to MAIR index 2 which is properly
configured for uncached inner and outer shareable domains.
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h index 0d65004f88..ca9b60e6d1 100644 --- a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h +++ b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h @@ -70,7 +70,7 @@ extern "C" { #define AARCH64_MMU_CODE_RW_CACHED AARCH64_MMU_DATA_RW_CACHED #define AARCH64_MMU_DATA_RO \ - ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 1 ) | MMU_DESC_WRITE_DISABLE ) + ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) | MMU_DESC_WRITE_DISABLE ) #define AARCH64_MMU_CODE AARCH64_MMU_DATA_RO #define AARCH64_MMU_CODE_RW AARCH64_MMU_DATA_RW @@ -78,7 +78,7 @@ extern "C" { #define AARCH64_MMU_DATA_RW_CACHED \ ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 3 ) ) #define AARCH64_MMU_DATA_RW \ - ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 1 ) ) + ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 2 ) ) #define AARCH64_MMU_DEVICE ( AARCH64_MMU_FLAGS_BASE | MMU_DESC_MAIR_ATTR( 0 ) ) rtems_status_code aarch64_mmu_map( |