spec: Add RISC-V grlib support

11 files changed, 357 insertions, 0 deletions

diff --git a/spec/bsp/riscv/if/grlib-io-group.yml b/spec/bsp/riscv/if/grlib-io-group.yml
new file mode 100644
index 00000000..87f3d109
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-io-group.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  This group contains the GRLIB register load/store API.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+description: null
+enabled-by: true
+identifier: RTEMSDeviceGRLIBIO
+index-entries: []
+interface-type: group
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: /dev/grlib/if/group
+name: Register Load/Store
+text: |
+  The GRLIB API shall contain the GRLIB Register Load/Store API.
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-io-header.yml b/spec/bsp/riscv/if/grlib-io-header.yml
new file mode 100644
index 00000000..b63e71de
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-io-header.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  This header file defines the register load/store interface.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+enabled-by: riscv
+index-entries: []
+interface-type: header-file
+links:
+- role: interface-placement
+  uid: /if/domain
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/io-header
+path: grlib/io.h
+prefix: bsps/riscv/include
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-load-08.yml b/spec/bsp/riscv/if/grlib-load-08.yml
new file mode 100644
index 00000000..06a99767
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-load-08.yml
@@ -0,0 +1,37 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Loads the memory-mapped unsigned 8-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      return *address;
+    params:
+    - const volatile ${/c/if/uint8_t:/name} *${.:/params[0]/name}
+    return: ${/c/if/uint8_t:/name}
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/load-08
+name: grlib_load_8
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 8-bit register to load.
+  dir: null
+  name: address
+return:
+  return: |
+    Returns the loaded register value.
+  return-values: []
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-load-16.yml b/spec/bsp/riscv/if/grlib-load-16.yml
new file mode 100644
index 00000000..4a9c3a44
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-load-16.yml
@@ -0,0 +1,37 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Loads the memory-mapped unsigned 16-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      return *address;
+    params:
+    - const volatile ${/c/if/uint16_t:/name} *${.:/params[0]/name}
+    return: ${/c/if/uint16_t:/name}
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/load-16
+name: grlib_load_16
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 16-bit register to load.
+  dir: null
+  name: address
+return:
+  return: |
+    Returns the loaded register value.
+  return-values: []
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-load-32.yml b/spec/bsp/riscv/if/grlib-load-32.yml
new file mode 100644
index 00000000..41da19f5
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-load-32.yml
@@ -0,0 +1,37 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Loads the memory-mapped unsigned 32-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      return *address;
+    params:
+    - const volatile ${/c/if/uint32_t:/name} *${.:/params[0]/name}
+    return: ${/c/if/uint32_t:/name}
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/load-32
+name: grlib_load_32
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 32-bit register to load.
+  dir: null
+  name: address
+return:
+  return: |
+    Returns the loaded register value.
+  return-values: []
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-load-64.yml b/spec/bsp/riscv/if/grlib-load-64.yml
new file mode 100644
index 00000000..afa15c63
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-load-64.yml
@@ -0,0 +1,37 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Loads the memory-mapped unsigned 64-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      return *address;
+    params:
+    - const volatile ${/c/if/uint64_t:/name} *${.:/params[0]/name}
+    return: ${/c/if/uint64_t:/name}
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/load-64
+name: grlib_load_64
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 64-bit register to load.
+  dir: null
+  name: address
+return:
+  return: |
+    Returns the loaded register value.
+  return-values: []
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-store-08.yml b/spec/bsp/riscv/if/grlib-store-08.yml
new file mode 100644
index 00000000..c9700c08
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-store-08.yml
@@ -0,0 +1,39 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Stores the value to the memory-mapped unsigned 8-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+     *address = value;
+    params:
+    - volatile ${/c/if/uint8_t:/name} *${.:/params[0]/name}
+    - ${/c/if/uint8_t:/name} ${.:/params[1]/name}
+    return: void
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/store-08
+name: grlib_store_8
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 8-bit register.
+  dir: null
+  name: address
+- description: |
+    is the value to store.
+  dir: null
+  name: value
+return: null
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-store-16.yml b/spec/bsp/riscv/if/grlib-store-16.yml
new file mode 100644
index 00000000..0482cd2c
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-store-16.yml
@@ -0,0 +1,39 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Stores the value to the memory-mapped unsigned 16-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      *address = value;
+    params:
+    - volatile ${/c/if/uint16_t:/name} *${.:/params[0]/name}
+    - ${/c/if/uint16_t:/name} ${.:/params[1]/name}
+    return: void
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/store-16
+name: grlib_store_16
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 16-bit register.
+  dir: null
+  name: address
+- description: |
+    is the value to store.
+  dir: null
+  name: value
+return: null
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-store-32.yml b/spec/bsp/riscv/if/grlib-store-32.yml
new file mode 100644
index 00000000..a6c1897e
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-store-32.yml
@@ -0,0 +1,39 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Stores the value to the memory-mapped unsigned 32-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      *address = value;
+    params:
+    - volatile ${/c/if/uint32_t:/name} *${.:/params[0]/name}
+    - ${/c/if/uint32_t:/name} ${.:/params[1]/name}
+    return: void
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/store-32
+name: grlib_store_32
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 32-bit register.
+  dir: null
+  name: address
+- description: |
+    is the value to store.
+  dir: null
+  name: value
+return: null
+type: interface
diff --git a/spec/bsp/riscv/if/grlib-store-64.yml b/spec/bsp/riscv/if/grlib-store-64.yml
new file mode 100644
index 00000000..2323688b
--- /dev/null
+++ b/spec/bsp/riscv/if/grlib-store-64.yml
@@ -0,0 +1,39 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+brief: |
+  Stores the value to the memory-mapped unsigned 64-bit register.
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+definition:
+  default:
+    attributes: null
+    body: |
+      *address = value;
+    params:
+    - volatile ${/c/if/uint64_t:/name} *${.:/params[0]/name}
+    - ${/c/if/uint64_t:/name} ${.:/params[1]/name}
+    return: void
+  variants: []
+description: null
+enabled-by: riscv
+index-entries: []
+interface-type: function
+links:
+- role: interface-placement
+  uid: grlib-io-header
+- role: interface-ingroup
+  uid: grlib-io-group
+- role: proxy-member
+  uid: /dev/grlib/if/store-64
+name: grlib_store_64
+notes: null
+params:
+- description: |
+    is the address of the memory-mapped unsigned 64-bit register.
+  dir: null
+  name: address
+- description: |
+    is the value to store.
+  dir: null
+  name: value
+return: null
+type: interface
diff --git a/spec/bsp/riscv/if/group.yml b/spec/bsp/riscv/if/group.yml
new file mode 100644
index 00000000..3229af64
--- /dev/null
+++ b/spec/bsp/riscv/if/group.yml
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH & Co. KG
+enabled-by: riscv
+identifier: RTEMSBSPsRISCV
+links:
+- role: requirement-refinement
+  uid: ../../if/group
+non-functional-type: design-group
+rationale: null
+references: []
+requirement-type: non-functional
+text: |
+  The ${/glossary/bsp:/term} component shall have a component containing the
+  RISC-V ${/glossary/bsp:/plural}.
+type: requirement