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SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
build-type: config-file
content: |
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
* Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* The RAM supports 32G of DDR4 or LPDDR memory using DDRMC0.
*
* The DDR Conroller (DDRC) has two regions R0 and R1. R0 is
* in the A32 address space and R1 is in the A64 address space.
*/
DDRMC0_REGION_0_BASE = 0x00000000000;
DDRMC0_REGION_0_LENGTH = 0x00080000000;
DDRMC0_REGION_1_BASE = 0x00800000000;
DDRMC0_REGION_1_LENGTH = 0x01000000000;
BSP_RAM_BASE = ${BSP_XILINX_VERSAL_RAM_BASE};
BSP_R0_RAM_BASE = DDRMC0_REGION_0_BASE;
BSP_R0_RAM_LENGTH =
${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
DDRMC0_REGION_0_LENGTH - BSP_RAM_BASE : ${BSP_XILINX_VERSAL_RAM_LENGTH};
BSP_R0_RAM_END = BSP_RAM_BASE + BSP_R0_RAM_LENGTH;
BSP_R1_RAM_BASE = DDRMC0_REGION_1_BASE;
BSP_R1_RAM_LENGTH =
${BSP_XILINX_VERSAL_RAM_LENGTH} >= DDRMC0_REGION_0_LENGTH ?
${BSP_XILINX_VERSAL_RAM_LENGTH} - DDRMC0_REGION_0_LENGTH : 0;
AARCH64_MMU_TT_PAGES_SIZE = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES};
MEMORY {
RAM : ORIGIN = BSP_RAM_BASE + ${BSP_XILINX_VERSAL_LOAD_OFFSET},
LENGTH = BSP_R0_RAM_LENGTH - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - AARCH64_MMU_TT_PAGES_SIZE
RAM1 : ORIGIN = BSP_R1_RAM_BASE,
LENGTH = BSP_R1_RAM_LENGTH
NOCACHE : ORIGIN = BSP_RAM_BASE + BSP_R0_RAM_LENGTH - AARCH64_MMU_TT_PAGES_SIZE - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
RAM_MMU : ORIGIN = BSP_R0_RAM_END - AARCH64_MMU_TT_PAGES_SIZE,
LENGTH = AARCH64_MMU_TT_PAGES_SIZE
}
REGION_ALIAS ("REGION_START", RAM);
REGION_ALIAS ("REGION_VECTOR", RAM);
REGION_ALIAS ("REGION_TEXT", RAM);
REGION_ALIAS ("REGION_TEXT_LOAD", RAM);
REGION_ALIAS ("REGION_RODATA", RAM);
REGION_ALIAS ("REGION_RODATA_LOAD", RAM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", RAM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
REGION_ALIAS ("REGION_BSS", RAM);
REGION_ALIAS ("REGION_WORK", RAM);
REGION_ALIAS ("REGION_STACK", RAM);
REGION_ALIAS ("REGION_NOCACHE", NOCACHE);
REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE);
bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;
bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
bsp_vector_table_in_start_section = 1;
bsp_r0_ram_base = DDRMC0_REGION_0_BASE;
bsp_r0_ram_end = ORIGIN (RAM) + LENGTH (RAM);
bsp_r1_ram_base = ORIGIN (RAM1);
bsp_r1_ram_end = ORIGIN (RAM1) + LENGTH (RAM1);
bsp_translation_table_base = ORIGIN (RAM_MMU);
bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
OUTPUT_FORMAT ("elf64-littleaarch64")
OUTPUT_ARCH (aarch64)
INCLUDE linkcmds.base
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
- Copyright (C) 2022 Chris Johns <chrisj@rtems.org>
enabled-by: true
install-path: ${BSP_LIBDIR}
links: []
target: linkcmds
type: build
|
