1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
|
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @brief RTEMS Port of Linux SPI API
*
* @ingroup SPILinux
*/
/*
* Copyright (c) 2016 embedded brains GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _UAPI_LINUX_SPI_H
#define _UAPI_LINUX_SPI_H
#include <sys/ioccom.h>
#include <stddef.h>
#include <stdint.h>
/**
* @defgroup SPILinux Linux SPI User-Space API
*
* @ingroup SPI
*
* @brief RTEMS port of Linux SPI user-space API.
*
* Additional documentation is available through the Linux sources, see
*
* /usr/src/linux/include/uapi/linux/spidev.h.
*
* @{
*/
/**
* @name SPI Transfer Flags
*
* @{
*/
/**
* @brief SPI transfer flag which sets the clock phase.
*/
#define SPI_CPHA 0x01
/**
* @brief SPI transfer flag which sets the clock polarity.
*/
#define SPI_CPOL 0x02
/**
* @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
* leading edge).
*/
#define SPI_MODE_0 0
/**
* @brief SPI transfer flag which sets SPI Mode 0 (clock starts low, sample on
* trailing edge).
*/
#define SPI_MODE_1 SPI_CPHA
/**
* @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
* leading edge).
*/
#define SPI_MODE_2 SPI_CPOL
/**
* @brief SPI transfer flag which sets SPI Mode 0 (clock starts high, sample on
* trailing edge).
*/
#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
/**
* @brief SPI transfer flag which selects the device by setting the chip select
* line.
*/
#define SPI_CS_HIGH 0x04
/**
* @brief SPI transfer flag which triggers data transmission with the LSB being
* sent first.
*/
#define SPI_LSB_FIRST 0x08
/**
* @brief SPI transfer flag which uses a shared wire for master input/slave
* output as well as master output/slave input.
*/
#define SPI_3WIRE 0x10
/**
* @brief SPI transfer flag which initiates the loopback mode.
*/
#define SPI_LOOP 0x20
/**
* @brief SPI transfer flag which indicates that no chip select is needed due to
* only one device on the bus.
*/
#define SPI_NO_CS 0x40
/**
* @brief SPI transfer flag which pulls the slave to low level during pause.
*/
#define SPI_READY 0x80
/**
* @brief SPI transfer flag which sets up dual mode for transmission.
*/
#define SPI_TX_DUAL 0x100
/**
* @brief SPI transfer flag which sets up quad mode for transmission.
*/
#define SPI_TX_QUAD 0x200
/**
* @brief SPI transfer flag which sets up dual mode for reception.
*/
#define SPI_RX_DUAL 0x400
/**
* @brief SPI transfer flag which sets up quad mode for reception.
*/
#define SPI_RX_QUAD 0x800
/** @} */
#define SPI_IOC_MAGIC 's'
/**
* @brief SPI transfer message.
*/
struct spi_ioc_transfer {
/**
* @brief Buffer for receive data.
*/
void *rx_buf;
/**
* @brief Buffer for transmit data.
*/
const void *tx_buf;
/**
* @brief Length of receive and transmit buffers in bytes.
*/
size_t len;
/**
* @brief Sets the bit-rate of the device.
*/
uint32_t speed_hz;
/**
* @brief Sets the delay after a transfer before the chip select status is
* changed and the next transfer is triggered.
*/
uint16_t delay_usecs;
/**
* @brief Sets the device wordsize.
*/
uint8_t bits_per_word;
/**
* @brief If true, device is deselected after transfer ended and before a new
* transfer is started.
*/
uint8_t cs_change;
/**
* @brief Amount of bits that are used for reading.
*/
uint8_t rx_nbits;
/**
* @brief Amount of bits that are used for writing.
*/
uint8_t tx_nbits;
/**
* @brief Sets one of the possible modes that can be used for SPI transfers
* (dependent on clock phase and polarity).
*/
uint32_t mode;
/**
* @brief Indicates which device is currently used.
*/
uint8_t cs;
};
/**
* @brief Calculates the size of the SPI message array.
*/
#define SPI_MSGSIZE(n) \
(((n) * sizeof(struct spi_ioc_transfer) < IOCPARM_MAX) ? \
(n) * sizeof(struct spi_ioc_transfer) : 0)
/**
* @brief Transfers an array with SPI messages.
*/
#define SPI_IOC_MESSAGE(n) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(n)])
/**
* @brief Reads the least-significant 8-bits of the SPI default mode.
*/
#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, uint8_t)
/**
* @brief Writes the SPI default mode (the most-significant 24-bits of the mode are
* set to zero).
*/
#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, uint8_t)
/**
* @brief Reads the SPI default least-significant bit first setting.
*/
#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, uint8_t)
/**
* @brief Writes the SPI default least-significant-bit first setting.
*/
#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, uint8_t)
/**
* @brief Reads the SPI default bits per word.
*/
#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, uint8_t)
/**
* @brief Writes the SPI default bits per word.
*/
#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, uint8_t)
/**
* @brief Reads the SPI default speed in Hz.
*/
#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, uint32_t)
/**
* @brief Writes the SPI default speed in Hz.
*/
#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, uint32_t)
/**
* @brief Reads the full 32-bit SPI default mode.
*/
#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, uint32_t)
/**
* @brief Writes the full 32-bit SPI default mode.
*/
#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, uint32_t)
#endif /* _UAPI_LINUX_SPI_H */
|
