1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
|
/*
* Cache Management Support Routines for the MC68040
* Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
* Surrey Satellite Technology Limited (SSTL), 2001
*
* $Id$
*/
#include <rtems.h>
#include "cache_.h"
#include <rtems/powerpc/registers.h>
/*
* CACHE MANAGER: The following functions are CPU-specific.
* They provide the basic implementation for the rtems_* cache
* management routines. If a given function has no meaning for the CPU,
* it does nothing by default.
*
* FIXME: Some functions simply have not been implemented.
*/
#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */
/* Helpful macros */
#define PPC_Get_HID0( _value ) \
do { \
_value = 0; /* to avoid warnings */ \
asm volatile( \
"mfspr %0, 0x3f0;" /* get HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
#define PPC_Set_HID0( _value ) \
do { \
asm volatile( \
"isync;" \
"mtspr 0x3f0, %0;" /* load HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
void _CPU_cache_enable_data (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= HID0_DCE; /* set DCE bit */
PPC_Set_HID0( value );
}
void _CPU_cache_disable_data (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value &= ~HID0_DCE; /* clear DCE bit */
PPC_Set_HID0( value );
}
void _CPU_cache_invalidate_1_data_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
}
void _CPU_cache_invalidate_entire_data (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= HID0_DCI; /* set data flash invalidate bit */
PPC_Set_HID0( value );
value &= ~HID0_DCI; /* clear data flash invalidate bit */
PPC_Set_HID0( value );
}
void _CPU_cache_freeze_data (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= HID0_DLOCK; /* set data cache lock bit */
PPC_Set_HID0( value );
}
void _CPU_cache_unfreeze_data (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value &= ~HID0_DLOCK; /* set data cache lock bit */
PPC_Set_HID0( value );
}
void _CPU_cache_flush_1_data_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
}
void _CPU_cache_flush_entire_data (
void )
{
/*
* FIXME: how can we do this?
*/
}
void _CPU_cache_enable_instruction (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= 0x00008000; /* Set ICE bit */
PPC_Set_HID0( value );
}
void _CPU_cache_disable_instruction (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value &= 0xFFFF7FFF; /* Clear ICE bit */
PPC_Set_HID0( value );
}
void _CPU_cache_invalidate_1_instruction_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
}
void _CPU_cache_invalidate_entire_instruction (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= HID0_ICFI; /* set data flash invalidate bit */
PPC_Set_HID0( value );
value &= ~HID0_ICFI; /* clear data flash invalidate bit */
PPC_Set_HID0( value );
}
void _CPU_cache_freeze_instruction (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value |= HID0_ILOCK; /* set instruction cache lock bit */
PPC_Set_HID0( value );
}
void _CPU_cache_unfreeze_instruction (
void )
{
uint32_t value;
PPC_Get_HID0( value );
value &= ~HID0_ILOCK; /* set instruction cache lock bit */
PPC_Set_HID0( value );
}
#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
#define mtspr(_spr,_reg) \
__asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
#define isync \
__asm__ volatile ("isync\n"::)
void _CPU_cache_flush_1_data_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
}
void _CPU_cache_invalidate_1_data_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
}
void _CPU_cache_flush_entire_data ( void ) {}
void _CPU_cache_invalidate_entire_data ( void ) {}
void _CPU_cache_freeze_data ( void ) {}
void _CPU_cache_unfreeze_data ( void ) {}
void _CPU_cache_enable_data ( void )
{
uint32_t r1;
r1 = (0x2<<24);
mtspr( 568, r1 );
isync;
}
void _CPU_cache_disable_data ( void )
{
uint32_t r1;
r1 = (0x4<<24);
mtspr( 568, r1 );
isync;
}
void _CPU_cache_invalidate_1_instruction_line(
const void * _address )
{
register const void *__address = _address;
asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
}
void _CPU_cache_invalidate_entire_instruction ( void ) {}
void _CPU_cache_freeze_instruction ( void ) {}
void _CPU_cache_unfreeze_instruction ( void ) {}
void _CPU_cache_enable_instruction ( void )
{
uint32_t r1;
r1 = (0x2<<24);
mtspr( 560, r1 );
isync;
}
void _CPU_cache_disable_instruction ( void )
{
uint32_t r1;
r1 = (0x4<<24);
mtspr( 560, r1 );
isync;
}
#endif
/* end of file */
|
