c/src/lib/libbsp/or1k/generic_or1k/sim.cfg


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section memory
  name     =      "RAM"
  random_seed = 12345
  type        = random
  ce       =          0
  mc       =          0
  baseaddr = 0x00000000
  size     = 0x08000000
  delayr   =          1
  delayw   =          2
end

section immu
  enabled = 0
  nsets = 64
  nways = 1
  pagesize = 8192
  hitdelay = 0
  missdelay = 0
end

section dmmu
  enabled = 0
  nsets = 64
  nways = 1
  pagesize = 8192
  hitdelay = 0
  missdelay = 0
end
section mc
  enabled = 0
  baseaddr = 0x90000000
  POC = 0x0000000a                 /* 32 bit SSRAM */
  index = 0
end

section ic
  enabled   =   1
  nsets     = 256
  nways     =   1
  blocksize =  32
  hitdelay  =  20
  missdelay =  60
end

section dc
  enabled = 1
  nsets = 256
  nways = 1
  blocksize = 32
  load_hitdelay = 40
  load_missdelay = 120
  store_hitdelay = 40
  store_missdelay = 120
end

section pic
  enabled = 1
  edge_trigger = 1
end

section sim
  verbose  =  1
  debug    =  0
  profile  =  0
  history  =  0
  clkcycle = 10ns		/* 100MHz clock */
end

section VAPI
  enabled = 1
  server_port = 50000
  log_enabled = 1
  vapi_log_file = "vapi.log"
end

section cpu
  ver = 0x12
  cfg = 0x00
  rev = 0x0001
  upr = 0x0000075f
  superscalar = 0
  hazards = 0
  dependstats = 0
  sbuf_len = 100
end

section debug
 enabled = 1
 rsp_enabled = 1
 rsp_port = 50001
end

section uart
  enabled  = 1
  baseaddr = 0x90000000
 #channel = "xterm"
  channel = "file:uart0.rx,uart0.tx"
  irq = 2
  16550    = 1
end

section pm
  enabled = 1
end