blob: 1f5a1a359668db53ef85c0e427096b389cc52aaa (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
/*
* Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/syscon.h>
#include <bsp/lm3s69xx.h>
#include <rtems.h>
static void delay_3_clocks(void)
{
asm volatile(
"nop\n\t"
"nop\n\t"
"nop");
}
void __attribute__((naked)) lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count)
{
asm volatile(
"subs r0, #1\n\t"
"bne lm3s69xx_syscon_delay_3x_clocks\n\t"
"bx lr"
);
}
void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable)
{
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
uint32_t mask = 1 << port;
rtems_interrupt_level level;
rtems_interrupt_disable(level);
if (enable)
syscon->rcgc2 |= mask;
else
syscon->rcgc2 &= ~mask;
delay_3_clocks();
rtems_interrupt_enable(level);
}
void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable)
{
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
uint32_t mask = 1 << port;
rtems_interrupt_level level;
rtems_interrupt_disable(level);
if (enable)
syscon->rcgc1 |= mask;
else
syscon->rcgc1 &= ~mask;
delay_3_clocks();
rtems_interrupt_enable(level);
}
void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable)
{
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
uint32_t mask = 1 << (port + 4);
rtems_interrupt_level level;
rtems_interrupt_disable(level);
if (enable)
syscon->rcgc1 |= mask;
else
syscon->rcgc1 &= ~mask;
delay_3_clocks();
rtems_interrupt_enable(level);
}
void lm3s69xx_syscon_enable_pwm_clock(bool enable)
{
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
rtems_interrupt_level level;
rtems_interrupt_disable(level);
if (enable)
syscon->rcgc0 |= SYSCONRCGC0_PWM;
else
syscon->rcgc0 &= ~SYSCONRCGC0_PWM;
delay_3_clocks();
rtems_interrupt_enable(level);
}
/**
* Sets PWMDIV field in the RCC register.
*
* @note div should be one of SCRCC_PWMDIV_DIV?_VAL constants.
*/
void lm3s69xx_syscon_set_pwmdiv(unsigned int div)
{
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
rtems_interrupt_level level;
rtems_interrupt_disable(level);
syscon->rcc = (syscon->rcc & ~SYSCONRCC_PWMDIV_MSK) | SYSCONRCC_PWMDIV(div)
| SYSCONRCC_USEPWMDIV;
rtems_interrupt_enable(level);
}
|
