1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/*
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Copyright (c) 2013, The Regents of the University of California (Regents).
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <bsp/linker-symbols.h>
#include <rtems/score/riscv-utility.h>
#include <rtems/score/cpu.h>
#include <rtems/asm.h>
EXTERN(bsp_section_bss_begin)
EXTERN(bsp_section_bss_end)
EXTERN(ISR_Handler)
EXTERN(bsp_section_stack_begin)
PUBLIC(bsp_start_vector_table_begin)
PUBLIC(bsp_start_vector_table_end)
PUBLIC(_start)
.section .bsp_start_text, "ax", @progbits
.align 2
TYPE_FUNC(_start)
SYM(_start):
la t0, ISR_Handler
csrw mtvec, t0
/* load stack and frame pointers */
la sp, _Configuration_Interrupt_stack_area_end
/* Clearing .bss */
la t0, bsp_section_bss_begin
la t1, bsp_section_bss_end
_loop_clear_bss:
bge t0, t1, _end_clear_bss
SREG x0, 0(t0)
addi t0, t0, CPU_SIZEOF_POINTER
j _loop_clear_bss
_end_clear_bss:
/* Init FPU unit if it's there */
li t0, MSTATUS_FS
csrs mstatus, t0
j boot_card
.align 4
bsp_start_vector_table_begin:
.word _RISCV_Exception_default /* User int */
.word _RISCV_Exception_default /* Supervisor int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine int */
.word _RISCV_Exception_default /* User timer int */
.word _RISCV_Exception_default /* Supervisor Timer int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine Timer int */
.word _RISCV_Exception_default /* User external int */
.word _RISCV_Exception_default /* Supervisor external int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine external int */
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
bsp_start_vector_table_end:
|