blob: ae3c471fb16f03f18c425bd05d355d6fc0a76017 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
/* @file
*
* @ingroup RTEMSBSPsARMLPC32XX
*
* @brief Implementations of interrupt mechanisms for Time Test 27
*/
/*
* Copyright (c) 2010 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
#include <rtems.h>
#include <bsp/lpc32xx.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#define MUST_WAIT_FOR_INTERRUPT 1
#define LPC32XX_TM27_TIMER (&lpc32xx.timer_2)
#define LPC32XX_TM27_IRQ LPC32XX_IRQ_TIMER_2
static inline void Install_tm27_vector(void (*handler)(rtems_vector_number))
{
static rtems_interrupt_entry entry;
volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
LPC32XX_TIMCLK_CTRL1 |= 1U << 4;
timer->tcr = LPC_TIMER_TCR_RST;
timer->ctcr = 0x0;
timer->pr = 0x0;
timer->ir = 0xff;
timer->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_STOP |
LPC_TIMER_MCR_MR0_RST;
timer->ccr = 0x0;
timer->emr = 0x0;
timer->mr0 = 0x1;
rtems_interrupt_entry_initialize(
&entry,
(rtems_interrupt_handler) handler,
NULL,
"tm27"
);
(void) rtems_interrupt_entry_install(
LPC32XX_TM27_IRQ,
RTEMS_INTERRUPT_SHARED,
&entry
);
}
static inline void Cause_tm27_intr(void)
{
volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
timer->tcr = LPC_TIMER_TCR_EN;
}
static inline void Clear_tm27_intr(void)
{
volatile lpc_timer *timer = LPC32XX_TM27_TIMER;
timer->ir = LPC_TIMER_IR_MR0;
lpc32xx_irq_set_priority(LPC32XX_TM27_IRQ, LPC32XX_IRQ_PRIORITY_LOWEST);
}
static inline void Lower_tm27_intr(void)
{
bsp_interrupt_vector_enable(LPC32XX_TM27_IRQ);
lpc32xx_irq_set_priority(LPC32XX_TM27_IRQ, LPC32XX_IRQ_PRIORITY_HIGHEST);
}
#endif /* __tm27_h */
|