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/*
* Copyright 2017-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#include "dcd.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.dcd_data"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.dcd_data"
#endif
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: DCDx v3.0
processor: MIMXRT1166xxxxx
package_id: MIMXRT1166DVM6A
mcu_data: ksdk2_0
processor_version: 13.0.2
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
const uint8_t dcd_data[] = {
/* HEADER */
/* Tag */
0xD2,
/* Image Length */
0x03, 0x98,
/* Version */
0x41,
/* COMMANDS */
/* group: 'SDRAM Initialization' */
/* #1.1-93, command header bytes for merged 'Write - value' command */
0xCC, 0x02, 0xEC, 0x04,
/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4, comment: 'SEMC_CLKROOT = SYS_PLL2_PFD1 / 2' */
0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03,
/* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4, comment: 'SEMC_ADDR00' */
0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
/* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4, comment: 'SEMC_ADDR01' */
0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
/* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4, comment: 'SEMC_ADDR02' */
0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
/* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4, comment: 'SEMC_ADDR03' */
0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
/* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4, comment: 'SEMC_ADDR04' */
0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
/* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4, comment: 'SEMC_ADDR05' */
0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
/* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4, comment: 'SEMC_ADDR06' */
0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
/* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4, comment: 'SEMC_ADDR07' */
0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
/* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4, comment: 'SEMC_ADDR08' */
0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4, comment: 'SEMC_ADDR09' */
0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4, comment: 'SEMC_ADDR10' */
0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4, comment: 'SEMC_ADDR11' */
0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4, comment: 'SEMC_ADDR12' */
0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4, comment: 'SEMC_BA0' */
0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4, comment: 'SEMC_BA1' */
0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4, comment: 'SEMC_CKE' */
0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4, comment: 'SEMC_CLK' */
0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4, comment: 'SEMC_CS0' */
0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4, comment: 'SEMC_WE' */
0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4, comment: 'SEMC_CAS' */
0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4, comment: 'SEMC_RAS' */
0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4, comment: 'SEMC_DM00' */
0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4, comment: 'SEMC_DM01' */
0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4, comment: 'SEMC_DATA00' */
0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4, comment: 'SEMC_DATA01' */
0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4, comment: 'SEMC_DATA02' */
0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4, comment: 'SEMC_DATA03' */
0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4, comment: 'SEMC_DATA04' */
0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4, comment: 'SEMC_DATA05' */
0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4, comment: 'SEMC_DATA06' */
0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4, comment: 'SEMC_DATA07' */
0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4, comment: 'SEMC_DATA08' */
0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4, comment: 'SEMC_DATA09' */
0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4, comment: 'SEMC_DATA10' */
0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4, comment: 'SEMC_DATA11' */
0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4, comment: 'SEMC_DATA12' */
0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4, comment: 'SEMC_DATA13' */
0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4, comment: 'SEMC_DATA14' */
0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4, comment: 'SEMC_DATA15' */
0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4, comment: 'SEMC_DQS' */
0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10,
/* #1.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4, comment: 'SEMC_ADDR00' */
0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08,
/* #1.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4, comment: 'SEMC_ADDR01' */
0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08,
/* #1.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4, comment: 'SEMC_ADDR02' */
0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08,
/* #1.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4, comment: 'SEMC_ADDR03' */
0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08,
/* #1.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4, comment: 'SEMC_ADDR04' */
0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08,
/* #1.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4, comment: 'SEMC_ADDR05' */
0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
/* #1.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4, comment: 'SEMC_ADDR06' */
0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08,
/* #1.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4, comment: 'SEMC_ADDR07' */
0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08,
/* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4, comment: 'SEMC_ADDR08' */
0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08,
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4, comment: 'SEMC_ADDR09' */
0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08,
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4, comment: 'SEMC_ADDR10' */
0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08,
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4, comment: 'SEMC_ADDR11' */
0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08,
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4, comment: 'SEMC_ADDR12' */
0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08,
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4, comment: 'SEMC_BA0' */
0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08,
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4, comment: 'SEMC_BA1' */
0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08,
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4, comment: 'SEMC_CKE' */
0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08,
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4, comment: 'SEMC_CLK' */
0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08,
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x04, size: 4, comment: 'SEMC_CS0' */
0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x04,
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4, comment: 'SEMC_WE' */
0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08,
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4, comment: 'SEMC_CAS' */
0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08,
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4, comment: 'SEMC_RAS' */
0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08,
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4, comment: 'SEMC_DM00' */
0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08,
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4, comment: 'SEMC_DM01' */
0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08,
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4, comment: 'SEMC_DATA00' */
0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08,
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4, comment: 'SEMC_DATA01' */
0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08,
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4, comment: 'SEMC_DATA02' */
0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08,
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4, comment: 'SEMC_DATA03' */
0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08,
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4, comment: 'SEMC_DATA04' */
0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08,
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4, comment: 'SEMC_DATA05' */
0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08,
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4, comment: 'SEMC_DATA06' */
0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08,
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4, comment: 'SEMC_DATA07' */
0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08,
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4, comment: 'SEMC_DATA08' */
0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08,
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4, comment: 'SEMC_DATA09' */
0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08,
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4, comment: 'SEMC_DATA10' */
0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08,
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4, comment: 'SEMC_DATA11' */
0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08,
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4, comment: 'SEMC_DATA12' */
0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08,
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4, comment: 'SEMC_DATA13' */
0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08,
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4, comment: 'SEMC_DATA14' */
0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08,
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4, comment: 'SEMC_DATA15' */
0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08,
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4, comment: 'SEMC_DQS' */
0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08,
/* #1.82, command: write_value, address: SEMC_MCR, value: 0x1FFF0004, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x00, 0x1F, 0xFF, 0x00, 0x04,
/* #1.83, command: write_value, address: SEMC_BMCR0, value: 0x104085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x08, 0x00, 0x10, 0x40, 0x85,
/* #1.84, command: write_value, address: SEMC_BMCR1, value: 0x40246085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x0C, 0x40, 0x24, 0x60, 0x85,
/* #1.85, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4, comment: 'CS0: Start add Address 0x80000000; Memsize 64MByte' */
0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D,
/* #1.86, command: write_value, address: SEMC_SDRAMCR0, value: 0xF35, size: 4, comment: 'PortSize 16; Burst Len 8; 9 Bit Column Addresses; CAS Latency 3' */
0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x35,
/* #1.87, command: write_value, address: SEMC_SDRAMCR1, value: 0x00664B22, size: 4, comment: 'PRE2ACT: tRP = 18ns; ACT2RW: tRCD = 18ns; RFRC: tRFC=72ns; WRC: tWR=15ns; CKEOFF: tRAS_min = 42ns; ACT2PRE: tRAS_min = 42ns' */
0x40, 0x0D, 0x40, 0x44, 0x00, 0x66, 0x4B, 0x22,
/* #1.88, command: write_value, address: SEMC_SDRAMCR2, value: 0x00090B13, size: 4, comment: 'SRCC: tXSR=120ns; REF2REF: tRFC=72ns; ACT2ACT: tRC=60ns' */
0x40, 0x0D, 0x40, 0x48, 0x00, 0x09, 0x0B, 0x13,
/* #1.89, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A00, size: 4, comment: 'Default values from NXP examples for SEMC' */
0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x00,
/* #1.90, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #1.91, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02,
/* #1.92, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.93, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4, comment: 'IP Command: Precharge All' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
/* #2, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #3, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #4, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #5, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #6, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #7.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Auto Refresh' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #8, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #9, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #10, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #11, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #12, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #13.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Precharge All' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #14, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #15, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #16, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #17, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #18, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #19.1-3, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x1C, 0x04,
/* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4, comment: 'Mode: BurstLen8; CAS Latency 3' */
0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33,
/* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4, comment: 'IP Command: Mode Set' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
/* #20, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #21, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #22, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #23, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #24, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #25.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A01, size: 4, comment: 'Enable autorefresh. Otherwise same as above.' */
0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x01
};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
#else
const uint8_t dcd_data[] = {0x00};
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
#endif /* XIP_BOOT_HEADER_ENABLE */
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