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* spec: Fix XPS_SYS_CTRL_BASEADDR default valueAlex White2023-01-271-2/+3
| | | | | The default value for XPS_SYS_CTRL_BASEADDR was given as an int rather than an iterable.
* bsps/xilinx-zynqmp: Add JFFS2 GQSPI NOR driverAlex White2023-01-272-0/+24
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* bsps: Add Xilinx GQSPI flash helperAlex White2023-01-272-0/+50
| | | | | | This adds helper functions for working with NOR flash connected to the Xilinx GQSPI controller. The helper functions are based on Xilinx's QSPIPSU flash interrupt example.
* spec: Install NandPsu headers correctlyKinsey Moore2023-01-261-1/+1
| | | | | These headers were mistakenly placed in the root of the installed BSP include directory. They should be in dev/nand.
* build: Add dl11 to libdl test exclude listSebastian Huber2023-01-241-0/+1
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* testsuites/libtest/dl11: Add DL test for TLSKinsey Moore2023-01-202-0/+40
| | | | | This adds a test verifying basic TLS functionality in loadable modules now that at least one architecture supports it.
* spec: Fix Xilinx support YAML licensesKinsey Moore2023-01-197-7/+7
| | | | This should use the CC 4.0 license to match the rest of the tree.
* build: Fix copyright statement formatSebastian Huber2023-01-171-1/+1
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* build: Remove bogus attributeSebastian Huber2023-01-171-1/+0
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* build: Use enabled by for defaultsSebastian Huber2023-01-17818-2749/+2984
| | | | | | | | | | | | | | Merge the "default" and "default-by-variant" attributes. Use an "enabled-by" expression to select the default value based on the enabled set. This makes it possible to select default values depending on other options. For example you could choose memory settings based on whether RTEMS_SMP is enabled or disabled. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Replace variant patterns with a listSebastian Huber2023-01-17134-210/+400
| | | | | | | | | | | Replace the variant patterns in the default-by-variant list with an explicit list of matching BSPs. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Format build itemsSebastian Huber2023-01-17154-544/+540
| | | | | Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a custom representer for integer default values to format all build items.
* build: Add reason to test state definitionsSebastian Huber2023-01-1753-643/+824
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* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-121-2/+2
| | | | | | | | Low-end configurations may want to have the HTIF support removed. Enable the option by default. Fix formatting. Fix node validity checks. Updates #4779.
* bsps: Move ZynqMP-specific info into the BSPKinsey Moore2023-01-043-42/+0
| | | | | | The address of the nandpsu peripheral is specific to the ZynqMP SoC and not relevant to other devices that might have one or more instances of this peripheral.
* bsps: Import Xilinx NAND driverKinsey Moore2022-12-234-0/+71
| | | | | | | | | | This adds Xilinx's driver for the Xilinx NAND controller embedded in the ZynqMP SoC. Within that device alone, it is possible to access this peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added to the hardware ZynqMP BSPs since QEMU does not support emulation of this peripheral. This driver supports polled operation only. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/dev/nand/VERSION.
* bsps: Import Xilinx support codeKinsey Moore2022-12-237-0/+176
| | | | | | | | | This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
* spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000Hesham Almatary2022-12-231-6/+0
| | | | | | | To follow other RISC-V-based OSes conventions. Delete generic BSPs that start at 0x70000000 as BSPs are now medany by default. Updates #4775
* spec/build/riscv: Default rv64* BSPs to medany cmodelHesham Almatary2022-12-234-68/+2
| | | | | | | | | | | | | | | Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x70000000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal programs that start at 0x80000000. Further, testing now has to account for an extra parameter (medany or not) that doubles the number of BSPs need to be tested. This commit defaults all RV64 BSPs to use medany code model to allow starting all BSPs at 0x80000000. BSPs that require different code models and/or start addresses are custom and need to add their own entries. Updates #4775
* bsp/atsam: Allow to use custom SDRAMChristian Mauderer2022-12-151-5/+16
| | | | | | | | | | | With the old build system in RTEMS 5 that was possible by just overwriting BOARD_Sdram_Config and setting a custom ATSAM_MEMORY_SDRAM_SIZE during building the BSP. In the new build system that ATSAM_MEMORY_SDRAM_SIZE is set exclusively by the selected SDRAM chip. This patch adds the possibility to specify a "custom-0x100000" or similar as SDRAM type where the number gives the SDRAM size.
* bsps/atsam: Add NULL pointer protectionChristian Mauderer2022-12-154-2/+27
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* config: Add CONFIGURE_RECORD_INTERRUPTS_ENABLEDSebastian Huber2022-12-022-0/+2
| | | | | | | | This enables the tracing of interrupt entry/exit events through an application configuration option. The interrupt processing can be viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools. Update #4769.
* aarch64/raspberrypi: Remove duplicate filesSebastian Huber2022-12-011-3/+0
| | | | These files are already provided by "../../objirq".
* spec/beagle: Add missing spi.h installKinsey Moore2022-11-281-0/+1
| | | | | | The beagle SPI functions are unusable by applications unless this file is installed with the BSP. This ensures that the file is installed properly.
* aarch64/versal: Add UART interrupt supportChris Johns2022-11-223-0/+18
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* bsps/riscv: RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber2022-11-101-2/+2
| | | | | Increase RISCV_MAXIMUM_EXTERNAL_INTERRUPTS to 128 to support recent Qemu versions by default.
* zynqmp: Add support for the CFC-400XKinsey Moore2022-11-0911-0/+61
| | | | | | | | This adds a BSP variant for the ZynqMP BSP family to support the Innoflight CFC-400X platform. To properly support the CFC-400X, device trees were added to the ZynqMP platform due to both the optional management interface as well as alternate physical configuration of the ethernet interfaces.
* build: Disable can01 for small memory BSPsSebastian Huber2022-11-071-0/+1
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* bsps/arm/beagle/dcan: Added DCAN supportPrashanth S2022-10-301-0/+2
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* cpukit/dev/can: Added CAN supportPrashanth S2022-10-303-0/+28
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* score: INTERNAL_ERROR_IDLE_THREAD_STACK_TOO_SMALLSebastian Huber2022-10-142-0/+22
| | | | | | | Ensure that the IDLE storage allocator did allocate a suffiently large area. Update #3835. Update #4524.
* config: Add CONFIGURE_IDLE_TASK_STORAGE_SIZESebastian Huber2022-10-143-0/+22
| | | | | | | | | | | | By default, allocate the IDLE task storage areas from the RTEMS Workspace. This avoids having to estimate the thread-local storage size in the default configuration. Add the application configuration option CONFIGURE_IDLE_TASK_STORAGE_SIZE to request a static allocation of the task storage area for IDLE tasks. Update #3835. Update #4524.
* score: INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILEDSebastian Huber2022-10-142-0/+22
| | | | | | Add the INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED fatal error in case the creation of an idle thread fails. This may happen due to a failing create extension provided by the application.
* build: Enable RISCV_BOOT_HARTID only for riscvSebastian Huber2022-10-131-1/+1
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* bsp/aarch64: Add new Raspberry Pi 4B BSPMohd Noor Aman2022-10-043-0/+175
| | | | | | | | | | | | | | | | | This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
* validation: Remove unused test suiteSebastian Huber2022-09-282-21/+0
| | | | Update #3716.
* rtems: Add rtems_clock_get_ticks_since_boot() functionSebastian Huber2022-09-231-0/+1
| | | | | This function was declared, however, a definition was missing. Add a validation test for it.
* build: Install SHA header filesSebastian Huber2022-09-221-0/+3
| | | | Update #3719.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-2012-3/+87
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* spec/build/bsps: Add dtb supportPadmarao Begari2022-09-202-0/+39
| | | | Add dtb and dtb header path configurable build option
* bsp/tms570: Fix TMS570_USE_HWINIT_STARTUPSebastian Huber2022-09-203-3/+19
| | | | Make sure only one module is built which defines bsp_start_hook_0().
* bsp/tms570: Add -mbe32 to LINKFLAGSSebastian Huber2022-09-202-0/+19
| | | | | | | | | | | | | | | | There is not just big-endian on ARM. We have two variants BE32 (obsolete) and BE8. The Cortex-R5F processor supports only BE8, however, some TMS570 variants are BE32 internally. In GCC 8 and later, the --be8 option is passed to the linker based on the selected architecture or CPU. Use BE32 by default for the TMS570 BSP. In GCC, see: commit 63d03dcecdafe34715282a5155cfc2162375feca Author: Richard Earnshaw <rearnsha@arm.com> Date: Mon Jul 3 13:22:05 2017 +0000 [arm] Clean up generation of BE8 format images.
* validation: Test deadlock detection special caseSebastian Huber2022-09-121-0/+1
| | | | Update #3716.
* bsp/qoriq: Enable VRSAVE optimizationSebastian Huber2022-09-081-0/+2
| | | | Close #4712.
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-0613-0/+282
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+1
| | | | | Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
* validation: CONFIGURE_SCHEDULER_TABLE_ENTRIESSebastian Huber2022-09-051-0/+1
| | | | | | Test this option in a configuration with only one processor. Update #3716.
* validation: Refine basedefs specificationSebastian Huber2022-09-052-1/+18
| | | | Update #3716.
* bsps/xilinx/versal: Add Cadence I2C driver supportChris Johns2022-08-256-0/+63
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* bsps/amd64: remove -Werror from ABI flagsStephen Clark2022-08-231-1/+0
| | | | The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
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