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* bsps/riscv: RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber2022-11-101-2/+2
| | | | | Increase RISCV_MAXIMUM_EXTERNAL_INTERRUPTS to 128 to support recent Qemu versions by default.
* zynqmp: Add support for the CFC-400XKinsey Moore2022-11-0911-0/+61
| | | | | | | | This adds a BSP variant for the ZynqMP BSP family to support the Innoflight CFC-400X platform. To properly support the CFC-400X, device trees were added to the ZynqMP platform due to both the optional management interface as well as alternate physical configuration of the ethernet interfaces.
* build: Disable can01 for small memory BSPsSebastian Huber2022-11-071-0/+1
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* bsps/arm/beagle/dcan: Added DCAN supportPrashanth S2022-10-301-0/+2
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* cpukit/dev/can: Added CAN supportPrashanth S2022-10-303-0/+28
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* score: INTERNAL_ERROR_IDLE_THREAD_STACK_TOO_SMALLSebastian Huber2022-10-142-0/+22
| | | | | | | Ensure that the IDLE storage allocator did allocate a suffiently large area. Update #3835. Update #4524.
* config: Add CONFIGURE_IDLE_TASK_STORAGE_SIZESebastian Huber2022-10-143-0/+22
| | | | | | | | | | | | By default, allocate the IDLE task storage areas from the RTEMS Workspace. This avoids having to estimate the thread-local storage size in the default configuration. Add the application configuration option CONFIGURE_IDLE_TASK_STORAGE_SIZE to request a static allocation of the task storage area for IDLE tasks. Update #3835. Update #4524.
* score: INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILEDSebastian Huber2022-10-142-0/+22
| | | | | | Add the INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED fatal error in case the creation of an idle thread fails. This may happen due to a failing create extension provided by the application.
* build: Enable RISCV_BOOT_HARTID only for riscvSebastian Huber2022-10-131-1/+1
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* bsp/aarch64: Add new Raspberry Pi 4B BSPMohd Noor Aman2022-10-043-0/+175
| | | | | | | | | | | | | | | | | This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in 64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM BSP. Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently. Mini-UART is not supported. Mini-UART is default UART on the board so it needs to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support for additional 4 PL011-UARTs on the board. The raspberrypi.h includes many of the address required for the future development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
* validation: Remove unused test suiteSebastian Huber2022-09-282-21/+0
| | | | Update #3716.
* rtems: Add rtems_clock_get_ticks_since_boot() functionSebastian Huber2022-09-231-0/+1
| | | | | This function was declared, however, a definition was missing. Add a validation test for it.
* build: Install SHA header filesSebastian Huber2022-09-221-0/+3
| | | | Update #3719.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-2012-3/+87
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* spec/build/bsps: Add dtb supportPadmarao Begari2022-09-202-0/+39
| | | | Add dtb and dtb header path configurable build option
* bsp/tms570: Fix TMS570_USE_HWINIT_STARTUPSebastian Huber2022-09-203-3/+19
| | | | Make sure only one module is built which defines bsp_start_hook_0().
* bsp/tms570: Add -mbe32 to LINKFLAGSSebastian Huber2022-09-202-0/+19
| | | | | | | | | | | | | | | | There is not just big-endian on ARM. We have two variants BE32 (obsolete) and BE8. The Cortex-R5F processor supports only BE8, however, some TMS570 variants are BE32 internally. In GCC 8 and later, the --be8 option is passed to the linker based on the selected architecture or CPU. Use BE32 by default for the TMS570 BSP. In GCC, see: commit 63d03dcecdafe34715282a5155cfc2162375feca Author: Richard Earnshaw <rearnsha@arm.com> Date: Mon Jul 3 13:22:05 2017 +0000 [arm] Clean up generation of BE8 format images.
* validation: Test deadlock detection special caseSebastian Huber2022-09-121-0/+1
| | | | Update #3716.
* bsp/qoriq: Enable VRSAVE optimizationSebastian Huber2022-09-081-0/+2
| | | | Close #4712.
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-0613-0/+282
| | | | | | | | | | | | | | | | | | | | Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the following NOEL-V FPGA example design ranges available from Cobham Gaisler. Follow the links for free bit-streams, DTS/DTB, user's manuals and quick-start guides: - NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7) - NOEL-PF-EX (https://www.gaisler.com/NOEL-PF) - NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU) Uses the shared GRLIB APBUART console driver "apbuart_termios.c". APBUART devices are probed using device tree. Closes #4225.
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+1
| | | | | Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
* validation: CONFIGURE_SCHEDULER_TABLE_ENTRIESSebastian Huber2022-09-051-0/+1
| | | | | | Test this option in a configuration with only one processor. Update #3716.
* validation: Refine basedefs specificationSebastian Huber2022-09-052-1/+18
| | | | Update #3716.
* bsps/xilinx/versal: Add Cadence I2C driver supportChris Johns2022-08-256-0/+63
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* bsps/amd64: remove -Werror from ABI flagsStephen Clark2022-08-231-1/+0
| | | | The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
* bsps/xilinx/versal: Remove IPL32 BSPs, add aiedge and change defaultsChris Johns2022-08-2310-110/+42
| | | | | | | | | | | - Versal has IO mapped to the upper 64bit address space and needs full 64bit addresses. - Add xilinx_versal_aiedge for custom hardware - Make the hardware settings the defaults and qemu as variants Closes #4693
* spec/librtemscpu: Fix installed headersChris Johns2022-08-222-2/+1
| | | | | | | | - pci.h is only for sparc - keyimpl.h is not referenced and so not needed Updates #4705
* spec/bsps/aarch64: Install ELF machine types for libdlChris Johns2022-08-221-0/+3
| | | | Updates #4705
* spec/bsps: Do not install tm27.hChris Johns2022-08-2290-90/+0
| | | | Updates #4705
* build/cpukit: Add confdefs/face.h to install ruleDuc Doan2022-08-111-0/+1
| | | | Updates #4691
* Add support for CONFIGURE_POSIX_TIMERS_FACE_BEHAVIORJoel Sherrill2022-08-102-0/+22
| | | | | | | | | This adds the configure option CONFIGURE_POSIX_TIMERS_FACE_BEHAVIOR which allows the application to choose whether to have the POSIX timer_create() function follow the behavior defined by POSIX or the FACE Technical Standard. Updates #4691.
* libdl: Refactor shared code in ARM and AArch64Ryan Long2022-08-082-0/+2
| | | | | | | | rtl-mdreloc-arm.c was used as the basis for rtl-mdreloc-aarch64.c. This lead to some code being shared by the two files. The code was consolidated into rtl-unwind-arm.c. Closes #4686
* build: Install <rtems/score/gcov.h>Sebastian Huber2022-08-041-0/+1
| | | | Update #4670.
* libmisc/shell: Add an 'rtems' command to report a running buildChris Johns2022-08-031-0/+1
| | | | - Report version, cpu, bsp, tools and options.
* cpukit/libdl: Add support for AArch64Ryan Long2022-07-293-0/+18
| | | | | | rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
* aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns2022-07-281-5/+43
| | | | | | | | | | | - Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
* build: Move RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber2022-07-264-19/+3
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* score: Remove PRIORITY_PSEUDO_ISR thread prioritySebastian Huber2022-07-261-0/+1
| | | | | | | | | | | | | | | The uniprocessor schedulers had some special case logic for the PRIORITY_PSEUDO_ISR priority. Tasks with a priority of PRIORITY_PSEUDO_ISR were allowed to preempt a not preemptible task. If other higher priority task are made ready while a PRIORITY_PSEUDO_ISR task preempts a not preemptible task, then the other tasks run before the not preemptible task. This made the RTEMS_NO_PREEMPT mode ineffective. Remove the PRIORITY_PSEUDO_ISR special case logic. This simplifies the uniprocessor schedulers. Move the uniprocessor-specific scheduler support to the new header file <rtems/score/scheduleruniimpl.h>. Close #2365.
* sptests/spstdc17: New testSebastian Huber2022-07-252-0/+24
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* imfs: Add <rtems/imfsimpl.h>Sebastian Huber2022-07-251-0/+1
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* bsps/microblaze: Fix build option definition orderAlex White2022-07-253-4/+2
| | | | | | The build option definitions were rearranged such that the option definitions used in the linker script were not available. This caused linker errors when building.
* sptls04: Test an external TLS objectSebastian Huber2022-07-211-0/+1
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* bsps/riscv: Sort .noinit* sectionsSebastian Huber2022-07-201-1/+1
| | | | | | | | Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
* build: Add missing cxxflagsSebastian Huber2022-07-2082-0/+82
| | | | Update #4670.
* spunlimited01: New testSebastian Huber2022-07-182-0/+22
| | | | Update #4677.
* score: Extend memory dirty/zero actionsSebastian Huber2022-07-151-0/+1
| | | | | | Dirty or zero also the part of the .noinit section used by RTEMS. Close #4678.
* irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber2022-07-1218-6/+171
| | | | | | | Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
* validation: Test thread idle bodiesSebastian Huber2022-07-071-0/+1
| | | | Update #3716.
* validation: Always test spurious interruptsSebastian Huber2022-07-072-3/+3
| | | | Update #3716.
* bsps/aarch64: Use MMU pages appropriatelyKinsey Moore2022-07-064-12/+12
| | | | | | | | | There were two bugs with MMU page use that were partially hiding each other. The linker script page table section was 4x the size it needed to be and the page table allocation routine was allocating pages PTRSIZE times larger than it needed to. On ILP32, this resulted in incorrect but functional allocation. On LP64, this resulted in allocation failures earlier than expected.
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