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* bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval BSPKarel Gardas2022-05-272-1/+5
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: provide linkcmds for SRAM, FLASH_SDRAM and SRAM_SDRAM linkingKarel Gardas2022-05-275-2/+156
| | | | Sponsored-By: Precidata
* bsps/stm32h7: add and enable test set exclusion for stm32h757i-eval BSPKarel Gardas2022-05-272-0/+21
| | | | Sponsored-By: Precidata
* bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval BSPKarel Gardas2022-05-279-2/+16
| | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h757i-eval BSPKarel Gardas2022-05-277-0/+54
| | | | | | | | | | This is minimalist configuration for the stm32h757i-eval BSP provided here. The only general enhancement worth mention is boot core configuration which is needed here as this is the first dual-core board supported by stm32h7 BSP family and we need to choose boot core in order to get C files compiling well. Sponsored-By: Precidata
* bsp/stm32h7: copy system files to nucleo-h743zi board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: copy system files to stm32h743i-eval board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: copy system files to stm32h7b3i-dk board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: move compilation of system files to BSPs spec. filesKarel Gardas2022-05-164-8/+18
| | | | | | The patch is done in preparation for stm32h7 BSP tree refactoring. Sponsored-By: Precidata
* build: Remove obsolete test excludesSebastian Huber2022-04-0613-52/+0
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* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-062-0/+2
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* unit: Add a unit test suiteSebastian Huber2022-04-061-0/+1
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* bsp/stm32h7: Disable some tests for a variantSebastian Huber2022-04-061-0/+2
| | | | Making this BSP a small memory target is a bit coarse and could be improved.
* bsps/stm32h7: link to flash on STM32H7B3I-DKKarel Gardas2022-04-061-1/+4
| | | | | The patch is needed due to smaller SRAM and completely disabled SDRAM on the BSP variant.
* bsp/stm32h7: use appropriate STM32H7B3xxQ define for STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-1/+4
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* bsp/stm32h7: configure S(D)RAM values for STM32H7B3I-DK BSP variantKarel Gardas2022-04-056-6/+24
| | | | Caveat: SDRAM 1 is completely disabled for now.
* bsp/stm32h7: HSE clock value configuration for STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-0/+3
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* bsp/stm32h7: add flash latency configurationKarel Gardas2022-04-052-0/+21
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* bsp/stm32h7: add configuration for USART1 GPIO pins, registers and alternate ↵Karel Gardas2022-04-054-0/+63
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* bsp/stm32h7: disable UART 5, 7, 8, 9 and USART 3, 6, 10 for STM32H7B3I-DK BSPKarel Gardas2022-04-057-7/+28
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* bsp/stm32h7: add power supply configurationKarel Gardas2022-04-052-0/+21
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* bsp/stm32h7: add spec file for the STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-0/+17
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* validation: Add test suitesSebastian Huber2022-03-2413-4/+59
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* build: Exclude rcxx01 test for sh BSPsSebastian Huber2022-03-236-0/+6
| | | | There seems to be a code size increase with GCC 12.
* microblaze: Add JFFS2 AXI QSPI driverAlex White2022-03-154-0/+43
| | | | This driver has been tested with Micron NOR Flash via AXI Quad SPI.
* bsp/fvp: Use only vector table of start sectionSebastian Huber2022-03-111-0/+2
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* bsps/riscv: Support .riscv.attributesSebastian Huber2022-02-251-1/+1
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* spec/microblaze: Use configurable RAM sizeKinsey Moore2022-02-233-1/+24
| | | | | | When committed, the MicroBlaze RAM size was hard-coded to 16MB. This changes the default to 256MB and sets the KCU105 BSPs to 2GB since that is what the board has on it.
* cpukit/microblaze: Add debug vector and handlerKinsey Moore2022-02-041-0/+1
| | | | | | This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger.
* cpukit/microblaze: Add exception frameworkKinsey Moore2022-02-041-1/+0
| | | | | | | | | | | This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
* microblaze: Add support for libbsd networkingAlex White2022-02-019-1/+139
| | | | | This includes fixes and improvements necessary to get libbsd networking running.
* microblaze: Add support for libbsd.Jennifer Averett2022-02-011-0/+2
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* sparc: Mark dl06 as expected failSebastian Huber2022-01-281-1/+3
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* bsps: Default to CPU counter benchmark timerSebastian Huber2022-01-1521-21/+21
| | | | | | Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
* bsp/imx7: dl06 fails expectedlySebastian Huber2022-01-142-0/+15
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* aarch64: always boot into EL1NSGedare Bloom2022-01-125-28/+0
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* build: Fix build item formatSebastian Huber2022-01-112-8/+6
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* bsp/mrm332: Fix TLS support in linker command fileSebastian Huber2021-12-221-2/+0
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* Remove powerpc/haleakala boardJoel Sherrill2021-12-176-136/+0
| | | | Closes #4302.
* bsps/arm: Add missing Cache Manager source fileSebastian Huber2021-12-132-0/+2
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* spec: Update location of cadence I2CKinsey Moore2021-12-092-3/+7
| | | | | | When the cadence I2C code was moved to a shared directory, the references were updated but the install locations weren't. This updates the install locations to match what out-of-tree applications expect.
* libc: Optimize malloc() initializationSebastian Huber2021-11-3010-0/+10
| | | | | | | | | | | | | | | | The BSPs provide memory for the separate C Program Heap initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the separate C Program Heap and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs. Change licence to BSD-2-Clause according to file history. Update #3053.
* score: Optimize Workspace Handler initializationSebastian Huber2021-11-3010-0/+10
| | | | | | | | | | | | The BSPs provide memory for the workspace initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the workspace handler and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs.
* build: Use common objects item for get memorySebastian Huber2021-11-30117-84/+210
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* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-291-3/+0
| | | | Updates #3937.
* build: Remove trailing white spaceSebastian Huber2021-11-292-2/+2
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* aarch64: Break out MMU definitionsKinsey Moore2021-11-014-0/+4
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* spec/aarch64: Enable previously unbuildable testsKinsey Moore2021-10-206-23/+0
| | | | | | | The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due to a toolchain issue preventing them from compiling correctly. The binutils version that contains the fix has been released and integrated into RSB such that these two tests now build and operate correctly.
* microblaze: Rework for RTEMS 6Alex White2021-10-1314-0/+522
| | | | | This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-213-0/+20
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-21 23:13:57 +0000