summaryrefslogtreecommitdiffstats
path: root/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml (unfollow)
Commit message (Collapse)AuthorFilesLines
2024-04-04dev/serial: Add Zynq UART kernel I/O supportSebastian Huber1-2/+0
Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a shared file.
2024-01-15bsps/arm: Use shared empty bsp_start_hook_0()Sebastian Huber1-0/+1
Update #4982.
2023-05-20Update company nameSebastian Huber1-1/+1
The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2022-08-22spec/bsps: Do not install tm27.hChris Johns1-1/+0
Updates #4705
2022-01-15bsps: Default to CPU counter benchmark timerSebastian Huber1-1/+1
Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
2021-12-13bsps/arm: Add missing Cache Manager source fileSebastian Huber1-0/+1
2021-11-30build: Use common objects item for get memorySebastian Huber1-1/+2
2021-09-21bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore1-0/+1
ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
2021-03-30bsps/shared: Add Xilinx-AXI SPI driver to wafJan Sommer1-0/+2
Updates #4321
2021-03-10bsps/xilinx_zynq: Add SPI driver to wafJan Sommer1-0/+2
Updates #4320
2021-02-26bsps: Add default rtems_get_target_hash()Sebastian Huber1-0/+1
Update #4267.
2021-02-24build: Sort source listsSebastian Huber1-2/+2
Use the Python sorted() function to sort the "source" lists.
2020-12-23bsps: Use header file for GIC architecture supportSebastian Huber1-1/+0
This avoids a function call overhead in the interrupt dispatching. Update #4202.
2020-12-10bsps/arm: Unify ARM Generic Timer optionsSebastian Huber1-4/+4
Update #4202.
2020-12-04spec: Move zynq-uart into its own objectKinsey Moore1-0/+2
Currently, zynq-uart code is always built and has some requirements for BSPs that use it. Instead of making all BSPs satisfy that requirement or working around it by setting defaults, this moves the zynq-uart code into its own spec build object so it can be included if needed.
2020-12-04Add AArch64 ZynpMP BSPKinsey Moore1-1/+1
This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC (ZynqMP) family of chips. It is configured to be usable on the Qemu ZCU102 machine definition and should be almost trivially portable to ZynqMP development boards and custom hardware. It is also configured to be usable with libbsd.
2020-12-02bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore1-1/+2
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
2020-12-02bsps: Move zynq-uart to bsps/sharedKinsey Moore1-2/+0
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
2020-10-05bsps: Break out AArch32 portions of GPT driverKinsey Moore1-1/+5
This breaks AArch32-specific portions of the ARM GPT driver into their own file so that the generic code can be moved for reuse by other architectures.
2020-09-14build: Alternative build system based on wafSebastian Huber1-0/+95
Update #3818.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-09 13:56:30 +0000