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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
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This reverts commit d1d3ceb502cf4075c28a052b36630125387e1026.
Per discussions on devel@ and Discord.
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This patch adds basic support for the following boards:
xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20
N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
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QEMU is known to fail certain tests intermittently due to clock tick
delivery issues. This defines those tests as intermittent for BSPs
intended to run on QEMU alone.
Updates #4922
Updates #4072
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Merge the "default" and "default-by-variant" attributes. Use an
"enabled-by" expression to select the default value based on the enabled
set. This makes it possible to select default values depending on other
options. For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a
custom representer for integer default values to format all build items.
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Updates #4705
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OPTIMIZATION_FLAGS must be defined before /build/bsp/bspopts is processed.
Update #4670.
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Propagate the group defined cppflags, cflags, and cxxflags from parent groups
to child items through the build item context.
Update #4670.
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Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
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When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
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Prefix the BSP family name with "bsps/" to make it distinct to the BSP
variant names.
Update #4468.
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- Optionally add support for 'default-by-family' to allow
option to be set by a family and so all related BSPs
Close #4468
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Updates #4321
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Updates #4320
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Update #4267.
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Use the Python sorted() function to sort the "source" lists.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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- Disabled by default
- Enable using ARM_MMU_USE_SMALL_PAGES option
Close 4192.
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Currently, zynq-uart code is always built and has some requirements for
BSPs that use it. Instead of making all BSPs satisfy that requirement or
working around it by setting defaults, this moves the zynq-uart code
into its own spec build object so it can be included if needed.
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This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
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Update #3818.
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