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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
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Propagate the group defined cppflags, cflags, and cxxflags from parent groups
to child items through the build item context.
Update #4670.
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Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a clustered structure in which multiple GICv3
instances are present. For example, two clusters of two Cortex-R52 cores where
each cluster has a dedicated GICv3 instance.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
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This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
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This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
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This UART driver is now needed for BSPs other than ARM.
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Update #3818.
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