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* aarch64: always boot into EL1NSGedare Bloom2022-01-121-2/+0
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* build: Fix build item formatSebastian Huber2022-01-112-8/+6
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* spec: Update location of cadence I2CKinsey Moore2021-12-091-1/+3
| | | | | | When the cadence I2C code was moved to a shared directory, the references were updated but the install locations weren't. This updates the install locations to match what out-of-tree applications expect.
* build: Use common objects item for get memorySebastian Huber2021-11-302-1/+2
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* aarch64: Break out MMU definitionsKinsey Moore2021-11-011-0/+1
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* spec/aarch64: Enable previously unbuildable testsKinsey Moore2021-10-202-7/+0
| | | | | | | The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due to a toolchain issue preventing them from compiling correctly. The binutils version that contains the fix has been released and integrated into RSB such that these two tests now build and operate correctly.
* cpukit: Add AArch64 SMP SupportKinsey Moore2021-09-213-0/+20
| | | | This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
* bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore2021-09-211-0/+1
| | | | | | | ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
* bsps/zynqmp: Added I2C support for ZynqMPStephen Clark2021-09-095-0/+87
| | | | Added I2C drivers for ZynqMP and updated build system accordingly.
* build: Merge default-by-family into by-variantSebastian Huber2021-08-188-8/+0
| | | | | | | Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. Update #4468.
* build: Use BSP family for optionsChris Johns2021-07-158-0/+8
| | | | | | | - Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
* Revert "bsps/zynqmp: Allow any or all CGEMs to be enabled"Kinsey Moore2021-07-015-72/+0
| | | | | | | This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42. This type of configuration does not belong in RTEMS and is better constrained to libbsd where the defines are actually being used.
* bsps/zynqmp: Allow any or all CGEMs to be enabledKinsey Moore2021-06-285-0/+72
| | | | | | | Provide the options necessary to enable any combination of CGEM ethernet interfaces in LibBSD. The default is still CGEM3, so this should continue to operate as expected on typical Zynq Ultrascale+ MPSoC development hardware.
* bsps/aarch64: replace boot options with asm switch codeGedare Bloom2021-06-241-2/+0
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* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-0/+2
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* spec/aarch64: Add BSPs for real ZynqMP hardwareKinsey Moore2021-05-277-2/+85
| | | | | | | Add the BSPs for running on the ZU3EG Ultrascale+ Zynq MPSoC and alter the option defaults necessary for them to run properly using the standard BOOT.BIN configured for PetaLinux that comes in the Out-of-Box package.
* bsps/aarch64: Add MMU driver to relax alignmentKinsey Moore2021-05-274-4/+16
| | | | | | | | | | | | | | | Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the toolchain and in the BSPs themselves. In writing this driver, it was found that the synchronous exception handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to avoid thread stack misalignments in RTEMS_DEBUG mode. This is now avoided by exactly preserving thread mode stack and flags and the new implementation is compatible with the draft information provided on the mailing list covering the Exception Management API.
* bsps/shared: Add Xilinx-AXI SPI driver to wafJan Sommer2021-03-301-0/+2
| | | | Updates #4321
* bsps/xilinx_zynq: Add SPI driver to wafJan Sommer2021-03-101-0/+2
| | | | Updates #4320
* spec/aarch64: Enable previously disabled testsAlex White2021-03-081-9/+1
| | | | | This enables several testsuites that were initially disabled during development.
* spec/aarch64: Rename ZynqMP QEMU BSPsKinsey Moore2021-03-053-3/+3
| | | | | | The current ZynqMP BSPs don't have _qemu in their name as do all other RTEMS BSPs that are specifically made to run on QEMU. This fixes the naming for those ZynqMP BSP variants for easier identification.
* spec/aarch64: Remove sp37 from intermittent testsAlex White2021-03-051-1/+0
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* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-1/+0
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* validation: Fix for 64-bit targetsSebastian Huber2021-03-041-3/+0
| | | | Closes #4179.
* bsps: Add default rtems_get_target_hash()Sebastian Huber2021-02-261-0/+1
| | | | Update #4267.
* build: Sort source listsSebastian Huber2021-02-241-5/+5
| | | | Use the Python sorted() function to sort the "source" lists.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-1/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* spec: Move zynq-uart into its own objectKinsey Moore2020-12-041-0/+2
| | | | | | | Currently, zynq-uart code is always built and has some requirements for BSPs that use it. Instead of making all BSPs satisfy that requirement or working around it by setting defaults, this moves the zynq-uart code into its own spec build object so it can be included if needed.
* Add AArch64 ZynpMP BSPKinsey Moore2020-12-0413-0/+433
This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC (ZynqMP) family of chips. It is configured to be usable on the Qemu ZCU102 machine definition and should be almost trivially portable to ZynqMP development boards and custom hardware. It is also configured to be usable with libbsd.
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