| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
|
|
| |
We must obtain the processor ID after interrupts are disabled since a
non-optimizing compiler may store the value on the stack and read it
back.
|
| |
|
|
|
|
| |
Add and use _Per_CPU_Lock_release().
|
| |
|
| |
|
| |
|
| |
|
|
|
|
|
|
| |
Add and use _Objects_Put_without_thread_dispatch(). These two functions
pair with the _Objects_Get() function. This helps to introduce object
specific SMP locks to avoid lock contention.
|
|
|
|
|
| |
Provide SMP support. The ISR disable/enable is not enough to ensure
mutual exclusion for SMP configurations.
|
|
|
|
|
| |
Align ISR disable/enable sequence in _Objects_Get_isr_disable() with
thread dispatch disable/enable sequence in _Objects_Get().
|
|
|
|
|
|
|
| |
Move thread dispatch declarations and inline functions to new header
<rtems/score/threaddispatch.h> to make it independent of the
Thread_Control structure. This avoids a cyclic dependency in case
thread dispatch functions are used for the object implementation.
|
| |
|
| |
|
|
|
|
|
| |
The _Thread_Initialize() function has nothing to do with thread
dispatching it simply initializes the thread control.
|
| |
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move the SMP lock implementation to the CPU port. An optimal SMP lock
implementation is highly architecture dependent. For example the memory
models may be fundamentally different.
The new SMP lock API has a flaw. It does not provide the ability to use
a local context for acquire and release pairs. Such a context is
necessary to implement for example the Mellor-Crummey and Scott (MCS)
locks. The SMP lock is currently used in _Thread_Disable_dispatch() and
_Thread_Enable_dispatch() and makes them to a giant lock acquire and
release. Since these functions do not pass state information via a
local context there is currently no use case for such a feature.
|
|
|
|
| |
Mark rtems_smp_secondary_cpu_initialize() as no return.
|
|
|
|
|
|
| |
This field is unused except for special case simulator clock drivers.
In these places use an alternative. Add and use
_Thread_Set_global_exit_status() and _Thread_Get_global_exit_status().
|
|
|
|
|
| |
Do not assume that the scheduler selects the main processor for the
initialization thread.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Delete bsp_smp_wait_for(). Other parts of the system work without
timeout, e.g. the spinlocks. Using a timeout here does not make the
system more robust.
Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The
Per_CPU_State follows the Score naming conventions. Add
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to
change and observe states.
Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer.
Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive()
functions provided by the CPU port. Use these functions in
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state().
Add prototype for _SMP_Send_message().
Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is
now performed in rtems_smp_secondary_cpu_initialize(). Issuing the
first context switch in the context of the inter-processor interrupt is
not possible on systems with a modern interrupt controller. Such an
interrupt controler usually requires a handshake protocol with interrupt
acknowledge and end of interrupt signals. A direct context switch in an
interrupt handler circumvents the interrupt processing epilogue and may
leave the system in an inconsistent state.
Release lock in rtems_smp_process_interrupt() even if no message was
delivered. This prevents deadlock of the system.
Simplify and format _SMP_Send_message(),
_SMP_Request_other_cores_to_perform_first_context_switch(),
_SMP_Request_other_cores_to_dispatch() and
_SMP_Request_other_cores_to_shutdown().
|
|
|
|
|
|
|
| |
Do not call bsp_smp_secondary_cpu_initialize() in
rtems_smp_secondary_cpu_initialize(). This allows more flexibilty in
the BSP low-level code. Specify context requirements for a call to
rtems_smp_secondary_cpu_initialize().
|
| |
|
| |
|
|
|
|
|
|
| |
Call _SMP_Handler_initialize() later and move bsp_smp_initialize() into
_SMP_Handler_initialize(). Change bsp_smp_initialize() prototype to
match integer types of calling context.
|
| |
|
|
|
|
|
|
| |
The _Per_CPU_Information is part of the BSS segment and must be zero
initialized. Some processors may already poll some per-CPU fields and
wait for a state change at this point.
|
| |
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The GNU assembler translates for example a
msr spsr, rN
into
msr SPSR_fc, rN
This would update only a subset of the register and leads to an
incomplete exceptions restore sequence resulting in system corruption.
Correct is this:
msr SPSR_fsxc, rN
|
| |
|
|
|
|
|
|
|
| |
Delete rtems_configuration_get_smp_maximum_processors(). Delete
rtems_configuration_smp_maximum_processors variable. Add
maximum_processors field to rtems_configuration_table if RTEMS_SMP is
defined. Add rtems_configuration_get_maximum_processors().
|
| |
|
| |
|
| |
|
|
|
|
| |
Add FUNCTION_THUMB_ENTRY(), FUNCTION_ENTRY() and FUNCTION_END().
|
| |
|
| |
|
|
|
|
|
|
| |
This header uses uint32_t but does not include stdint.h
This may cause problems when compiling applications that include BSP
headers that include this file (leon.h for example)
|
|
|
|
| |
The Thumb-2 instruction set as encodings for the relevant instructions.
|
| |
|
|
|
|
|
| |
i386 soft-float is no longer supported by gcc. Dropping
related code in the i386 score/cpu code.
|
| |
|
|
|
|
| |
architectures. SMP atomic port will be later.
|
|
|
|
| |
disable/enable-IRQ function simulated.
|
| |
|
| |
|
| |
|