| Commit message (Collapse) | Author | Age | Files | Lines |
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The APIC timer is calibrated by running the i8254 PIT for a fraction of a
second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the
APIC counter has ticked. The calibration can be run multiple times (determined
by APIC_TIMER_NUM_CALIBRATIONS) and averaged out.
Updates #2898.
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Updates #2898.
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Updates #2898.
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Updates #2898.
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Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.
It seems that previously the condition
CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)
was true on all CPU ports. Now, we need an additional check.
Update #3482.
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Update #3433.
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Update #3433.
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The CLINT and PLIC need some per-processor state.
Update #3433.
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Update #3433.
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Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
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Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.
Update #3433.
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Update #3433.
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Add RTEMS_PREDICT_TRUE() and RTEMS_PREDICT_FALSE() for static branch
prediction hints.
Close #3475.
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Pass current processor control as first parameter to make dependency
more explicit.
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Apparently the .word assembler directive is not the right thing on this
target.
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On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads. Use an illegal
instruction instead.
Update #3433.
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This helps to reduce the use of architecture-specific defines throughout
the code base.
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The context validation support functions _CPU_Context_validate() and
_CPU_Context_volatile_clobber() are used only by one test program
(spcontext01). Move the function declarations to the CPU port
implementation header file.
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This change was added to the FreeBSD version of this function.
This was spotted by Coverity Scan.
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Commit 8744498752ad4f0eaf9fb5640c6a0e0f2dc92fda broke the
_Scheduler_EDF_SMP_Set_affinity() implementation. We must test the
overall affinity against the online processors.
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Update #3465.
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This addition allows us to successfully run the sample hello.exe test.
Updates #2898.
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Current state:
- Basic context initialization and switching code.
- Stubbed console (empty functions).
- Mostly functional linker script (may need tweaks if we ever want to move
away from the large code model (see: CPU_CFLAGS).
- Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for
UEFI-awareness.
In short, the current state with this commit lets us boot, go through the system
initialization functions, and then call user application's Init task too.
Updates #2898.
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An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.
Update #3433.
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Update #3433.
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See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Save/restore non-volatile registers in _CPU_Context_switch().
Save/restore volatile registers in _ISR_Handler().
Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Move SREG and LREG assembler defines to <rtems/score/asm.h>.
Update #3433.
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Update #3433.
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The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.
Create separate CPU_Interrupt_frame structure.
Update #3433.
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The RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
does not mention that this is a frame pointer.
Update #3433.
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Update #3433.
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Do not clear the complete thread context. Initialize only the necessary
members. The Context_Control::is_executing member must be preserved
across _CPU_Context_Initialize() calls.
Update #3433.
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According to the RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
the stack alignment is 128 bits (16 bytes).
Update #3433.
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The current ABI says that there is no stack red zone:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."
Update #3433.
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The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).
Update #2751.
Update #3433.
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Update #3433.
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Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).
Update #3433.
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Use the atomic read and clear operation to disable interrupts.
Do not write the complete mstatus. Instead, set only the MIE bit
depending on the level parameter.
Update #3433.
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