| Commit message (Collapse) | Author | Age | Files | Lines |
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Update #2132.
Close #3140.
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Close #2133.
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Close #2132.
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Update #2132.
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Update #2133.
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In 64-bit mode, the linker must have the ability to restore the TOC
pointer after an external function call.
Update #3082.
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Update #3082.
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Update #3082.
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Update #3082.
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Fix warning on 64-bit PowerPC.
Update #3082.
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Update #3082.
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Update #3082.
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Update #3082.
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Update #3093.
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Update #3093.
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Update #3082.
Update #3085.
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This fixes some "variably modified" warnings and a clang compile error.
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The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus, from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically, the deferred floating point switch was
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context.
The floating point unit is disabled for interrupt handlers. Thus, in case
an interrupt handler uses the floating point unit then this will result in a
trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT).
In uniprocessor configurations, a lazy floating point context switch is
used. In case an active floating point thread is interrupted (PSR[EF] == 1)
and a thread dispatch is carried out, then this thread is registered as the
floating point owner. When a floating point owner is present during a
context switch, the floating point unit is disabled for the heir thread
(PSR[EF] == 0). The floating point disabled trap checks that the use of the
floating point unit is allowed and saves/restores the floating point context
on demand.
Update #3077.
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Add new fatal error INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT.
Update #3077.
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Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH.
Update comment.
Update #3077.
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Update #3077.
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Update #3059.
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This patch adds NOP instructions to prevent instruction sequences
that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009:
"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"
for more information.
The sequences are only modified if __FIX_LEON3FT_B2BST is defined.
The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc,
and -mfix-ut699 GCC flags that prevents the sensitive sequences from
being generated.
Update #3057.
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Update #3059.
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Close #3071.
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Ensure that the thread processor affinity fits the new scheduler
instance.
Update #3059.
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Update #3059.
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This allows scheduler implementations to easily access
scheduler-specific data.
Update #3059.
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Update #3059.
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The set of online processors must be a subset of the thread processor
affinity for the schedulers without arbitrary processor affinity support
to avoid problems in case of processor addition and removal.
Update #3059.
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Update #3059.
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Update #3059.
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Replace the simple processor count with the processor set owned by the
scheduler instance.
Update #3059.
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Update #3059.
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Update #3059.
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Update #3059.
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Implement the Processor_mask via <sys/bitset.h>. Provide
_Processor_mask_To_uint32_t() to enable its use in device specific
routines, e.g. interrupt affinity register in an interrupt controller.
Update #3059.
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Right after a "msr basepri_max, %[basepri]" instruction an interrupt
service may still take place (observed at least on Cortex-M7). However,
pendable service calls that are activated during this interrupt service
may be delayed until interrupts are enable again. The
_ARMV7M_Pendable_service_call() did not check that a thread dispatch is
allowed. Move this test from _ARMV7M_Interrupt_service_leave() to
_ARMV7M_Pendable_service_call().
Update #3060.
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Update #3060.
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Update #3056.
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Update #3056.
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In SMP configurations, add a red-black tree node to Scheduler_Node to
enable an EDF scheduler implementation.
Update #3056.
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Account for legacy AltiVec context.
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Do not zero the GPR2 in the thread context via dcbz instructions. Bug
was introduced by 32b4a0c42704f0076da8e2d5411290f55d1b2965.
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This task variable is superfluous since we use thread-local storage now.
Update #2289.
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Update #2468.
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Update #2468.
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