| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
| |
* src/coremutexsurrender.c: Use holder thread not executing
thread because even though they may and often are the same
it is not guaranteed unless the proper attribute is set.
|
|
|
|
|
|
|
|
| |
* include/rtems/score/coremsg.h, src/coremsgsubmit.c: Add a new
return status to account for blocking sends. Otherwise, the
caller will think that the returned message status will have
the ultimate results of the operation. If the send times out,
the final status will be in the return_code of the thread.
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cpu_asm.S: This patch was co-developed with Eric Norum
<eric.norum@usask.ca>. It closes a one instruction window
on some m68k CPU cores. It fixes symptoms seen as:
1) No more `interrupt handler invoked twice for
a single interrupt'.
2) No more `lockup when mc68360 CPM and PIT interrupts
are at different levels'.
It does insert a little more overhead on machines without hardware
interrupt stacks but correctness has a price.
|
|
|
|
|
|
|
|
| |
* include/rtems/score/coremsg.h, inline/rtems/score/coremsg.inl,
src/coremsgsubmit.c: Unblocking message queue operations should
NOT use _Thread_Executing for return status since it is permissible
to invoke message send operations from an ISR. This was reported
by Suvrat Gupta <suvrat@utstar.com>.
|
|
|
|
| |
* cpu.c: Fixed typo.
|
|
|
|
|
|
| |
* macros/rtems/score/coresem.inl, inline/rtems/score/coresem.inl:
Cut and paste problem incorrectly enabled interrupts twice with
the first time being too early.
|
|
|
|
|
|
|
| |
* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
|
|
|
|
|
|
|
|
| |
* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
|
|
|
|
|
| |
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
|
|
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
|
|
|
|
|
| |
* include/rtems/score/.cvsignore: Add stamp-h, cpuopts.h,
cpuopts.h.in, cpuopts-tmp.h.
|
|
|
|
| |
* rtems/score/cpu.h: Remove #undef __STRICT_ANSI__.
|
|
|
|
|
|
| |
* cpu_asm.S: Merged patches from Gregory Menke
<Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
stack usage and include nops in the delay slots.
|
|
|
|
|
|
| |
* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
|
|
|
|
| |
* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
|
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
Removed unused variable _CPU_Thread_dispatch_pointer
and cleaned numerous comments.
|
|
|
|
|
|
|
| |
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
|
|
|
|
|
| |
* Makefile.am, rtems/score/Makefile.am:
Apply include_*HEADERS instead of H_FILES.
|
|
|
|
|
|
| |
* include/rtems/Makefile.am, include/rtems/score/Makefile.am,
inline/rtems/score/Makefile.am, macros/rtems/score/Makefile.am
Apply include_*HEADERS instead of H_FILES.
|
|
|
|
|
| |
* src/objectextendinformation.c: Added include of string.h to
eliminate warning.
|
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Bug report from Peter Mueller
<peter.o.mueller@gmx.de> because of not correcting for the ISR
vector table now being allocated from the workspace.
|
|
|
|
|
| |
* rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
register constraints from "general" to "register".
|
|
|
|
|
| |
* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
to make it easier to conditionalize the code for various ISA levels.
|
|
|
|
|
| |
* src/threadinitialize.c: Fix my bad hack of Ralf's fp_area
warning removal patch. :(
|
|
|
|
| |
* src/threadinitialize.c: Removed warning.
|
|
|
|
|
|
|
|
| |
* idtcpu.h: Commented out definition of "wait". It was stupid to
use such a common word as a macro.
* rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
* rtems/score/mips.h: Added include of <idtcpu.h>.
* rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
|
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
|
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Modify to properly dereference _ISR_Vector_table
now that it is dynamically allocated.
|
|
|
|
| |
* ChangeLog: Removed duplicate entry.
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
|
|
|
|
| |
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
|
|
|
|
|
| |
* src/isr.c: Allocate the _ISR_Vector_table all the time not just when
we are allocating an interrupt stack.
|
|
|
|
|
|
| |
* cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
Previous code resulting in the interrupted immediately returning
to the caller of the routine it was inside.
|
|
|
|
|
| |
* cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
because it has not been allocated yet.
|
|
|
|
|
|
| |
* cpu.c: Do not read or write raw interrupt vector table if
we are on a CPU that does not have a %vbr register and the
BSP is configured as having the table in ROM.
|
|
|
|
|
|
| |
* include/rtems/score/isr.h, src/isr.c: Allocate it from the
workspace rather than explicitly declaring it. This allows
the size to be a non-constant from the perspective of score/cpu.
|
|
|
|
|
|
|
|
| |
* cpu.c: Removed duplicate declaration for _ISR_Vector_table.
* cpu_asm.S: Removed assembly language to vector ISR handler
on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
longer a constant -- get the real value from libcpu.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
|
|
|
|
| |
* cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning.
|
|
|
|
|
| |
* rtems/score/cpu.h: When mips ISA level is 1, registers in the
context should be 32 not 64 bits.
|
|
|
|
|
|
|
|
| |
* macros/rtems/score/coresem.inl: Removed comments since convention
calls for comments to be in inline versin.
* macros/rtems/score/object.inl (Objects_Get_local_object): Fixed
style to use _ prefix on variable names and use parentheses.
* macros/rtems/score/object.inl (_Objects_Namespace_remove): Added.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* General effort to make things compile with macros not inlines
* inline/rtems/score/coremutex.inl: Added comment indicating
for macros there is another copy of
_CORE_mutex_Seize_interrupt_trylock() in src/coremutexseize.c.
* src/coremutexseize.c: Added body of
_CORE_mutex_Seize_interrupt_trylock() for macro case.
* macros/rtems/score/coremutex.inl: Added prototype for
_CORE_mutex_Seize_interrupt_trylock() since there is a real
body when macros are enabled.
* macros/rtems/score/coresem.inl: Added macro implementation of
_CORE_semaphore_Seize_isr_disable.
* macros/score/Makefile.am: Fixed typos.
* rtems/score/address.inl: Correct macro implementation of
_Addresses_Is_aligned() so it would compile.
* macros/rtems/score/coremsg.inl: Added closing parentheses.
|
|
|
|
|
|
| |
* cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
correct name of _CPU_Context_switch_restore. Added dummy
version of exc_utlb_code() so applications would link.
|
|
|
|
|
|
|
|
|
| |
* src/heapallocate.c: Do not allow the size to overflow when
adjusting it. A test allocated a stack of -1 (~0). This
actually resulted in a stack being allocated but with a
size of 0xb. The allocator did not test the size to see if
it rolled through 0 and so allowed the allocation to happen, the
thread to get created. The task crashed as you would expect.
|
|
|
|
| |
* cpu_asm.S: Fix for CPUs with FPU revision B or C.
|
|
|
|
|
|
| |
* cpu.c, rtems/cpu/sparc.h: Make floating point optional based
on gcc arguments. Do not initialize FP context if there is
no FPU. Flush instruction cache after installing RTEMS trap handler.
|
|
|
|
| |
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
|