| Commit message (Collapse) | Author | Age | Files | Lines |
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The user of the red-black tree container must now ensure that at most
one thread at once can access an instance.
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Interrupts are disabled by the caller _Thread_Change_priority() or
_Thread_Set_transient() or directly in the scheduler operation. Thus
there is no need to use protected variants.
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The r2 may be used for thread-local storage.
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This filed is only used if RTEMS_MULTIPROCESSING is defined.
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This state is necessery to implement the SLEEP(9) FreeBSD kernel API.
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Use unsigned long instead of uint_fast32_t since C11 provides only a
ATOMIC_LONG_LOCK_FREE macro constant. This makes it also possible to
use properly typed integer literals like 123UL. It is now clear which
compatible type should be used for the atomic integer.
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Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
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Delete _Atomic_Init_flag(). Change ATOMIC_INITIALIZER_FLAG into a
constant. Rename _Atomic_Clear_flag() to _Atomic_Flag_clear(). Rename
_Atomic_Test_set_flag() to _Atomic_Flag_test_and_set(). This is now in
line with the C11 schema.
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Add proper license and copyright.
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This file uses already C11 features. Include proper header file.
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Add and use CHAIN_NODE_INITIALIZER_ONE_NODE_CHAIN(),
RTEMS_CHAIN_INITIALIZER_ONE_NODE() and
RTEMS_CHAIN_NODE_INITIALIZER_ONE_NODE_CHAIN().
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The _Thread_queue_Process_timeout() operation had several race
conditions in the event of nested interrupts. Protect the critical
sections via disabled interrupts.
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Return if the executing context performed the extract operation since
interrupts may interfere.
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Add thread parameter to _Thread_queue_Enqueue_with_handler() to avoid
access to global _Thread_Executing.
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Add Thread_Control::is_in_the_air field if configured for SMP. This
helps to simplify the extract operation and avoids superfluous
inter-processor interrupts. Move the processor allocation step into the
enqueue operation.
Add and use _Scheduler_simple_smp_Get_highest_ready(). Add and use
_Scheduler_SMP_Get_lowest_scheduled().
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Rename _Scheduler_simple_smp_Allocate_processor() to
_Scheduler_SMP_Allocate_processor().
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Rename _Scheduler_simple_smp_Start_idle() to
_Scheduler_SMP_Start_idle().
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Replace Scheduler_simple_smp_Control with Scheduler_SMP_Control. Rename
_Scheduler_simple_smp_Instance() to _Scheduler_SMP_Instance().
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Delete _Priority_bit_map_Handler_initialization() and rely on BSS
initialization. Move definition of _Priority_Major_bit_map and
_Priority_Bit_map to separate file. Move definition of __log2table also
to this file.
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Move workspace allocation to _Scheduler_priority_Initialize().
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Remove superfluous check since a ready thread must exist.
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Add and use _Scheduler_priority_Get_ready_queues()
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Add and use _Scheduler_priority_Get_scheduler_info().
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Add call to _Scheduler_Schedule() in missing path after
_Thread_Set_transient() in _Thread_Change_priority(). See also
sptests/spintrcritical19.
Add thread parameter to _Scheduler_Schedule(). This parameter is
currently unused but may be used in future SMP schedulers.
Do heir selection in _Scheduler_Schedule(). Use
_Scheduler_Update_heir() for this in the particular scheduler
implementation.
Add and use _Scheduler_Generic_block().
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This variable must be available for each processor in the system.
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Move the _CPU_Context_switch(), _CPU_Context_restore() and
_CPU_Context_switch_to_first_task_smp() code since the method to obtain
the processor index is BSP specific.
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Interrupt support for per-CPU thread dispatch disable level.
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Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
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Add and use _Per_CPU_Release_all().
The context switch user extensions are invoked in _Thread_Dispatch().
This change is necessary to avoid the giant lock in _Thread_Dispatch().
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