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* cpukit/score/cpu/sh/context.c: Correct name of _CPU_Context_switchJoel Sherrill2015-03-091-1/+1
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* or1k: Correct _CPU_Thread_Idle_body prototypeJoel Sherrill2015-03-092-2/+2
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* score: Fix for GCC version 5 and laterSebastian Huber2015-03-091-1/+2
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* score: TypoSebastian Huber2015-03-091-1/+1
| | | | Close #2286.
* Fix even more Doxygen issuesJoel Sherrill2015-03-069-9/+40
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* coremuteximpl.h: Reorder macro names to match body and fix Doxygen warningsJoel Sherrill2015-03-061-7/+13
| | | | closes 2285.
* Fix more Doxygen typosJoel Sherrill2015-03-063-5/+5
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* Fix a number of minor Doxygen formatting issuesJoel Sherrill2015-03-062-4/+4
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* score: Allow NULL for SMP lock nameSebastian Huber2015-03-061-1/+1
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* score: Fix SMP lock implementationSebastian Huber2015-03-063-1/+9
| | | | | | | | See also: https://nahratzah.wordpress.com/2012/10/12/a-trivial-fair-spinlock/ http://concurrencyfreaks.blogspot.de/2014/05/relaxed-atomics-optimizations-for.html
* score: Add compiler memory barrier to atomic opsSebastian Huber2015-03-051-0/+6
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* score: Add thread wait flagsSebastian Huber2015-03-053-0/+193
| | | | Update #2273.
* score: Add thread acquireSebastian Huber2015-03-052-24/+79
| | | | Update #2273.
* score: Add ISR lock to Objects_ControlSebastian Huber2015-03-055-0/+166
| | | | | | | | | This enables per-object SMP locks on SMP configurations and is the first step to support fine-grained locking. On uni-processor configuration there will be no overhead. The _Objects_Acquire() is intended to replace _Objects_Get_isr_disable(). Update #2273.
* score: Thread dispatch dis/enable without GiantSebastian Huber2015-03-051-22/+82
| | | | Update #2273.
* score: Add and use _Thread_Do_dispatch()Sebastian Huber2015-03-053-85/+120
| | | | | | | | | | | | The _Thread_Dispatch() function is quite complex and the time to set up and tear down the stack frame is significant. Split this function into two parts. The complex part is now in _Thread_Do_dispatch(). Call _Thread_Do_dispatch() in _Thread_Enable_dispatch() only if necessary. This increases the average case performance. Simplify _Thread_Handler() for SMP configurations. Update #2273.
* score: Simplify and fix signal deliverySebastian Huber2015-03-052-43/+12
| | | | | | | Deliver the POSIX signals after the thread state was updated to avoid race-conditions on SMP configurations. Update #2273.
* score: Update _Thread_Heir only if necessarySebastian Huber2015-03-0510-40/+34
| | | | | | | | | | | | | | | | | | | | Previously, the _Thread_Heir was updated unconditionally in case a new heir was determined. The _Thread_Dispatch_necessary was only updated in case the executing thread was preemptible or an internal thread was unblocked. Change this to update the _Thread_Heir and _Thread_Dispatch_necessary only in case the currently selected heir thread is preemptible or a dispatch is forced. Move the schedule decision into the change priority operation and use the schedule operation only in rtems_task_mode() in case preemption is enabled or an ASR dispatch is necessary. This is a behaviour change. Previously, the RTEMS_NO_PREEMPT also prevented signal delivery in certain cases (not always). Now, signal delivery is no longer influenced by RTEMS_NO_PREEMPT. Since the currently selected heir thread is used to determine if a new heir is chosen, non-preemptible heir threads currently not executing now prevent a new heir. This may have an application impact, see change test tm04. Document this change in sp04. Update #2273.
* score: Add and use PRIORITY_PSEUDO_ISRSebastian Huber2015-03-052-1/+8
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* score: C/C++ compatibility macros for ISR locksSebastian Huber2015-03-051-4/+51
| | | | Update #2273.
* score: DocumentationAlexander Krutwig2015-03-051-0/+13
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-0519-333/+0
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* score/cpu/or1k: Add cpuatomic.h to fix broken build.Hesham ALMatary2015-03-043-2/+19
| | | | | 4e3d9a4d6c76fba8e31138d503f736405dafc213 broke or1k, cpuatomic.h has to be added to all architectures.
* score: ISR lock C/C++ compatiblity issueSebastian Huber2015-03-041-65/+63
| | | | | | | | | | Empty structures are implementation-defined in C. GCC gives them a size of zero. In C++ empty structures have a non-zero size. Add ISR_LOCK_DEFINE() to define ISR locks for structures used by C and C++. Update #2273.
* score: Add and use _Thread_Enable_dispatch_body()Sebastian Huber2015-03-042-5/+8
| | | | Update #2273.
* score: Inline _Thread_Disable_dispatch() for SMPSebastian Huber2015-03-041-2/+1
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* score: Add parameter to Giant acquire/releaseSebastian Huber2015-03-043-10/+18
| | | | Update #2273.
* or1k/or1k-exception-default.c: Eliminate dependency on BSP provided .h fileHesham ALMatary2015-03-031-1/+0
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* score: Enable SMP barriers for all configurationsSebastian Huber2015-03-022-6/+1
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* ARM: Fix _ARMV4_Exception_fiq_defaultMartin Galvan2015-02-271-0/+8
| | | | | | | | In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137.
* sparc64: fix copyright notices.Gedare Bloom2015-02-231-12/+1
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bfin: do not reset dispatch neededGedare Bloom2015-02-191-2/+0
| | | | | | | | Closes #2148 Fix suggested in above ticket. On examination, the assembly appears to be clearing the DISPATCH_NEEDED flag before jumping to _Thread_Dispatch.
* score: Make <rtems/score/atomic.h> availableSebastian Huber2015-02-194-206/+588
| | | | | | | | Make <rtems/score/atomic.h> available for all RTEMS configurations. Use inline functions instead of macros. Use ISR disable/enable on uni-processor configurations to ensure atomicity. Update #2273.
* score: Fix _Thread_Start_multitasking() on SMPSebastian Huber2015-02-171-11/+13
| | | | Close #2268.
* score: Fix FP context restore via _Thread_HandlerSebastian Huber2015-02-174-68/+44
| | | | | | | | | | After a context switch we end up in the second part of _Thread_Dispatch() or in _Thread_Handler() in case of new threads. Use the same function _Thread_Restore_fp() to restore the floating-point context. It makes no sense to do this in _Thread_Start_multitasking(). This fixes also a race condition in SMP configurations. Update #2268.
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-176-6/+22
| | | | Update #2268.
* score: Mention ticket in commentSebastian Huber2015-02-131-1/+1
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* or1k/cpu.c: Eliminate dependency on BSP provided headerHesham ALMatary2015-02-101-2/+7
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* score: Delete superfluous Heap_Statistics::instanceSebastian Huber2015-01-222-8/+0
| | | | | This value depends on the _Heap_Initialize() call sequence and carries no useful information.
* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-203-10/+13
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-135-8/+700
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* nios2: Disable assembler warningSebastian Huber2015-01-131-2/+3
| | | | Close #2232.
* arm: Fix compile error for ARMv6-M multilibSebastian Huber2015-01-092-2/+5
| | | | | | | ARMv6-M is not supported since we cannot directly use the ARMv7-M code due to some inline assembler statements. Close #2231.
* powerpc: Add AltiVec register ASM definesSebastian Huber2015-01-091-0/+32
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* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-0/+2
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Add PPC_STACK_ALIGN_POWERSebastian Huber2015-01-091-16/+6
| | | | Simplify PPC_STACK_ALIGNMENT definition.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-092-6/+12
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-092-3/+4
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* powerpc: Delete _CPU_IRQ_infoSebastian Huber2015-01-091-16/+0
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* powerpc: Use alternate time base for CPU counterSebastian Huber2015-01-091-3/+3
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