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* score: Fix SMP priority affinity scheduler yieldSebastian Huber2022-05-131-0/+1
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* score: Add SMP priority affinity scheduler yieldTian Ye2022-05-121-0/+18
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* score/src: Add file headers and licensesRyan Long2022-05-043-0/+81
| | | | | These files had no header, copyright, or license. Based on git history, added appropriate copyright and license.
* sparc64-syscall.h: Add file headers and licensesRyan Long2022-05-041-0/+15
| | | | | This file had no header, copyright, or license. Based on git history, added appropriate copyright and license.
* cpukit/microblaze: Add file headers and licensesRyan Long2022-05-042-0/+70
| | | | | These files had no file header, copyright, or license. Based on git history, added appropriate copyright and license.
* heap: Fix heap statistics with protection enabledSebastian Huber2022-04-281-0/+9
| | | | Close #4644.
* Remove duplicate SPDX lines accidentally addedJoel Sherrill2022-04-084-8/+0
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* x86_64/elf_machdep.h: Replace stub with NetBSD versionRyan Long2022-04-081-4/+76
| | | | | | | The other ports included that architecture's version of this file from NetBSD. This patch follows that pattern. closes #4641
* cpukit/score/cpu/moxie: Change license to BSD-2Joel Sherrill2022-04-018-24/+176
| | | | | | Permission received from Anthony Green. Updates #3053.
* cpukit/: Update Eric Norum contact info and normalize file headersJoel Sherrill2022-03-241-21/+25
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* smp: Add fatal errorSebastian Huber2022-03-241-0/+5
| | | | | | | Add SMP-specifc SMP_FATAL_MULTITASKING_START_ON_NOT_ONLINE_PROCESSOR fatal error. This fatal error helps to diagnose a broken SMP startup sequence. Without this error a context switch using the NULL pointer for the thread control block happens which may be difficult to debug.
* score: Add _IO_Relax()Sebastian Huber2022-03-241-0/+53
| | | | | | | This function may be used to burn a couple of processor cycles with minimum impact on the system bus. It may be used in busy wait loops. Since it is a global function, it is possible to wrap it in device driver test code.
* cpukit/aarch64: Add Per_CPU_Control accessorKinsey Moore2022-03-121-0/+23
| | | | | | Add an architecture-specific implementation for _CPU_Get_current_per_CPU_control() to reduce overhead for getting the current CPU's Per_CPU_Control structure.
* arm: Fix PMSA section to region mappingSebastian Huber2022-03-111-22/+33
| | | | | Fix move of regions. Allow sections to be contained in a region (may happen due to region alignment).
* arm: Add _AArch32_PMSA_Map_sections_to_regions()Sebastian Huber2022-03-112-20/+90
| | | | This simplifies unit testing.
* cpukit/: Scripted embedded brains header file clean upJoel Sherrill2022-03-10102-612/+1
| | | | Updates #4625.
* SMP: Fix start multitasking for some targetsSebastian Huber2022-03-097-0/+59
| | | | | | | | | | | | | The previous SMP multitasking start assumed that the initial heir thread of a processor starts execution in _Thread_Handler(). The _Thread_Handler() sets the interrupt state explicitly by _ISR_Set_level() before it calls the thread entry. Under certain timing conditions, processors may perform an initial context switch to a thread which already executes its thread body (see smptests/smpstart01). In this case, interrupts are disabled after the context switch on targets which do not save/restore the interrupt state during a context switch (aarch64, arm, and riscv). Close #4627.
* score: Disable thread dispatching earlierSebastian Huber2022-03-082-6/+6
| | | | | | | Disable thread dispatching earlier on secondary processors. This ensures that fatal error and per-CPU job handlers are called with thread dispatching disabled. On the boot processor, the thread dispatching is already disabled by _Thread_Dispatch_initialization().
* mpci: Fix RTEMS_DEBUG supportSebastian Huber2022-03-081-1/+1
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* score/cpu/v850: Change license to BSD-2Joel Sherrill2022-02-288-24/+176
| | | | Updates #3053.
* score/cpu/sparc64: Change license to BSD-2Joel Sherrill2022-02-289-27/+198
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* score/cpu/sparc: Change license to BSD-2Joel Sherrill2022-02-2816-48/+352
| | | | Updates #3053.
* score/cpu/powerpc: Change license to BSD-2Joel Sherrill2022-02-2810-34/+219
| | | | Updates #3053.
* score/cpu/or1k: Change license to BSD-2Joel Sherrill2022-02-2814-42/+308
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* score/cpu/no_cpu: Change license to BSD-2Joel Sherrill2022-02-289-27/+198
| | | | Updates #3053.
* score/cpu/nios2: Change license to BSD-2Joel Sherrill2022-02-2827-81/+594
| | | | Updates #3053.
* score/cpu/mips: Change license to BSD-2Joel Sherrill2022-02-286-18/+132
| | | | Updates #3053.
* score/cpu/m68k: Change license to BSD-2Joel Sherrill2022-02-288-24/+176
| | | | Updates #3053.
* score/cpu/i386: Change license to BSD-2Joel Sherrill2022-02-2810-30/+218
| | | | | | sse_test.c was deliberarely NOT changed. Updates #3053.
* score/cpu/arm: Change license to BSD-2Joel Sherrill2022-02-2838-115/+836
| | | | Updates #3053.
* score/src/[t-z]*.c: Change license to BSD-2Joel Sherrill2022-02-2853-159/+1166
| | | | Updates #3053.
* score/src/[n-s]*.c: Change license to BSD-2Joel Sherrill2022-02-2896-288/+2120
| | | | Updates #3053.
* score/src/[a-m]*.c: Change license to BSD-2Joel Sherrill2022-02-2851-153/+1122
| | | | Updates #3053.
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-255-11/+46
| | | | | | | | | | This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
* score/cpu/i386: Clean up file headers in prep for license change.Joel Sherrill2022-02-233-6/+9
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* score/src/schedulersimple*.c: Replace found in found in with found inJoel Sherrill2022-02-234-4/+4
| | | | Updates #3053.
* cpukit/libdebugger: Add MicroBlaze supportKinsey Moore2022-02-231-0/+24
| | | | | | | | | | | | Add MicroBlaze support for libdebugger. This uses only software break type instructions to provide self-hosted GDB debugging support for applications since internal control of debug hardware is not possible. Also of note, this implementation for MicroBlaze would typically use the brki instruction for software break, but instead uses an illegal opcode to manage software breaks as exceptions. This is due to poor interaction with the debug hardware where the debug hardware will intercept software breaks instead of allowing the software break vector to execute.
* microblaze: Decouple exceptions from interruptsKinsey Moore2022-02-232-8/+8
| | | | | | | | Exception handling should be enabled at all times during execution to ensure that exceptions are not ignored which would cause further problems. This separates use of the exception enable bit from use of the interrupt enable bit in the machine status register so that they can be manipulated independently.
* kern_ntptime.c: Port to RTEMSSebastian Huber2022-02-212-3/+141
| | | | | | Remove previous adjtime() implementation. Update #2348.
* kern_ntptime.c: Import from FreeBSDSebastian Huber2022-02-211-0/+1053
| | | | | | | | | | | | | | | | | | | | The file was imported from this repository: https://github.com/freebsd/freebsd.git This commit was used: commit 3ec0dc367bff27c345ad83240625b2057af391b9 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Mon Feb 7 14:16:16 2022 -0700 kern_ntptime.c: Remove ntp_init() The ntp_init() function did set a couple of global objects to zero. These objects are in the .bss section and already initialized to zero during kernel or module loading. Update #2348.
* kern_tc: unify timecounter to bintime delta conversionAndriy Gapon2022-02-211-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two places where we convert from a timecounter delta to a bintime delta: tc_windup and bintime_off. Both functions use the same calculations when the timecounter delta is small. But for a large delta (greater than approximately an equivalent of 1 second) the calculations were different. Both functions use approximate calculations based on th_scale that avoid division. Both produce values slightly greater than a true value, calculated with division by tc_frequency, would be. tc_windup is slightly more accurate, so its result is closer to the true value and, thus, smaller than bintime_off result. As a consequence there can be a jump back in time when time hands are switched after a long period of time (a large delta). Just before the switch the time would be calculated with a large delta from th_offset_count in bintime_off. tc_windup does the switch using its own calculations of a new th_offset using the large delta. As explained earlier, the new th_offset may end up being less than the previously produced binuptime. So, for a period of time new binuptime values may be "back in time" comparing to values just before the switch. Such a jump must never happen. All the code assumes that the uptime is monotonically nondecreasing and some code works incorrectly when that assumption is broken. For example, we have observed sleepq_timeout() ignoring a timeout when the sbinuptime value obtained by the callout code was greater than the expiration value, but the sbinuptime obtained in sleepq_timeout() was less than it. In that case the target thread would never get woken up. The unified calculations should ensure the monotonic property of the uptime. The problem is quite rare as normally tc_windup should be called HZ times per second (typically 1000 or 100). But it may happen in VMs on very busy hypervisors where a VM's virtual CPU may not get an execution time slot for a second or more. Reviewed by: kib MFC after: 2 weeks Sponsored by: Panzura LLC
* timecounter: Initialize tc_lock earlierMark Johnston2022-02-211-1/+2
| | | | | | | | | | | | | Hyper-V wants to register its MSR-based timecounter during SI_SUB_HYPERVISOR, before SI_SUB_LOCK, since an emulated 8254 may not be available for DELAY(). So we cannot use MTX_SYSINIT to initialize the timecounter lock. PR: 259878 Reviewed by: kib MFC after: 3 days Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D33014
* cpukit/microblaze: Simplify dispatch assemblyKinsey Moore2022-02-041-45/+3
| | | | | | The dispatch code was unnecessarily saving and restoring an extra interrupt frame. This avoids the extra frame and folds the dispatch call into a fallthrough to the interrupt frame restoration code.
* cpukit/microblaze: Clarify interrupt frame usageKinsey Moore2022-02-042-5/+14
| | | | | | Avoid use of magic numbers in favor of named constants and add MSR to the interrupt frame so that thread dispatch can occur on exceptions as well.
* cpukit/microblaze: Add exception extensionsKinsey Moore2022-02-043-0/+388
| | | | | Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and mark this functionality as available on MicroBlaze.
* cpukit/microblaze: Add debug vector and handlerKinsey Moore2022-02-042-0/+35
| | | | | | This patch adds a vector for debug events along with a hook similar to the exception framework. The debug vector generates an exception frame for use by libdebugger.
* cpukit/microblaze: Add exception frameworkKinsey Moore2022-02-043-17/+187
| | | | | | | | | | | This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
* microblaze: Add support for libbsd networkingAlex White2022-02-012-4/+1
| | | | | This includes fixes and improvements necessary to get libbsd networking running.
* arm: Optimize interrupt handlingSebastian Huber2022-01-173-0/+53
| | | | | Use the SRS (Store Return State) instruction if available. This considerably simplifies the context save and restore.
* arm: Fix stack alignment during interrupt handlingSebastian Huber2022-01-171-10/+23
| | | | | | | | | | | On a public interface, the stack pointer must be aligned on an 8-byte boundary. However, it may temporarily be only aligned on a 4-byte boundary. The interrupt handling code must ensure that the stack pointer is properly aligned before it calls a function. See also: https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling Update #4579.
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