summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu (follow)
Commit message (Collapse)AuthorAgeFilesLines
...
* nios2: Allow ISR nesting in dispatch variantSebastian Huber2021-02-012-173/+16
| | | | | | Rename _Nios2_ISR_Dispatch_with_shadow_non_preemptive() in _Nios2_ISR_Dispatch_with_shadow_register_set(). Remove _Nios2_ISR_Dispatch_with_shadow_preemptive().
* nios2: Optimize ISR dispatch variantSebastian Huber2021-02-011-42/+60
| | | | | Use _Thread_Do_dispatch() in _Nios2_ISR_Dispatch_with_shadow_non_preemptive().
* nios2: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2021-02-015-35/+23
|
* nios2: Add TLS supportSebastian Huber2021-02-011-4/+15
| | | | Update #4214.
* nios2: Make _ISR_Is_in_progress() weakSebastian Huber2021-02-011-1/+1
| | | | This allows the BSP to override this function.
* nios2: Fix ISR dispatch variantsSebastian Huber2021-02-012-9/+7
| | | | | The thread dispatch disabled level moved to _Per_CPU_Information some time ago.
* Update header.amSebastian Huber2020-12-231-0/+2
|
* arm: Add support for Arm PMSAv8-32Sebastian Huber2020-12-223-0/+568
| | | | Update #4202.
* arm: Add header file for AArch32 System RegistersSebastian Huber2020-12-221-0/+14657
| | | | Update #4202.
* arm: Optimize arm_interrupt_disable()Sebastian Huber2020-12-161-2/+11
| | | | Update #4202.
* cpu/armv7m: Fix table based init for ARMV7M_MPUChristian Mauderer2020-12-141-1/+7
| | | | | | | | Somehow the table index has been missing in the latest patch version. With that, the configuration for the first region has been applied multiple times. Update #4180
* cpukit/aarch64: Add explanation of exception flowKinsey Moore2020-12-102-3/+18
|
* cpukit/aarch64: Use hex consistently for offsetsKinsey Moore2020-12-105-116/+116
|
* arm: Support Armv8 in <rtems/score/arm.h>Sebastian Huber2020-12-101-11/+10
| | | | Update #4202.
* score/aarch64: Resolve warning in exception dumpKinsey Moore2020-11-241-2/+2
| | | | | This resolves a warning in the exception frame dump for AArch64 relating to a missized printf format specifier.
* cpu/armv7m: Add table based init for ARMV7M_MPUChristian Mauderer2020-11-201-0/+103
| | | | | | | Modify the MPU functions of the stm32h7 BSP to be table based and available for all ARMV7M BSPs. Update #4180
* score/aarch64: Size saved SP register for ABIKinsey Moore2020-11-131-1/+4
| | | | | This ensures that the saved SP register is sized appropriately depending on the chosen ABI and prevents a warning in the libmisc stack checker.
* sparc: Add SPARC_INTERRUPT_SOURCE_TO_TRAP()Sebastian Huber2020-11-061-0/+12
| | | | Update #4171.
* sparc: Add SPARC_INTERRUPT_TRAP_TO_SOURCE()Sebastian Huber2020-11-061-0/+17
| | | | Update #4171.
* sparc: Add SPARC_IS_INTERRUPT_TRAP()Sebastian Huber2020-11-061-0/+17
| | | | Update #4171.
* sparc: Move SPARC-specific macros to sparc.hSebastian Huber2020-11-062-22/+40
| | | | | | Clarify Doxygen comments. Fix formatting. Update #4171.
* bsps/arm: Workaround for Errata 845369Sebastian Huber2020-10-161-0/+32
| | | | | | | Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption. Update #4115.
* rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber2020-10-1019-62/+28
| | | | | | | | | | | Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors like this: error: no return statement in function returning non-void [-Werror=return-type] Use C11 and C++11 standard means to declare a no-return function. Close #4122.
* score: Add AArch64 portKinsey Moore2020-10-0516-0/+2751
| | | | | This adds a CPU port for AArch64(ARMv8) with support for exceptions and interrupts.
* or1k: Do not use printk() for _CPU_Fatal_halt()Sebastian Huber2020-09-231-4/+0
| | | | Debug output can be added to user-defined fatal error handlers.
* or1k: Remove superfluous includesSebastian Huber2020-09-231-2/+0
| | | | Including <stdio.h> in <rtems/score/cpu.h> breaks libbsd.
* arm: Fix arm_cp15_set_translation_table_entries()Sebastian Huber2020-09-171-0/+16
| | | | | | | | In a multi-processor system we must broadcast the TLB maintenance operation to the Inner Shareable domain to ensure that the other processors update their TLB caches accordingly. Close #4068.
* i386/score: fix assembly mnemonicGedare Bloom2020-09-121-1/+1
| | | | Closes #4076.
* sparc: Use RTEMS_XCONCAT()Sebastian Huber2020-08-201-4/+2
| | | | Prefer macros with a proper namespace.
* i386: Fix possible race condition on first context restoreJan Sommer2020-07-291-1/+1
| | | | | | | | | | | | Make sure that the esp is restored before the eflags register. When the init task is initially restored, system interrupts are activated when the eflags register is loaded. If the esp register still points to an address in the interrupt stack area (from early system initlization) the ISR might overwrite its own stack. Closes #4031
* epiphany: Remove support for this targetSebastian Huber2020-07-0513-1882/+0
| | | | | | | Due to an unmaintained toolchain (internal errors in GCC, no FSF GDB integration) the Epiphany architecture was obsoleted in RTEMS 5.1. Update #3941.
* i386: Replace fpcr clobber with memory clobberSebastian Huber2020-07-052-3/+3
| | | | Update #3943.
* score: Clarify CPU_USE_LIBC_INIT_FINI_ARRAY optionSebastian Huber2020-06-301-3/+4
| | | | Update #4018.
* score: Add CPU_USE_LIBC_INIT_FINI_ARRAYKinsey Moore2020-06-3018-0/+42
| | | | | | | | This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU ports to determine which global constructor and destructor methods are used instead of placing architecture defines where they shouldn't be. Close #4018
* bsp/pc386: Define interrupt stack frame for smpJan Sommer2020-06-112-13/+17
| | | | | | - Defines CPU_Interrupt_frame in cpu_impl.h - Updates isq_asm.S to save/restore registers in matching order to interrupt frame
* bsp/pc386: Update context switch and restoreJan Sommer2020-06-112-16/+51
| | | | Uses similar flow in cpu_asm.S for i386 as for arm.
* bsp/pc386: Update GDT to work for SMPJan Sommer2020-06-112-5/+32
| | | | | | | | | | Create a GS segment in the GDT for each processor for storing TLS. This makes the GDT in startAP.S obsolete as all processors now share the same GDT, which is passed to each AP at startup. The correct segment for each processor is calculated in cpu_asm.S. Update #3335
* arm: Fix ARMv7-M exception handlerSebastian Huber2020-05-271-8/+15
| | | | | | Store the stack pointer of the exception context to the exception frame. Close #3987.
* Canonicalize config.h includeSebastian Huber2020-04-1662-62/+62
| | | | | | | | Use the following variant which was already used by most source files: #ifdef HAVE_CONFIG_H #include "config.h" #endif
* arm: ARMv7-M statically initialized vector tableSebastian Huber2020-04-032-16/+30
| | | | | | | Statically initialize the ARMv7-M vector table to allow a placement in ROM with read-only MPU settings. Change licence to BSD-2-Clause in some files.
* score: Remove superfluous FP types/definesSebastian Huber2020-02-1210-795/+33
| | | | Update #3835.
* Regenerate headers.amSebastian Huber2019-11-291-0/+1
|
* riscv: preliminarily support for libdlHesham Almatary2019-11-121-0/+144
| | | | Support for targets compiled with -fno-pic and -mno-relax
* arm: Add defines for small pages MMUSebastian Huber2019-10-311-0/+57
|
* arm: Fix default exception handlerSebastian Huber2019-09-031-2/+2
| | | | Keep the stack pointer properly 8-byte aligned.
* arm: Return the current handler from arm_cp15_set_exception_handlerChris Johns2019-06-281-1/+6
| | | | Closes #3762
* sparc: Fix mistakenly cleared PSR[EF] bit.Maksim E. Kozlov2019-06-071-1/+1
| | | | | The superfluously modified %l0 had no effect if the branch is not taken. This change clarifies the code.
* sparc: Fix missed restoring of PSR in syscall_lazy_fp_switchMaksim E. Kozlov2019-06-061-0/+11
| | | | | | | | | It is needed to restore PSR just before return because condition codes are dirty after the CMP instructions and this may cause undefined program behavior after returning from the switching procedure (on following branch instruction, for example). Close #3756.
* sparc: Improve _CPU_Context_validate()Sebastian Huber2019-06-061-8/+20
| | | | | | Use the FPU and check that the condition codes in the PSR are preserved. Update #3756.
* doxygen: Rename Score* groups in RTEMSScore*Sebastian Huber2019-04-041-1/+1
| | | | Update #3706
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 22:17:14 +0000