| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
| |
* rtems/score/cpu.h: Define _CPU_Interrupt_stack_setup() macro
which reserves space for the 'vector' arg to _C_dispatch_isr()
routine and aligns the irq stack to CPU_STACK_ALIGNMENT.
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Replaced misleading typedef of
CPU_Interrupt_frame by 'void'. The i386 port does not
pass any frame info to the interrupt handlers.
|
|
|
|
|
|
| |
* ChangeLog, score/cpu/i386/ChangeLog: moved log messages
I had erroneously written to cpukit/Changelog to
cpukit/score/cpu/i386/ChangeLog.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* score/cpu/i386/rtems/score/cpu.h:
Added #ifdef ASM constructs so that this header can be
included from assembly code.
Increased CPU_STACK_ALIGNMENT to 16 bytes. Gcc maintains
16-byte alignment and it may be a advantageous to provide
initial 16-byte alignment. When using SSE some gcc versions
may produce code that crashes if the stack is not 16-byte aligned.
Make sure _CPU_Context_Initialize() sets the thread stack
up so that it is aligned to CPU_CACHE_ALIGNMENT.
* score/cpu/i386/cpu_asm.S:
Align stack to CPU_CACHE_ALIGNMENT before calling C-code.
|
|
|
|
| |
* score/cpu/i386/rtems/asm.h: Added definition for cr4 register.
|
|
|
|
| |
* score/cpu/Makefile.am: Update DIST_SUBDIRS.
|
|
|
|
|
|
|
|
| |
* rtems/score/cpu.h: Changed fpscr field to an integer type in
Context_Control_fp. Fixed warnings in PPC_Set_timebase_register().
Changed _CPU_Context_Initialize_fp() to initialize all fields and
avoid floating-point instructions.
* rtems/score/powerpc.h: Removed PPC_INIT_FPSCR define.
|
|
|
|
|
| |
* score/cpu/i386/cpu.c, score/cpu/i386/cpu.h: let the default
exception handler print a stack trace.
|
| |
|
| |
|
|
|
|
| |
* rtems/score/arm.h: Recognize ARMv7A.
|
|
|
|
| |
* rtems/score/arm.h: Recognize ARMv6J as needed by arm1136 variants.
|
|
|
|
|
| |
* rtems/score/cpu.h: Define CPU_STRUCTURE_ALIGNMENT to be on a 4 byte
boundary.
|
|
|
|
|
| |
* rtems/score/cpu.h: Add no return atrribute to _CPU_Context_restore()
since it is used for restarting self.
|
|
|
|
|
| |
* rtems/asm.h: Added macro to define ARM functions.
* cpu_asm.S, arm_exc_handler_low.S: Use macro from above.
|
|
|
|
|
| |
* rtems/score/cpu.h: Make heap alignment 4 which is greater than
CPU_ALIGNMENT but minimum for heap.
|
| |
|
|
|
|
|
| |
* rtems/score/cpu.h: Mark _CPU_Context_restore() as noreturn so the
compiler will not generate code thinking it returns.
|
|
|
|
|
| |
* cpu.c, cpu_asm.S, rtems/score/cpu.h: Fix bug in
_CPU_Context_Initialize.
|
|
|
|
|
|
| |
* Makefile.am: added AVR specific Header files to score/cpu/avr/avr.
These are from avr-libc 1.6 and assumed to exist by AVR applications.
* preinstall.am: Regenerated.
|
|
|
|
| |
* score/cpu/Makefile.am: nios2 was not in the list.
|
|
|
|
|
|
|
| |
* cpu.c, cpu_asm.S, rtems/score/cpu.h: Context switch now works well
enough to run ticker to completion with the simulator clock idle
task. But if you comment out the printk's in _CPU_Context_Initialize,
it hangs. This remains to be investigated.
|
|
|
|
| |
* cpu.c, cpu_asm.S: Unsuccessful attempt to fix.
|
|
|
|
|
|
|
| |
*cpu_asm.S: implemented _CPU_Context_Restore by adding tags to
restore section of context switch.
Fixed bug in _CPU_Context_Switch. The wrong registers were being
used for pointer to running task Context_Control struct.
|
| |
|
| |
|
| |
|
|
|
|
|
|
| |
* cpu_asm.S: Fixed bug in _CPU_Context_Switch. The wrong registers
were being used for pointer to running task Context_Control
struct.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cpu.c: Implemented _CPU_Context_Initialize as a C function instead
of a macro. It works with limited functionality. Implemented
_CPU_Thread_Idle_body to use sleep instruction.
* Makefile.am: Changed cpu_asm.c -> cpu_asm.S
* cpu_asm.S: renamed from cpu_asm.c and implemented functions is asm
* rtems/asm.h: Appended "macros.inc" to the end of "asm.h"
* rtems/score/cpu.h:
+ Included "avr/io.h".
+ Added use 16 bit object definition.
+ Modified Context_Control struct to relect the registers
that need to be saved.
+ Implemented _CPU_ISR_Disable, _CPU_ISR_Enable, and _CPU_ISR_Flash.
Added function definitions for _CPU_Context_Initialize and
_CPU_Push.
|
|
|
|
|
| |
* score/cpu/mips/rtems/mips/idtcpu.h: Missed another WAIT
define. Removed.
|
| |
|
|
|
|
|
| |
* score/cpu/mips/rtems/mips/idtcpu.h: Remote WAIT define. Horrible
overload.
|
| |
|
|
|
|
|
|
| |
PR 1418/cpukit
* rtems/score/cpu.h: corrected _CPU_ISR_Flash implementation, added
core synchronization after all cli/sti.
|
|
|
|
| |
initialization, save and restore code.
|
|
|
|
|
| |
* rtems/score/cpu.h: Lower number of priorities and do not inline as
much.
|
|
|
|
| |
* rtems/score/cpu.h: Remove warnings.
|
|
|
|
| |
* cpu_asm.S, irq.c, rtems/score/cpu.h: Add lm32 gdb stub support.
|
|
|
|
|
| |
* rtems/score/cpu.h: Lower minimum stack size to 512 and CPU alignment
to 4.
|
|
|
|
| |
* cpu_asm.c: Add stub for setjmp/longjmp. Remove when in newlib.
|
|
|
|
|
|
|
|
|
|
|
|
| |
* cpu.h: corrected the registers in Context_Control and
in CPU_Interrupt_frame to correspond to the saved frame in cpu_asm.S
Also switched on CPU_ISR_PASSES_FRAME_POINTER.
* cpu_asm.S: Moved the restore part of _CPU_Context_switch for
easier reading. Fixed _CPU_Context_restore, it now moves the
argument and branches to a label in _CPU_Context_switch. Removed
unnecessary saves of registers in context switch and irq handling.
Rewrote irq code to call the C helper. Added some documentation
* irq.c: New file derived from c4x and nios2.
|
|
|
|
|
| |
* cpu_asm.S: We cannot use any other register than r0 without saving
them to the stack. (_ISR_Handler clears r0 right at the beginning)
|
|
|
|
|
|
|
|
| |
PR 1385/cpukit
* cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
the size changed from 4 bytes to 1 byte. The interrupt dispatching
code accesses two boolean variables for scheduling purposes and the
assembly implementations of this code did not get updated.
|
|
|
|
| |
* cpu_asm.S: Eliminate extern of unused variables.
|
|
|
|
| |
* cpu.c: Remove stray semi-colon.
|
|
|
|
| |
* rtems/score/cpu.h: AVR stack grows down.
|
|
|
|
|
| |
Standards (EIS) special purpose register definitions for MMU and L1
cache.
|
|
|
|
|
|
| |
* rtems/score/sh.h: SH2E and SH3E have a DSP rather than an FPU. They
are not compatible. We currently only support the FPU found on the
SH3 and SH4.
|
|
|
|
|
| |
* cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
consistently return void * and take a uintptr_t argument.
|
|
|
|
|
| |
* rtems/score/cpu.h: Change prototype of IDLE thread to consistently
return void * and take a uintptr_t argument.
|