Commit message (Collapse) | Author | Age | Files | Lines | |
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* | sparc: Disable FPU in interrupt context | Alexander Krutwig | 2015-05-30 | 2 | -1/+32 |
| | | | | Update #2270. | ||||
* | sparc: Remove superfluous FP enable | Sebastian Huber | 2015-05-30 | 2 | -22/+7 |
| | | | | | | | The FP context save/restore makes only sense in the context of FP threads. Update #2270. | ||||
* | sparc: Avoid new window for FP save/restore | Sebastian Huber | 2015-05-30 | 1 | -54/+48 |
| | | | | Update #2270. | ||||
* | sparc: Improve _CPU_Context_validate() | Alexander Krutwig | 2015-05-29 | 1 | -46/+49 |
| | | | | | | | Write the pattern only once to the entry register window and the floating point registers. Update #2270. | ||||
* | sparc: Add static assertion | Sebastian Huber | 2015-05-26 | 1 | -0/+5 |
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* | sparc: Delete unused CONTEXT_CONTROL_SIZE | Sebastian Huber | 2015-05-26 | 2 | -5/+0 |
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* | sparc: Delete unused ISF_STACK_FRAME_OFFSET | Sebastian Huber | 2015-05-26 | 2 | -3/+0 |
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* | sparc: Add static offset assertions | Sebastian Huber | 2015-05-26 | 1 | -0/+32 |
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* | cpukit: Add Epiphany architecture port v4 | Hesham ALMatary | 2015-05-21 | 14 | -0/+2490 |
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* | sparc: Add support for sptests/spcontext01 | Alexander Krutwig | 2015-05-21 | 4 | -10/+528 |
| | | | | | | Implement _CPU_Context_validate() and _CPU_Context_volatile_clobber(). Update #2270. | ||||
* | or1k-utility.h: Add missing end of C++ header pattern | Joel Sherrill | 2015-04-17 | 1 | -0/+4 |
| | | | | closes 2326. | ||||
* | arm: Align ARM exception frame to 8 bytes | Daniel Krueger | 2015-04-10 | 2 | -1/+7 |
| | | | | | | | | | | | The stack pointer must be aligned on 8 byte boundary on ARM, so the size of the exception frame must be a multiple of 8 bytes. Otherwise we might/will get an alignment fault, when executing code in the data abort handler for example. Close #2318. Signed-off-by: Daniel Krueger <daniel.krueger@systec-electronic.com> | ||||
* | or1k: Send halt signal to or1k simulators when rtems terminates | Hesham ALMatary | 2015-04-02 | 2 | -1/+11 |
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* | sparc: Ensure interrupt service after ISR enable | Sebastian Huber | 2015-03-25 | 1 | -1/+8 |
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* | Replace www.rtems.com with www.rtems.org | Sebastian Huber | 2015-03-20 | 2 | -2/+2 |
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* | cpukit: add and use CPU_Uint32ptr type | Gedare Bloom | 2015-03-16 | 19 | -0/+59 |
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* | score/or1k: Fix warnings. Add missing prototypes | Hesham ALMatary | 2015-03-13 | 1 | -0/+4 |
| | | | | Closes #2304 | ||||
* | cpukit: Remove old DESCRIPTION: in comments | Joel Sherrill | 2015-03-11 | 1 | -6/+4 |
| | | | | These were remnants of pre-Doxygen comment style. | ||||
* | or1k/rtems/score/cpu.h: Add no_return attribute to _CPU_Context_restore | Joel Sherrill | 2015-03-09 | 1 | -1/+1 |
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* | cpukit/score/cpu/sh/context.c: Correct name of _CPU_Context_switch | Joel Sherrill | 2015-03-09 | 1 | -1/+1 |
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* | or1k: Correct _CPU_Thread_Idle_body prototype | Joel Sherrill | 2015-03-09 | 2 | -2/+2 |
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* | score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITY | Sebastian Huber | 2015-03-05 | 19 | -333/+0 |
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* | score/cpu/or1k: Add cpuatomic.h to fix broken build. | Hesham ALMatary | 2015-03-04 | 3 | -2/+19 |
| | | | | | 4e3d9a4d6c76fba8e31138d503f736405dafc213 broke or1k, cpuatomic.h has to be added to all architectures. | ||||
* | or1k/or1k-exception-default.c: Eliminate dependency on BSP provided .h file | Hesham ALMatary | 2015-03-03 | 1 | -1/+0 |
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* | ARM: Fix _ARMV4_Exception_fiq_default | Martin Galvan | 2015-02-27 | 1 | -0/+8 |
| | | | | | | | | In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137. | ||||
* | sparc64: fix copyright notices. | Gedare Bloom | 2015-02-23 | 1 | -12/+1 |
| | | | | | The sparc64 port had some incorrect copyright notices affixed to source code files. | ||||
* | bfin: do not reset dispatch needed | Gedare Bloom | 2015-02-19 | 1 | -2/+0 |
| | | | | | | | | Closes #2148 Fix suggested in above ticket. On examination, the assembly appears to be clearing the DISPATCH_NEEDED flag before jumping to _Thread_Dispatch. | ||||
* | score: Add _CPU_SMP_Prepare_start_multitasking() | Sebastian Huber | 2015-02-17 | 5 | -6/+20 |
| | | | | Update #2268. | ||||
* | or1k/cpu.c: Eliminate dependency on BSP provided header | Hesham ALMatary | 2015-02-10 | 1 | -2/+7 |
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* | powerpc: Fix AltiVec VSCR save/restore | Sebastian Huber | 2015-01-20 | 3 | -10/+13 |
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* | powerpc: AltiVec and FPU context support | Sebastian Huber | 2015-01-13 | 5 | -8/+700 |
| | | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size. | ||||
* | nios2: Disable assembler warning | Sebastian Huber | 2015-01-13 | 1 | -2/+3 |
| | | | | Close #2232. | ||||
* | arm: Fix compile error for ARMv6-M multilib | Sebastian Huber | 2015-01-09 | 2 | -2/+5 |
| | | | | | | | ARMv6-M is not supported since we cannot directly use the ARMv7-M code due to some inline assembler statements. Close #2231. | ||||
* | powerpc: Add AltiVec register ASM defines | Sebastian Huber | 2015-01-09 | 1 | -0/+32 |
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* | powerpc: Use PPC_HAS_FPU | Sebastian Huber | 2015-01-09 | 1 | -0/+2 |
| | | | | Provide floating point context support only if PPC_HAS_FPU == 1. | ||||
* | powerpc: Add PPC_STACK_ALIGN_POWER | Sebastian Huber | 2015-01-09 | 1 | -16/+6 |
| | | | | Simplify PPC_STACK_ALIGNMENT definition. | ||||
* | powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500 | Sebastian Huber | 2015-01-09 | 2 | -6/+12 |
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* | powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZE | Sebastian Huber | 2015-01-09 | 2 | -3/+4 |
| | | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT. | ||||
* | powerpc: Delete _CPU_IRQ_info | Sebastian Huber | 2015-01-09 | 1 | -16/+0 |
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* | powerpc: Use alternate time base for CPU counter | Sebastian Huber | 2015-01-09 | 1 | -3/+3 |
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* | sparc64: put each copyright on one line | Gedare Bloom | 2014-12-08 | 5 | -16/+11 |
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* | i386: doxygen and comments related to VESA real mode framebuffer | Jan Dolezal | 2014-12-04 | 2 | -17/+26 |
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* | SPARC: optimize IRQ enable & disable | Daniel Hellstrom | 2014-12-04 | 1 | -2/+16 |
| | | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this. | ||||
* | arm: Use CPU_TIMESTAMP_USE_STRUCT_TIMESPEC | Sebastian Huber | 2014-11-25 | 1 | -1/+1 |
| | | | | | | | Converting 64-bit nanoseconds values into the common struct timeval or struct timespec formats requires a 64-bit division to get the seconds value. Performance analysis of high network loads revealed that this is too costly on ARM. | ||||
* | score: i386: functions converting real mode pointer to physical address and back | Jan Dolezal | 2014-11-20 | 2 | -0/+75 |
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* | cpukit/score/cpu/lm32/irq.c: Fix warning | Joel Sherrill | 2014-10-20 | 1 | -0/+6 |
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* | score/cpu/lm32/rtems/score/cpu.h: Fix set but not used warning | Joel Sherrill | 2014-10-20 | 1 | -0/+3 |
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* | score/cpu/i386/rtems/score/cpu.h: Fix set but not used warning | Joel Sherrill | 2014-10-20 | 1 | -0/+1 |
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* | bfin libcpu and libbsp: Fix warnings | Joel Sherrill | 2014-10-16 | 1 | -0/+1 |
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* | h8300/cpu_asm.S: Correct register size suffix for loading DISPATCH_NEEDED | Joel Sherrill | 2014-10-15 | 1 | -1/+1 |
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