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* score: Implement forced thread migrationSebastian Huber2014-05-0711-8/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of task migration in RTEMS has some implications with respect to the interrupt latency. It is crucial to preserve the system invariant that a task can execute on at most one processor in the system at a time. This is accomplished with a boolean indicator in the task context. The processor architecture specific low-level task context switch code will mark that a task context is no longer executing and waits that the heir context stopped execution before it restores the heir context and resumes execution of the heir task. So there is one point in time in which a processor is without a task. This is essential to avoid cyclic dependencies in case multiple tasks migrate at once. Otherwise some supervising entity is necessary to prevent life-locks. Such a global supervisor would lead to scalability problems so this approach is not used. Currently the thread dispatch is performed with interrupts disabled. So in case the heir task is currently executing on another processor then this prolongs the time of disabled interrupts since one processor has to wait for another processor to make progress. It is difficult to avoid this issue with the interrupt latency since interrupts normally store the context of the interrupted task on its stack. In case a task is marked as not executing we must not use its task stack to store such an interrupt context. We cannot use the heir stack before it stopped execution on another processor. So if we enable interrupts during this transition we have to provide an alternative task independent stack for this time frame. This issue needs further investigation.
* score: Statically initialize _ISR_Vector_tableSebastian Huber2014-04-2913-96/+17
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* sparc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-282-33/+36
| | | | | | | | | | | | | | | | Use register g6 for the per-CPU control of the current processor. The register g6 is reserved for the operating system by the SPARC ABI. On Linux register g6 is used for a similar purpose with the same method since 1996. The register g6 must be initialized during system startup and then must remain unchanged. Since the per-CPU control is used in all critical sections of the operating system, this is a performance optimization for the operating system core procedures. An additional benefit is that the low-level context switch and interrupt processing code is now identical on non-SMP and SMP configurations.
* sparc: Optimize context switchSebastian Huber2014-04-282-51/+48
| | | | | | The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well.
* score: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2014-04-281-0/+18
| | | | | | | | | Add optional method _CPU_Get_current_per_CPU_control() to obtain the per-CPU control of the current processor. This is optional. Not every CPU port needs this. It is only an optional optimization variant. In case this macro is undefined, the default implementation using the current processor index will be used.
* score: Clarify TLS supportSebastian Huber2014-04-173-3/+3
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* score: SMP initialization changesSebastian Huber2014-04-145-12/+56
| | | | | | | | | | | | | | | | | Add and use _CPU_SMP_Start_processor(). Add and use _CPU_SMP_Finalize_initialization(). This makes most _CPU_SMP_Initialize() functions a bit simpler since we can calculate the minimum value of the count of processors requested by the application configuration and the count of physically or virtually available processors in the high-level code. The CPU port has now the ability to signal a processor start failure. With the support for clustered/partitioned scheduling the presence of particular processors can be configured to be optional or mandatory. There will be a fatal error only in case mandatory processors are not present. The CPU port may use a timeout to monitor the start of a processor.
* sparc: Use __leon__ multilib defineSebastian Huber2014-04-141-1/+8
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* score: Clarify CPU port alignment requirementsSebastian Huber2014-04-071-7/+9
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* score: Rename Priority_bit_map_ControlSebastian Huber2014-04-0329-29/+29
| | | | Rename Priority_bit_map_Control in Priority_bit_map_Word.
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-21204-204/+204
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* arm: Add support for interrupt profilingSebastian Huber2014-03-141-0/+20
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* arm: Fix stack alignment in interrupt handlerSebastian Huber2014-03-101-29/+19
| | | | | | According to AAPCS, section 5.2.1.2, "Stack constraints at a public interface" the stack must be 8 byte aligned. This was not the case during interrupt processing.
* score: SMP initialization and shutdown changesSebastian Huber2014-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename _SMP_Request_other_cores_to_perform_first_context_switch() into _SMP_Request_start_multitasking() since this requests now a multitasking start on all configured and available processors. The name corresponds _Thread_Start_multitasking() and _SMP_Start_multitasking_on_secondary_processor() actions issued in response to this request. Move in source file to right place. Rename PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING into PER_CPU_STATE_READY_TO_START_MULTITASKING. Rename PER_CPU_STATE_BEGIN_MULTITASKING into PER_CPU_STATE_REQUEST_START_MULTITASKING. Rename _SMP_Request_other_cores_to_shutdown() into _SMP_Request_shutdown(). Add a per-CPU state lock to protect all changes. This was necessary to offer a controlled shutdown of the system (atomic read/writes alone are not sufficient for this kind of synchronization). Add documentation for Per_CPU_State. Delete debug output. New tests smptests/smpfatal01 and smptests/smpfatal02.
* sparc: Fix CPU counter supportSebastian Huber2014-02-243-2/+84
| | | | | | | | The SPARC processors supported by RTEMS have no built-in CPU counter support. We have to use some hardware counter module for this purpose. The BSP must provide a 32-bit register which contains the current CPU counter value and a function for the difference calculation. It can use for example the GPTIMER instance used for the clock driver.
* score: _CPU_SMP_Get_current_processor()Sebastian Huber2014-02-216-11/+8
| | | | | | | Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor() and all _CPU_SMP_Get_current_processor(). Make inline ASM statements volatile again. Test smptests/smpmigration01 showed that GCC optimizes too much otherwise.
* score: Rename _Internal_error_Occurred()Sebastian Huber2014-02-214-4/+4
| | | | Rename _Internal_error_Occurred() into _Terminate().
* score: Rename bsp_smp_initialize()Sebastian Huber2014-02-195-0/+26
| | | | | Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU port must supply this function.
* score: Delete _Thread_BSP_contextSebastian Huber2014-02-192-35/+6
| | | | | | | | | | | | Do not return to BSP context in the exit() shutdown path. This makes it possible to re-use the initialization stack. It can be used for the interrupt stack for example. On targets with a small RAM this is a considerable benefit. This change eliminates also some special cases and simplifies the code. Delete _Thread_Set_global_exit_status(), _Thread_Get_global_exit_status() and _Thread_Stop_multitasking().
* powerpc: Change interrupt disable implemetationSebastian Huber2014-02-193-19/+36
| | | | | | | | | | | | Instead of SPRG0 (= special purpose register 272) use the new global symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask. The benefit is that it is now possible to disable interrupts without further run-time initialization in boot_card(). At least on Freescale e500 cores this leads also to a faster execution since the mfmsr and mfspr instruction require four cycles to complete. The instructions to load the mask value can execute while the mfmsr is in progress.
* score: Use atomic API for SMP lockSebastian Huber2014-02-1715-544/+0
| | | | | Use a ticket lock implementation based on atomic operations. Delete CPU port specific SMP lock implementations.
* sparc: Add atomic support for SPARC V8Sebastian Huber2014-02-172-0/+203
| | | | Use SWAP instruction with one lock for the system in the SMP case.
* sparc: Add LEON3_ASR17_PROCESSOR_INDEX_SHIFTSebastian Huber2014-02-141-0/+14
| | | | Add _LEON3_Get_current_processor().
* score: Remove volatile from asm statementsSebastian Huber2014-02-142-2/+2
| | | | | The instructions to get the processor current index have no side-effects.
* score: Add CPU counter supportSebastian Huber2014-02-1434-0/+288
| | | | | | | | | Add a CPU counter interface to allow access to a free-running counter. It is useful to measure short time intervals. This can be used for example to enable profiling of critical low-level functions. Add two busy wait functions rtems_counter_delay_ticks() and rtems_counter_delay_nanoseconds() implemented via the CPU counter.
* sparc: Increase CPU_STRUCTURE_ALIGNMENT to 32Sebastian Huber2014-02-131-1/+1
| | | | Recent LEON4 systems use a cache line size of 32 bytes.
* sparc: Save/restore only non-volatile contextSebastian Huber2014-02-122-64/+74
| | | | | | | | | | The _CPU_Context_switch() is a normal function call. The following registers are volatile (the caller must assume that the register contents are destroyed by the callee) according to "SYSTEM V APPLICATION BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0, o1, o2, o3, o4, o5. Drop these registers from the context. Ensure that offset defines match the structure offsets.
* score: _CPU_Context_switch_to_first_task_smp()Sebastian Huber2014-02-054-23/+0
| | | | | Delete _CPU_Context_switch_to_first_task_smp() and use _CPU_Context_restore() instead.
* Add thread-local storage (TLS) supportSebastian Huber2014-02-0437-52/+270
| | | | | Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
* arm: Add ARMv7-M SHCSR register bitsSebastian Huber2014-01-101-0/+6
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* arm: Fix set by but not used warningSebastian Huber2013-12-161-1/+2
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* no_cpu/cpusmplock.h: Clean up to be compilableJoel Sherrill2013-12-141-0/+4
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* arm: Clear reservationsSebastian Huber2013-12-032-1/+2
| | | | | Recent GCC versions use atomic operations based on load/store exclusive in the C++ library.
* nios2: TyposSebastian Huber2013-11-261-2/+2
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* powerpc: Add r2 to CPU contextSebastian Huber2013-11-183-11/+13
| | | | The r2 may be used for thread-local storage.
* powerpc: Do not validate reserved XER bitsSebastian Huber2013-11-181-2/+2
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* no_cpu/.../cpu.h: Comment improvementJoel Sherrill2013-11-141-0/+5
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* mips/.../cpu.h: Comment improvementJoel Sherrill2013-11-141-1/+3
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* arm: Fix inconsistent define usageSebastian Huber2013-09-061-2/+3
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* nios2: Include proper header fileSebastian Huber2013-09-031-1/+1
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* score: Simplify <rtems/score/cpuatomic.h>WeiY2013-08-2817-510/+102
| | | | Add proper license and copyright.
* arm: Make barrier operations more visibleSebastian Huber2013-08-221-10/+15
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* powerpc: Fix _CPU_Context_validate()Sebastian Huber2013-08-131-1/+1
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* sparc: Make _CPU_ISR_Dispatch_disable per-CPUSebastian Huber2013-08-092-17/+21
| | | | This variable must be available for each processor in the system.
* sparc: Move _CPU_Context_switch(), etc.Sebastian Huber2013-08-091-224/+0
| | | | | | Move the _CPU_Context_switch(), _CPU_Context_restore() and _CPU_Context_switch_to_first_task_smp() code since the method to obtain the processor index is BSP specific.
* arm: Per-CPU thread dispatch disableSebastian Huber2013-08-091-51/+25
| | | | Interrupt support for per-CPU thread dispatch disable level.
* score: Per-CPU thread dispatch disable levelSebastian Huber2013-08-094-17/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
* score/cpu: Add CPU_Per_CPU_controlSebastian Huber2013-08-0918-2/+123
| | | | Add CPU port specific per-CPU control.
* arm: Fix ISR level context initializationSebastian Huber2013-08-051-1/+2
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* arm: Fix CPU_MODES_INTERRUPT_MASKSebastian Huber2013-08-052-4/+6
| | | | | The set of interrupt levels must be a continuous range of non-negative integers starting at zero.
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