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* riscv32: Add missing preinstall.amSebastian Huber2017-10-281-0/+57
| | | | Update #3109.
* cpukit: Add basic riscv32 architecture port v3Hesham Almatary2017-10-2817-0/+3446
| | | | | | | Limitations: * NO FPU support [TODO] Update #3109
* Add riscv32 to autotools files v3Hesham Almatary2017-10-281-0/+1
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* powerpc: PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORESebastian Huber2017-08-221-0/+5
| | | | | | | In 64-bit mode, the linker must have the ability to restore the TOC pointer after an external function call. Update #3082.
* powerpc: Add 64-bit context/interrupt supportSebastian Huber2017-08-226-187/+263
| | | | Update #3082.
* powerpc: 64-bit _CPU_Context_Initialize() supportSebastian Huber2017-08-221-2/+2
| | | | Update #3082.
* powerpc: 64-bit support for CPU_SIZEOF_POINTERSebastian Huber2017-08-221-0/+4
| | | | Update #3082.
* powerpc: ppc_interrupt_get_disable_mask()Sebastian Huber2017-08-221-1/+1
| | | | | | Fix warning on 64-bit PowerPC. Update #3082.
* powerpc: Add register definesSebastian Huber2017-08-221-0/+16
| | | | Update #3082.
* arm: Use ARM code on Thumb 1 targetsSebastian Huber2017-08-101-1/+1
| | | | Update #3093.
* arm: Validate IT[7:0] bit field of PSRSebastian Huber2017-08-101-1/+25
| | | | Update #3093.
* powerpc: Add register definesSebastian Huber2017-07-311-0/+26
| | | | | Update #3082. Update #3085.
* bsp/t32mppc: Add SMP supportSebastian Huber2017-07-281-0/+3
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* sparc: Add lazy floating point switchSebastian Huber2017-07-256-219/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus, from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically, the deferred floating point switch was used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus, in case an interrupt handler uses the floating point unit then this will result in a trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). In uniprocessor configurations, a lazy floating point context switch is used. In case an active floating point thread is interrupted (PSR[EF] == 1) and a thread dispatch is carried out, then this thread is registered as the floating point owner. When a floating point owner is present during a context switch, the floating point unit is disabled for the heir thread (PSR[EF] == 0). The floating point disabled trap checks that the use of the floating point unit is allowed and saves/restores the floating point context on demand. Update #3077.
* sparc: Rename SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2017-07-253-28/+30
| | | | | | | Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH. Update comment. Update #3077.
* score: Add optional _CPU_Context_Destroy()Sebastian Huber2017-07-251-0/+19
| | | | Update #3077.
* sparc: Add assembly workaround for LEON3FT B2BST errataDaniel Cederman2017-07-173-0/+33
| | | | | | | | | | | | | | | This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc, and -mfix-ut699 GCC flags that prevents the sensitive sequences from being generated. Update #3057.
* arm: Fix ARMv7-M interrupt processingSebastian Huber2017-07-042-30/+48
| | | | | | | | | | | | Right after a "msr basepri_max, %[basepri]" instruction an interrupt service may still take place (observed at least on Cortex-M7). However, pendable service calls that are activated during this interrupt service may be delayed until interrupts are enable again. The _ARMV7M_Pendable_service_call() did not check that a thread dispatch is allowed. Move this test from _ARMV7M_Interrupt_service_leave() to _ARMV7M_Pendable_service_call(). Update #3060.
* powerpc: Fix PPC_CONTEXT_VOLATILE_SIZESebastian Huber2017-06-201-0/+4
| | | | Account for legacy AltiVec context.
* powerpc: Fix TLS supportSebastian Huber2017-06-201-10/+11
| | | | | Do not zero the GPR2 in the thread context via dcbz instructions. Bug was introduced by 32b4a0c42704f0076da8e2d5411290f55d1b2965.
* i386: Support thread-local storage (TLS)Sebastian Huber2017-06-123-7/+43
| | | | Update #2468.
* i386: Move _CPU_Context_Initialize()Sebastian Huber2017-06-092-46/+65
| | | | Update #2468.
* Simplify TLS support in context switchSebastian Huber2017-06-091-11/+2
| | | | | | There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
* build-system: Parallel build all subdirs.Chris Johns2017-05-241-1/+1
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* arm: Fix profiling support of Thumb-1 targetsSebastian Huber2017-05-231-1/+3
| | | | Update #2751.
* score/cpu/or1k/rtems/score/cpu.h: Fix printf() format warningJoel Sherrill2017-04-251-1/+3
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* score/cpu/or1k/or1k-exception-frame-print.c: Fix printf() format warningJoel Sherrill2017-04-251-2/+4
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* moxie/rtems/score/cpu.h: Fix printf() format warningJoel Sherrill2017-04-251-1/+1
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* epiphany/rtems/score/cpu.h: Fix printf() format warningJoel Sherrill2017-04-251-1/+3
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* epiphany/cpu.c: Fix typo to eliminate warningJoel Sherrill2017-04-251-2/+2
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* epiphany/cpu.c: Fix not a prototype warningJoel Sherrill2017-04-241-2/+2
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* cpukit/../i386/cpu.c: Use inttypes.h to fix 1 warning.Cillian O'Donnell2017-04-141-1/+2
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* arm: Optimize context switchSebastian Huber2017-03-283-78/+55
| | | | | | | | | Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the interrupts are always enabled during a context switch even after interrupt processing (see #2751). Remove the CPSR from the context control since it contains only volatile bits. Close #2954.
* arm: Fix CPU context validation for Cortex-R4Sebastian Huber2017-03-092-7/+3
| | | | Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
* arm: Remove legacy execption supportSebastian Huber2017-03-084-301/+0
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* powerpc: Fix PPC_CONTEXT_VOLATILE_SIZESebastian Huber2017-03-061-1/+1
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* sparc: Fix volatile clobberSebastian Huber2017-02-031-1/+1
| | | | | | | Do not adjust the stack pointer, since this is already done by the restor instruction. Update #2270.
* bsps/arm: Fix Cortex-M DWT CPU counter.Christian Mauderer2017-01-301-1/+45
| | | | | | | | | It is necessary to enable the DWT using a special initialization sequence before the CYCCNT can be enabled. See for example the RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h. Note that this problem only occurs if no debugger is connected. A debugger most likely already enables the necessary module.
* score: Delete _CPU_Context_Fp_start()Sebastian Huber2017-01-2616-271/+14
| | | | | | | | | | Since the FP area pointer is passed by reference in _CPU_Context_Initialize_fp() the optional FP area adjustment via _CPU_Context_Fp_start() is superfluous. It is also wrong with respect to memory management, e.g. pointer passed to _Workspace_Free() may be not the one returned by _Workspace_Allocate(). Close #1400.
* Adding ARM VFP V2 supportKevin Kirspel2017-01-241-0/+6
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* sparc: Relax CPU_STACK_ALIGNMENTSebastian Huber2017-01-241-12/+3
| | | | Close #2352.
* Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIANSebastian Huber2017-01-2417-310/+0
| | | | | | Use de-facto standard BYTE_ORDER instead. Close #2803.
* score: Introduce _Internal_error()Sebastian Huber2016-12-121-1/+1
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* score: Remove fatal is internal indicatorSebastian Huber2016-12-094-8/+4
| | | | | | | | | The fatal is internal indicator is redundant since the fatal source and error code uniquely identify a fatal error. Keep the fatal user extension is internal parameter for backward compatibility and set it to false always. Update #2825.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-022-0/+5
| | | | Update #2751.
* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+3
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* arm: Fix _CPU_ISR_Is_enabled() for ARMv7-MSebastian Huber2016-11-241-1/+1
| | | | Update #2811.
* score: Robust thread dispatchSebastian Huber2016-11-2317-0/+47
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-212-10/+40
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
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