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* cpukit: add and use CPU_Uint32ptr typeGedare Bloom2015-03-1619-0/+59
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* score/or1k: Fix warnings. Add missing prototypesHesham ALMatary2015-03-131-0/+4
| | | | Closes #2304
* cpukit: Remove old DESCRIPTION: in commentsJoel Sherrill2015-03-111-6/+4
| | | | These were remnants of pre-Doxygen comment style.
* or1k/rtems/score/cpu.h: Add no_return attribute to _CPU_Context_restoreJoel Sherrill2015-03-091-1/+1
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* cpukit/score/cpu/sh/context.c: Correct name of _CPU_Context_switchJoel Sherrill2015-03-091-1/+1
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* or1k: Correct _CPU_Thread_Idle_body prototypeJoel Sherrill2015-03-092-2/+2
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* score: Delete unused CPU_UNROLL_ENQUEUE_PRIORITYSebastian Huber2015-03-0519-333/+0
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* score/cpu/or1k: Add cpuatomic.h to fix broken build.Hesham ALMatary2015-03-043-2/+19
| | | | | 4e3d9a4d6c76fba8e31138d503f736405dafc213 broke or1k, cpuatomic.h has to be added to all architectures.
* or1k/or1k-exception-default.c: Eliminate dependency on BSP provided .h fileHesham ALMatary2015-03-031-1/+0
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* ARM: Fix _ARMV4_Exception_fiq_defaultMartin Galvan2015-02-271-0/+8
| | | | | | | | In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when it gets loaded back to the CPSR in save_more_context it won't re-enable the FIQs. Tested on a TMS570LS3137.
* sparc64: fix copyright notices.Gedare Bloom2015-02-231-12/+1
| | | | | The sparc64 port had some incorrect copyright notices affixed to source code files.
* bfin: do not reset dispatch neededGedare Bloom2015-02-191-2/+0
| | | | | | | | Closes #2148 Fix suggested in above ticket. On examination, the assembly appears to be clearing the DISPATCH_NEEDED flag before jumping to _Thread_Dispatch.
* score: Add _CPU_SMP_Prepare_start_multitasking()Sebastian Huber2015-02-175-6/+20
| | | | Update #2268.
* or1k/cpu.c: Eliminate dependency on BSP provided headerHesham ALMatary2015-02-101-2/+7
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* powerpc: Fix AltiVec VSCR save/restoreSebastian Huber2015-01-203-10/+13
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* powerpc: AltiVec and FPU context supportSebastian Huber2015-01-135-8/+700
| | | | | | | | | | | Add AltiVec and FPU support to the Context_Control in case we use the e6500 multilib. Add PPC_MULTILIB_ALTIVEC and PPC_MULTILIB_FPU multilib defines. Add non-volatile AltiVec and FPU context to Context_Control. Add save/restore of non-volatile AltiVec and FPU to _CPU_Context_switch(). Add save/restore of volatile AltiVec and FPU context to the exception code. Adjust data cache optimizations for the new context and cache line size.
* nios2: Disable assembler warningSebastian Huber2015-01-131-2/+3
| | | | Close #2232.
* arm: Fix compile error for ARMv6-M multilibSebastian Huber2015-01-092-2/+5
| | | | | | | ARMv6-M is not supported since we cannot directly use the ARMv7-M code due to some inline assembler statements. Close #2231.
* powerpc: Add AltiVec register ASM definesSebastian Huber2015-01-091-0/+32
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* powerpc: Use PPC_HAS_FPUSebastian Huber2015-01-091-0/+2
| | | | Provide floating point context support only if PPC_HAS_FPU == 1.
* powerpc: Add PPC_STACK_ALIGN_POWERSebastian Huber2015-01-091-16/+6
| | | | Simplify PPC_STACK_ALIGNMENT definition.
* powerpc: Set PPC_DEFAULT_CACHE_LINE_SIZE for e6500Sebastian Huber2015-01-092-6/+12
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* powerpc: Use PPC_DEFAULT_CACHE_LINE_SIZESebastian Huber2015-01-092-3/+4
| | | | | Use it for the default PPC_CACHE_ALIGNMENT. Use it for PPC_STRUCTURE_ALIGNMENT.
* powerpc: Delete _CPU_IRQ_infoSebastian Huber2015-01-091-16/+0
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* powerpc: Use alternate time base for CPU counterSebastian Huber2015-01-091-3/+3
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* sparc64: put each copyright on one lineGedare Bloom2014-12-085-16/+11
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* i386: doxygen and comments related to VESA real mode framebufferJan Dolezal2014-12-042-17/+26
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* SPARC: optimize IRQ enable & disableDaniel Hellstrom2014-12-041-2/+16
| | | | | | | | | | | | | | | | * Coding style cleanups. * Use OS reserved trap 0x89 for IRQ Disable * Use OS reserved trap 0x8A for IRQ Enable * Add to SPARC CPU supplement documentation This will result in faster Disable/Enable code since the system trap handler does not need to decode which function the user wants. Besides the IRQ disable/enabled can now be inline which avoids the caller to take into account that o0-o7+g1-g4 registers are destroyed by trap handler. It was also possible to reduce the interrupt trap handler by five instructions due to this.
* arm: Use CPU_TIMESTAMP_USE_STRUCT_TIMESPECSebastian Huber2014-11-251-1/+1
| | | | | | | Converting 64-bit nanoseconds values into the common struct timeval or struct timespec formats requires a 64-bit division to get the seconds value. Performance analysis of high network loads revealed that this is too costly on ARM.
* score: i386: functions converting real mode pointer to physical address and backJan Dolezal2014-11-202-0/+75
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* cpukit/score/cpu/lm32/irq.c: Fix warningJoel Sherrill2014-10-201-0/+6
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* score/cpu/lm32/rtems/score/cpu.h: Fix set but not used warningJoel Sherrill2014-10-201-0/+3
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* score/cpu/i386/rtems/score/cpu.h: Fix set but not used warningJoel Sherrill2014-10-201-0/+1
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* bfin libcpu and libbsp: Fix warningsJoel Sherrill2014-10-161-0/+1
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* h8300/cpu_asm.S: Correct register size suffix for loading DISPATCH_NEEDEDJoel Sherrill2014-10-151-1/+1
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* sparc64: fix warnings in cpukit/score/cpuGedare Bloom2014-10-132-4/+2
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* score/cpu/m32c: Fix warningsJoel Sherrill2014-10-132-4/+5
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* arm: Fix warningSebastian Huber2014-10-101-0/+6
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* m32r/cpu_asm.c: Add prototype to fix warningJoel Sherrill2014-10-091-0/+5
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* m32r/rtems/score/cpu.h: Fix macros to avoid warningsJoel Sherrill2014-10-091-18/+20
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* h8300/rtems/score/cpu.h: Fix macros to avoid warningsJoel Sherrill2014-10-091-6/+17
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* avr/rtems/score/cpu.h: Fix macros to avoid warningsJoel Sherrill2014-10-091-6/+5
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* m68k/rtems/score/cpu.h: _CPU_Context_Restart_self needed ↵Joel Sherrill2014-10-091-1/+1
| | | | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
* moxiertems/score/cpu.h: _CPU_Context_switch needed ↵Joel Sherrill2014-10-091-9/+22
| | | | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE plus fix warnings on unimplemented ISR enable/disable
* arm/rtems/score/cpu.h: _ARMV7M_Start_multitasking needed ↵Joel Sherrill2014-10-091-1/+2
| | | | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
* nios2-iic-irq.c: Fix warningsJoel Sherrill2014-10-091-0/+6
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* nios2-iic-irq.c: Include <rtems/score/interr.h> so it buildsJoel Sherrill2014-10-091-0/+1
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* SPARC: Fatal_halt use source and exit codesDaniel Hellstrom2014-10-061-8/+2
| | | | | | | | | | | | | | | The Fatal_halt handler now have two options, either halt as before or enter system error state to return to debugger or simulator. The exit-code is now also propagated to the debugger which is very useful for testing. The CPU_Fatal_halt handler was split up into two, since the only the LEON3 support the CPU power down. The LEON3 halt now uses the power-down instruction to save CPU power. This doesn't stop a potential watch-dog timer from expiring.
* or1k fix bug: Initialize thread context with higher stack address.Hesham ALMatary2014-09-291-2/+3
| | | | | | Since or1k architecture stack grows down, threads should be initialized with high stack addresses instead of lower ones. This is done in _CPU_Context_Initialize function.
* m68k: Use CPU_TIMESTAMP_USE_STRUCT_TIMESPECSebastian Huber2014-09-231-1/+1
| | | | | | | Converting 64-bit nanoseconds values into the common struct timeval or struct timespec formats requires a 64-bit division to get the seconds value. Performance analysis of high network loads revealed that this is too costly on PowerPC.
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