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* Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIANSebastian Huber2017-01-2417-310/+0
| | | | | | Use de-facto standard BYTE_ORDER instead. Close #2803.
* score: Introduce _Internal_error()Sebastian Huber2016-12-121-1/+1
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* score: Remove fatal is internal indicatorSebastian Huber2016-12-094-8/+4
| | | | | | | | | The fatal is internal indicator is redundant since the fatal source and error code uniquely identify a fatal error. Keep the fatal user extension is internal parameter for backward compatibility and set it to false always. Update #2825.
* score: Fix ARM and PowerPC context initializationSebastian Huber2016-12-022-0/+5
| | | | Update #2751.
* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+3
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* arm: Fix _CPU_ISR_Is_enabled() for ARMv7-MSebastian Huber2016-11-241-1/+1
| | | | Update #2811.
* score: Robust thread dispatchSebastian Huber2016-11-2317-0/+47
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* arm: Fix _ARMV4_Exception_interruptSebastian Huber2016-11-231-1/+1
| | | | | | | Use the right register to determine if a thread dispatch is allowed and necessary. Update #2751.
* arm: Fix Thumb-1 targetsSebastian Huber2016-11-212-10/+40
| | | | | | | We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
* sparc64: Fix _CPU_ISR_Is_enabled()Sebastian Huber2016-11-211-1/+1
| | | | Update #2820.
* nios2: Fix _CPU_ISR_Is_enabled()Sebastian Huber2016-11-211-4/+4
| | | | Close #2818.
* arm: Fix ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLESebastian Huber2016-11-211-2/+4
| | | | Close #2816.
* bfin: ASM compatibility for <rtems/score/cpu.h>Sebastian Huber2016-11-211-2/+2
| | | | Close #2817.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-1818-2/+112
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* powerpc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-2/+5
| | | | Update #2751.
* arm: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-184-31/+94
| | | | Update #2751.
* arm: Simplify _ARMV4_Exception_interruptSebastian Huber2016-11-181-18/+22
| | | | | Move profiling code closer to bsp_interrupt_disable() to allow re-use of r9 later.
* arm: Use local labelsSebastian Huber2016-11-181-9/+9
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* sparc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-22/+5
| | | | Update #2751.
* score: Allow interrupts during thread dispatchSebastian Huber2016-11-181-3/+7
| | | | | | | | | Use a processor-specific interrupt frame during context switches in case the executing thread is longer executes on the processor and the heir thread is about to start execution. During this period we must not use a thread stack for interrupt processing. Update #2809.
* score: Add Per_CPU_Control::Interrupt_frameSebastian Huber2016-11-181-5/+0
| | | | Update #2809.
* arm: Provide CPU_Interrupt_frame for ARMv4Sebastian Huber2016-11-182-3/+55
| | | | Update #2809.
* powerpc: Add up to date CPU_Interrupt_frameSebastian Huber2016-11-182-6/+386
| | | | | | | Rename ppc_exc_min_frame to CPU_Interrupt_frame. Move it and the corresponding defines to <rtems/score/cpuimpl.h>. Update #2809.
* powerpc: Move legacy CPU_Interrupt_frameSebastian Huber2016-11-181-31/+0
| | | | | | | The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx support. Move it to here. Update #2809.
* sparc: Move CPU_Interrupt_frame related definesSebastian Huber2016-11-185-54/+58
| | | | | | Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>. Update #2809.
* sparc: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-184-26/+26
| | | | | | | | Rename SPARC-specific CPU_Minimum_stack_frame to SPARC_Minimum_stack_frame. Rename SPARC-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* sparc64: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-183-30/+30
| | | | | | | | Rename SPARC64-specific CPU_Minimum_stack_frame to SPARC64_Minimum_stack_frame. Rename SPARC64-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-1814-14/+14
| | | | Update #2808.
* score: Move CPU_PER_CPU_CONTROL_SIZESebastian Huber2016-11-1834-94/+125
| | | | | Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to <rtems/score/cpuimpl.h> to hide it from <rtems.h>.
* score: Remove obsolete definesSebastian Huber2016-11-1817-270/+0
| | | | The thread dispatch inline option is no longer used.
* arm: Use TPIDRPRW for current per-CPU controlSebastian Huber2016-11-184-9/+30
| | | | | | Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
* powerpc: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-101-0/+27
| | | | | | | | Add _CPU_Get_current_per_CPU_control() on SMP configurations. Use SPRG0 for the current per-CPU control. This reduces the code size by three instructions and is slightly faster. Update #2805.
* score: Move _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-104-28/+28
| | | | | Move _CPU_Get_current_per_CPU_control() from <rtems/score/cpu.h> to <rtems/score/cpuimpl.h>.
* sparc: Provide _CPU_Get_thread_executing()Sebastian Huber2016-11-071-0/+4
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* score: Add optional _CPU_Get_thread_executing()Sebastian Huber2016-11-071-0/+12
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* score: Add <rtems/score/cpuimpl.h>Sebastian Huber2016-11-0751-0/+595
| | | | | | The aim of this file is to encapsulate CPU port implementation details. This helps to hide implementation details from <rtems.h> which indirectly includes <rtems/score/cpu.h>.
* score/arm: Correct logic to select 64 byte cache line maximum size for Cortex-A.Pavel Pisa2016-10-041-2/+2
| | | | | | | | The use of actual cache line max bytes and minimum required alignment in architecture but not-BSP dependent code could be problematic because there exists even ARM instruction set implementations with 128 byte line length and real maximum can be quite problematic to say. But actually supported ARM BSPs should be OK with these values.
* score: Fix C/C++ compatibility issueSebastian Huber2016-09-2316-59/+5
| | | | | | | Only use CPU_Per_CPU_control if it contains at least one filed. In GNU C empty structures have a size of zero. In C++ structures have a non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not used anymore.
* stackchk: Use a const pattern to checkSebastian Huber2016-09-081-1/+9
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* arm: Add VFP context validate support for ARMv5Kevin Kirspel2016-08-192-5/+11
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* score: Fix printk() format specifiersSebastian Huber2016-07-261-2/+5
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* score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.Pavel Pisa2016-07-042-2/+9
| | | | | Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment.
* arm/score and shared: define ARM hypervisor mode and alternate vector table ↵Pavel Pisa2016-07-041-0/+1
| | | | | | | | | base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example).
* score: _CPU_SMP_Send_interrupt() documentationSebastian Huber2016-06-291-4/+0
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* sparc: Optimize CPU counter supportSebastian Huber2016-06-225-38/+98
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* sparc: Rework CPU counter supportSebastian Huber2016-06-214-26/+88
| | | | | Rework CPU counter support to enable use of the GR740 up-counter via %asr22 and %asr23.
* i386: Fix _CPU_Bitfield_Find_first_bit()Sebastian Huber2016-06-131-6/+5
| | | | Bug introduced by b04b76c6a0c87ffc9670d356e793108411ce355a.
* score: Simplify priority bit map implementationSebastian Huber2016-06-0820-41/+2
| | | | | | | | | | The priority bit map can deal with a maximum of 256 priority values ranging from 0 to 255. Consistently use an unsigned int for computation, due to the usual integer promotion rules. Make Priority_bit_map_Word definition architecture-independent and define it to uint16_t. This was already the case for all architectures except PowerPC. Adjust the PowerPC bitmap support accordingly.
* score: Delete CPU_USE_GENERIC_BITFIELD_DATASebastian Huber2016-06-0818-47/+4
| | | | | | Rename __log2table into _Bitfield_Leading_zeros since it acually returns the count of leading zeros of an 8-bit integer. The value for zero is a bit odd. Provide it unconditionally.
* powerpc: Define bitmap defines to FALSESebastian Huber2016-06-081-0/+4
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