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* doxygen: score: Add RISC-V CPU architecture groupAndreas Dachsberger2019-04-021-1/+1
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-261-1/+1
| | | | Update #3706.
* riscv: Rework exception handlingSebastian Huber2018-07-251-28/+47
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* riscv: Add LADDR assembler defineSebastian Huber2018-07-061-1/+1
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Clear reservationsSebastian Huber2018-07-051-0/+2
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-291-0/+50
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-291-89/+51
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
| | | | Update #3433.
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-291-45/+60
| | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433.
* riscv: Format assembler filesSebastian Huber2018-06-271-167/+168
| | | | | | Use tabs to match the GCC generated assembler output. Update #3433.
* cpukit: RISC-V - make riscv32 code work for riscv64 - v2Hesham Almatary2017-11-011-0/+221
* Use #ifdefs for 32/64 bit code * Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size) * Move the code to a new shared riscv folder to be shared between riscv32 and riscv64 * Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv Update #3109
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