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* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-181-0/+2
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* riscv: Clear reservationsSebastian Huber2018-07-051-0/+2
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
| | | | Update #3433.
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
| | | | Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-291-9/+37
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-291-0/+1
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-291-62/+29
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-291-12/+0
| | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433.
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-291-8/+15
| | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-281-0/+1
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* bsp/riscv: Load global pointerSebastian Huber2018-06-271-2/+0
| | | | Update #3433.
* riscv: Format assembler filesSebastian Huber2018-06-271-93/+93
| | | | | | Use tabs to match the GCC generated assembler output. Update #3433.
* cpukit: RISC-V - make riscv32 code work for riscv64 - v2Hesham Almatary2017-11-011-0/+136
* Use #ifdefs for 32/64 bit code * Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size) * Move the code to a new shared riscv folder to be shared between riscv32 and riscv64 * Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv Update #3109
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