summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/riscv/riscv-context-initialize.c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* riscv: Fix fcsr initializationSebastian Huber2018-07-021-1/+10
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-291-0/+8
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-291-6/+2
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-291-6/+6
| | | | Update #3433.
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-291-4/+0
| | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433.
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
| | | | | | | | | | The RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md does not mention that this is a frame pointer. Update #3433.
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
| | | | Update #3433.
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
| | | | | | | | Do not clear the complete thread context. Initialize only the necessary members. The Context_Control::is_executing member must be preserved across _CPU_Context_Initialize() calls. Update #3433.
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-291-2/+1
| | | | | | | | | | | The current ABI says that there is no stack red zone: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md "Procedures must not rely upon the persistence of stack-allocated data whose addresses lie below the stack pointer." Update #3433.
* cpukit: RISC-V - make riscv32 code work for riscv64 - v2Hesham Almatary2017-11-011-0/+67
* Use #ifdefs for 32/64 bit code * Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size) * Move the code to a new shared riscv folder to be shared between riscv32 and riscv64 * Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv Update #3109
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-22 00:21:41 +0000