Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | doxygen: score: Add RISC-V CPU architecture group | Andreas Dachsberger | 2019-04-02 | 1 | -0/+12 |
* | riscv: Rework CPU counter support | Sebastian Huber | 2018-07-27 | 1 | -0/+38 |
* | riscv: Add CLINT and PLIC support | Sebastian Huber | 2018-07-25 | 1 | -5/+45 |
* | riscv: Rework exception handling | Sebastian Huber | 2018-07-25 | 1 | -0/+7 |
* | riscv: New CPU_Exception_frame | Sebastian Huber | 2018-07-25 | 1 | -54/+46 |
* | score: Add _CPU_Instruction_illegal() | Sebastian Huber | 2018-07-23 | 1 | -0/+5 |
* | score: Add _CPU_Instruction_no_operation() | Sebastian Huber | 2018-07-20 | 1 | -0/+5 |
* | score: Move context validation declarations | Sebastian Huber | 2018-07-20 | 1 | -0/+4 |
* | riscv: Clear reservations | Sebastian Huber | 2018-07-05 | 1 | -0/+11 |
* | riscv: Fix fcsr initialization | Sebastian Huber | 2018-07-02 | 1 | -0/+9 |
* | riscv: Add floating-point support | Sebastian Huber | 2018-06-29 | 1 | -0/+131 |
* | riscv: Optimize context switch and interrupts | Sebastian Huber | 2018-06-29 | 1 | -11/+103 |
* | riscv: Remove mstatus from thread context | Sebastian Huber | 2018-06-29 | 1 | -4/+11 |
* | riscv: Enable interrupts during dispatch after ISR | Sebastian Huber | 2018-06-29 | 1 | -0/+4 |
* | riscv: Add _CPU_Get_current_per_CPU_control() | Sebastian Huber | 2018-06-28 | 1 | -0/+15 |
* | riscv: Add dummy SMP support | Sebastian Huber | 2018-06-28 | 1 | -1/+11 |
* | Remove make preinstall | Chris Johns | 2018-01-25 | 1 | -0/+51 |